1 /* $NetBSD: tegra_pciereg.h,v 1.4 2017/09/26 16:12:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_PCIEREG_H 30 #define _ARM_TEGRA_PCIEREG_H 31 32 /* PADS */ 33 #define PADS_REFCLK_CFG0_REG 0xc8 34 35 /* AFI */ 36 #define AFI_AXI_NBAR 9 37 38 #define AFI_AXI_BARi_SZ(i) ((i) < 6 ? \ 39 0x000 + ((i) - 0) * 0x04 : \ 40 0x134 + ((i) - 6) * 0x04) 41 42 #define AFI_AXI_BARi_START(i) ((i) < 6 ? \ 43 0x018 + ((i) - 0) * 0x04 : \ 44 0x140 + ((i) - 6) * 0x04) 45 46 #define AFI_FPCI_BARi(i) ((i) < 6 ? \ 47 0x030 + ((i) - 0) * 0x04 : \ 48 0x14c + ((i) - 6) * 0x04) 49 50 #define AFI_MSI_BAR_SZ_REG 0x60 51 #define AFI_MSI_FPCI_BAR_ST_REG 0x64 52 #define AFI_MSI_AXI_BAR_ST_REG 0x68 53 #define AFI_INTR_MASK_REG 0xb4 54 #define AFI_INTR_CODE_REG 0xb8 55 #define AFI_INTR_SIGNATURE_REG 0xbc 56 #define AFI_SM_INTR_ENABLE_REG 0xc4 57 #define AFI_AFI_INTR_ENABLE_REG 0xc8 58 #define AFI_PCIE_CONFIG_REG 0xf8 59 #define AFI_PEXn_CTRL_REG(n) (0x110 + (n) * 8) 60 #define AFI_PEXn_STATUS_REG(n) (0x114 + (n) * 8) 61 #define AFI_PLLE_CONTROL_REG 0x160 62 #define AFI_PEXBIAS_CTRL_REG 0x168 63 #define AFI_MSG_REG 0x190 64 65 #define AFI_INTR_MASK_MSI __BIT(8) 66 #define AFI_INTR_MASK_INT __BIT(0) 67 68 #define AFI_INTR_CODE_INT_CODE __BITS(4,0) 69 #define AFI_INTR_CODE_SM_MSG 6 70 71 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG __BITS(23,20) 72 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1 0 73 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1 1 74 #define AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(n) __BIT(1 + (n)) 75 76 #define AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN __BIT(4) 77 #define AFI_PEXn_CTRL_REFCLK_EN __BIT(3) 78 #define AFI_PEXn_CTRL_CLKREQ_EN __BIT(1) 79 #define AFI_PEXn_CTRL_RST_L __BIT(0) 80 81 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL __BIT(9) 82 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN __BIT(1) 83 84 #define AFI_PEXBIAS_CTRL_PWRD __BIT(0) 85 86 #define AFI_MSG_INT1 __BITS(27,24) 87 #define AFI_MSG_PM_PME1 __BIT(20) 88 #define AFI_MSG_INT0 __BITS(11,8) 89 #define AFI_MSG_PM_PME0 __BIT(4) 90 91 #endif /* _ARM_TEGRA_PCIEREG_H */ 92