1 /* $NetBSD: tegra_ehci.c,v 1.20 2021/08/07 16:18:44 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.20 2021/08/07 16:18:44 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38
39 #include <dev/usb/usb.h>
40 #include <dev/usb/usbdi.h>
41 #include <dev/usb/usbdivar.h>
42 #include <dev/usb/usb_mem.h>
43 #include <dev/usb/ehcireg.h>
44 #include <dev/usb/ehcivar.h>
45
46 #include <arm/nvidia/tegra_reg.h>
47 #include <arm/nvidia/tegra_var.h>
48 #include <arm/nvidia/tegra_usbreg.h>
49
50 #include <dev/fdt/fdtvar.h>
51
52 #define TEGRA_EHCI_REG_OFFSET 0x100
53
54 static int tegra_ehci_match(device_t, cfdata_t, void *);
55 static void tegra_ehci_attach(device_t, device_t, void *);
56
57 static void tegra_ehci_init(struct ehci_softc *);
58
59 struct tegra_ehci_softc {
60 struct ehci_softc sc;
61 bus_space_tag_t sc_bst;
62 bus_space_handle_t sc_bsh;
63 void *sc_ih;
64 };
65
66 static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
67 int i);
68
69 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc),
70 tegra_ehci_match, tegra_ehci_attach, NULL,
71 ehci_activate, NULL, ehci_childdet);
72
73 static const struct device_compatible_entry compat_data[] = {
74 { .compat = "nvidia,tegra210-ehci" },
75 { .compat = "nvidia,tegra124-ehci" },
76 { .compat = "nvidia,tegra30-ehci" },
77 DEVICE_COMPAT_EOL
78 };
79
80 static int
tegra_ehci_match(device_t parent,cfdata_t cf,void * aux)81 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux)
82 {
83 struct fdt_attach_args * const faa = aux;
84
85 return of_compatible_match(faa->faa_phandle, compat_data);
86 }
87
88 static void
tegra_ehci_attach(device_t parent,device_t self,void * aux)89 tegra_ehci_attach(device_t parent, device_t self, void *aux)
90 {
91 struct tegra_ehci_softc * const sc = device_private(self);
92 struct fdt_attach_args * const faa = aux;
93 char intrstr[128];
94 bus_addr_t addr;
95 bus_size_t size;
96 int error;
97
98 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
99 aprint_error(": couldn't get registers\n");
100 return;
101 }
102
103 sc->sc_bst = faa->faa_bst;
104 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
105 if (error) {
106 aprint_error(": couldn't map USB\n");
107 return;
108 }
109
110 sc->sc.sc_dev = self;
111 sc->sc.sc_bus.ub_hcpriv = &sc->sc;
112 sc->sc.sc_bus.ub_dmatag = faa->faa_dmat;
113 sc->sc.sc_bus.ub_revision = USBREV_2_0;
114 sc->sc.sc_ncomp = 0;
115 sc->sc.sc_flags = EHCIF_ETTF;
116 sc->sc.sc_size = size - TEGRA_EHCI_REG_OFFSET;
117 sc->sc.iot = sc->sc_bst;
118 bus_space_subregion(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_REG_OFFSET,
119 sc->sc.sc_size, &sc->sc.ioh);
120 sc->sc.sc_vendor_init = tegra_ehci_init;
121 sc->sc.sc_vendor_port_status = tegra_ehci_port_status;
122
123 aprint_naive("\n");
124 aprint_normal(": USB\n");
125
126 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
127
128 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
129 aprint_error_dev(self, "failed to decode interrupt\n");
130 return;
131 }
132
133 sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_USB,
134 FDT_INTR_MPSAFE, ehci_intr, &sc->sc, device_xname(self));
135 if (sc->sc_ih == NULL) {
136 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
137 intrstr);
138 return;
139 }
140 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
141
142 error = ehci_init(&sc->sc);
143 if (error) {
144 aprint_error_dev(self, "init failed, error = %d\n", error);
145 return;
146 }
147
148 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
149 CFARGS_NONE);
150 }
151
152 static void
tegra_ehci_init(struct ehci_softc * esc)153 tegra_ehci_init(struct ehci_softc *esc)
154 {
155 struct tegra_ehci_softc * const sc = device_private(esc->sc_dev);
156 uint32_t usbmode;
157
158 usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
159 TEGRA_EHCI_USBMODE_REG);
160
161 const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM);
162 if (cm != TEGRA_EHCI_USBMODE_CM_HOST) {
163 aprint_verbose_dev(esc->sc_dev, "switching to host mode\n");
164 usbmode &= ~TEGRA_EHCI_USBMODE_CM;
165 usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST,
166 TEGRA_EHCI_USBMODE_CM);
167 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
168 TEGRA_EHCI_USBMODE_REG, usbmode);
169 }
170
171 /* Parallel transceiver select */
172 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
173 TEGRA_EHCI_HOSTPC1_DEVLC_REG,
174 __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI,
175 TEGRA_EHCI_HOSTPC1_DEVLC_PTS),
176 TEGRA_EHCI_HOSTPC1_DEVLC_PTS |
177 TEGRA_EHCI_HOSTPC1_DEVLC_STS);
178
179 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG,
180 __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES));
181 }
182
183 static int
tegra_ehci_port_status(struct ehci_softc * ehci_sc,uint32_t v,int i)184 tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i)
185 {
186 struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev);
187 bus_space_tag_t iot = sc->sc_bst;
188 bus_space_handle_t ioh = sc->sc_bsh;
189
190 i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED);
191
192 uint32_t val = bus_space_read_4(iot, ioh,
193 TEGRA_EHCI_HOSTPC1_DEVLC_REG);
194
195 switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) {
196 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS:
197 i |= UPS_FULL_SPEED;
198 break;
199 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS:
200 i |= UPS_LOW_SPEED;
201 break;
202 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS:
203 default:
204 i |= UPS_HIGH_SPEED;
205 break;
206 }
207 return i;
208 }
209