1 /* $NetBSD: tegra30-mc.h,v 1.1.1.4 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H 5 #define DT_BINDINGS_MEMORY_TEGRA30_MC_H 6 7 #define TEGRA_SWGROUP_PTC 0 8 #define TEGRA_SWGROUP_DC 1 9 #define TEGRA_SWGROUP_DCB 2 10 #define TEGRA_SWGROUP_EPP 3 11 #define TEGRA_SWGROUP_G2 4 12 #define TEGRA_SWGROUP_MPE 5 13 #define TEGRA_SWGROUP_VI 6 14 #define TEGRA_SWGROUP_AFI 7 15 #define TEGRA_SWGROUP_AVPC 8 16 #define TEGRA_SWGROUP_NV 9 17 #define TEGRA_SWGROUP_NV2 10 18 #define TEGRA_SWGROUP_HDA 11 19 #define TEGRA_SWGROUP_HC 12 20 #define TEGRA_SWGROUP_PPCS 13 21 #define TEGRA_SWGROUP_SATA 14 22 #define TEGRA_SWGROUP_VDE 15 23 #define TEGRA_SWGROUP_MPCORELP 16 24 #define TEGRA_SWGROUP_MPCORE 17 25 #define TEGRA_SWGROUP_ISP 18 26 27 #define TEGRA30_MC_RESET_AFI 0 28 #define TEGRA30_MC_RESET_AVPC 1 29 #define TEGRA30_MC_RESET_DC 2 30 #define TEGRA30_MC_RESET_DCB 3 31 #define TEGRA30_MC_RESET_EPP 4 32 #define TEGRA30_MC_RESET_2D 5 33 #define TEGRA30_MC_RESET_HC 6 34 #define TEGRA30_MC_RESET_HDA 7 35 #define TEGRA30_MC_RESET_ISP 8 36 #define TEGRA30_MC_RESET_MPCORE 9 37 #define TEGRA30_MC_RESET_MPCORELP 10 38 #define TEGRA30_MC_RESET_MPE 11 39 #define TEGRA30_MC_RESET_3D 12 40 #define TEGRA30_MC_RESET_3D2 13 41 #define TEGRA30_MC_RESET_PPCS 14 42 #define TEGRA30_MC_RESET_SATA 15 43 #define TEGRA30_MC_RESET_VDE 16 44 #define TEGRA30_MC_RESET_VI 17 45 46 #define TEGRA30_MC_PTCR 0 47 #define TEGRA30_MC_DISPLAY0A 1 48 #define TEGRA30_MC_DISPLAY0AB 2 49 #define TEGRA30_MC_DISPLAY0B 3 50 #define TEGRA30_MC_DISPLAY0BB 4 51 #define TEGRA30_MC_DISPLAY0C 5 52 #define TEGRA30_MC_DISPLAY0CB 6 53 #define TEGRA30_MC_DISPLAY1B 7 54 #define TEGRA30_MC_DISPLAY1BB 8 55 #define TEGRA30_MC_EPPUP 9 56 #define TEGRA30_MC_G2PR 10 57 #define TEGRA30_MC_G2SR 11 58 #define TEGRA30_MC_MPEUNIFBR 12 59 #define TEGRA30_MC_VIRUV 13 60 #define TEGRA30_MC_AFIR 14 61 #define TEGRA30_MC_AVPCARM7R 15 62 #define TEGRA30_MC_DISPLAYHC 16 63 #define TEGRA30_MC_DISPLAYHCB 17 64 #define TEGRA30_MC_FDCDRD 18 65 #define TEGRA30_MC_FDCDRD2 19 66 #define TEGRA30_MC_G2DR 20 67 #define TEGRA30_MC_HDAR 21 68 #define TEGRA30_MC_HOST1XDMAR 22 69 #define TEGRA30_MC_HOST1XR 23 70 #define TEGRA30_MC_IDXSRD 24 71 #define TEGRA30_MC_IDXSRD2 25 72 #define TEGRA30_MC_MPE_IPRED 26 73 #define TEGRA30_MC_MPEAMEMRD 27 74 #define TEGRA30_MC_MPECSRD 28 75 #define TEGRA30_MC_PPCSAHBDMAR 29 76 #define TEGRA30_MC_PPCSAHBSLVR 30 77 #define TEGRA30_MC_SATAR 31 78 #define TEGRA30_MC_TEXSRD 32 79 #define TEGRA30_MC_TEXSRD2 33 80 #define TEGRA30_MC_VDEBSEVR 34 81 #define TEGRA30_MC_VDEMBER 35 82 #define TEGRA30_MC_VDEMCER 36 83 #define TEGRA30_MC_VDETPER 37 84 #define TEGRA30_MC_MPCORELPR 38 85 #define TEGRA30_MC_MPCORER 39 86 #define TEGRA30_MC_EPPU 40 87 #define TEGRA30_MC_EPPV 41 88 #define TEGRA30_MC_EPPY 42 89 #define TEGRA30_MC_MPEUNIFBW 43 90 #define TEGRA30_MC_VIWSB 44 91 #define TEGRA30_MC_VIWU 45 92 #define TEGRA30_MC_VIWV 46 93 #define TEGRA30_MC_VIWY 47 94 #define TEGRA30_MC_G2DW 48 95 #define TEGRA30_MC_AFIW 49 96 #define TEGRA30_MC_AVPCARM7W 50 97 #define TEGRA30_MC_FDCDWR 51 98 #define TEGRA30_MC_FDCDWR2 52 99 #define TEGRA30_MC_HDAW 53 100 #define TEGRA30_MC_HOST1XW 54 101 #define TEGRA30_MC_ISPW 55 102 #define TEGRA30_MC_MPCORELPW 56 103 #define TEGRA30_MC_MPCOREW 57 104 #define TEGRA30_MC_MPECSWR 58 105 #define TEGRA30_MC_PPCSAHBDMAW 59 106 #define TEGRA30_MC_PPCSAHBSLVW 60 107 #define TEGRA30_MC_SATAW 61 108 #define TEGRA30_MC_VDEBSEVW 62 109 #define TEGRA30_MC_VDEDBGW 63 110 #define TEGRA30_MC_VDEMBEW 64 111 #define TEGRA30_MC_VDETPMW 65 112 113 #endif 114