1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
3 * All rights reserved.
4 */
5
6 #ifndef __T4_CHIP_TYPE_H__
7 #define __T4_CHIP_TYPE_H__
8
9 /*
10 * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
11 *
12 * V = "4" for T4; "5" for T5, etc. or
13 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
14 * PP = adapter product designation
15 *
16 * We use the "version" (V) of the adpater to code the Chip Version above.
17 */
18 #define CHELSIO_PCI_ID_VER(devid) ((devid) >> 12)
19 #define CHELSIO_PCI_ID_FUNC(devid) (((devid) >> 8) & 0xf)
20 #define CHELSIO_PCI_ID_PROD(devid) ((devid) & 0xff)
21
22 #define CHELSIO_T4 0x4
23 #define CHELSIO_T5 0x5
24 #define CHELSIO_T6 0x6
25
26 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
27 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
28 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
29
30 enum chip_type {
31 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
32 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
33 T4_FIRST_REV = T4_A1,
34 T4_LAST_REV = T4_A2,
35
36 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
37 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
38 T5_FIRST_REV = T5_A0,
39 T5_LAST_REV = T5_A1,
40
41 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
42 T6_FIRST_REV = T6_A0,
43 T6_LAST_REV = T6_A0,
44 };
45
is_t4(enum chip_type chip)46 static inline int is_t4(enum chip_type chip)
47 {
48 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
49 }
50
is_t5(enum chip_type chip)51 static inline int is_t5(enum chip_type chip)
52 {
53 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
54 }
55
is_t6(enum chip_type chip)56 static inline int is_t6(enum chip_type chip)
57 {
58 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
59 }
60 #endif /* __T4_CHIP_TYPE_H__ */
61