1 /* $NetBSD: sunxi_thermal.c,v 1.16 2023/05/02 23:08:58 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Allwinner thermal sensor controller
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: sunxi_thermal.c,v 1.16 2023/05/02 23:08:58 jmcneill Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/device.h>
39 #include <sys/kernel.h>
40 #include <sys/reboot.h>
41
42 #include <dev/sysmon/sysmonvar.h>
43 #include <dev/sysmon/sysmon_taskq.h>
44
45 #include <dev/fdt/fdtvar.h>
46
47 #include <arm/sunxi/sunxi_sid.h>
48
49 #define THS_CTRL0 0x00
50 #define THS_CTRL1 0x04
51 #define ADC_CALI_EN (1 << 17)
52 #define THS_CTRL2 0x40
53 #define SENSOR_ACQ1_SHIFT 16
54 #define SENSOR2_EN (1 << 2)
55 #define SENSOR1_EN (1 << 1)
56 #define SENSOR0_EN (1 << 0)
57 #define THS_INTC 0x44
58 #define THS_INTS 0x48
59 #define THS2_DATA_IRQ_STS (1 << 10)
60 #define THS1_DATA_IRQ_STS (1 << 9)
61 #define THS0_DATA_IRQ_STS (1 << 8)
62 #define SHUT_INT2_STS (1 << 6)
63 #define SHUT_INT1_STS (1 << 5)
64 #define SHUT_INT0_STS (1 << 4)
65 #define ALARM_INT2_STS (1 << 2)
66 #define ALARM_INT1_STS (1 << 1)
67 #define ALARM_INT0_STS (1 << 0)
68 #define THS_ALARM0_CTRL 0x50
69 #define ALARM_T_HOT_MASK 0xfff
70 #define ALARM_T_HOT_SHIFT 16
71 #define ALARM_T_HYST_MASK 0xfff
72 #define ALARM_T_HYST_SHIFT 0
73 #define THS_SHUTDOWN0_CTRL 0x60
74 #define SHUT_T_HOT_MASK 0xfff
75 #define SHUT_T_HOT_SHIFT 16
76 #define THS_FILTER 0x70
77 #define THS_CALIB0 0x74
78 #define THS_CALIB1 0x78
79 #define THS_DATA0 0x80
80 #define THS_DATA1 0x84
81 #define THS_DATA2 0x88
82 #define DATA_MASK 0xfff
83
84 #define A83T_ADC_ACQUIRE_TIME 0x17
85 #define A83T_FILTER 0x4
86 #define A83T_INTC 0x1000
87 #define A83T_TEMP_BASE 2719000
88 #define A83T_TEMP_MUL 1000
89 #define A83T_TEMP_DIV 14186
90 #define A83T_CLK_RATE 24000000
91
92 #define A64_ADC_ACQUIRE_TIME 0x190
93 #define A64_FILTER 0x6
94 #define A64_INTC 0x18000
95 #define A64_TEMP_BASE 2170000
96 #define A64_TEMP_MUL 1000
97 #define A64_TEMP_DIV 8560
98 #define A64_CLK_RATE 4000000
99
100 #define H3_ADC_ACQUIRE_TIME 0x3f
101 #define H3_FILTER 0x6
102 #define H3_INTC 0x191000
103 #define H3_TEMP_BASE 217
104 #define H3_TEMP_MUL 1000
105 #define H3_TEMP_DIV 8253
106 #define H3_TEMP_MINUS 1794000
107 #define H3_CLK_RATE 4000000
108 #define H3_INIT_ALARM 90 /* degC */
109 #define H3_INIT_SHUT 105 /* degC */
110
111 #define H5_ADC_ACQUIRE_TIME 0x1df
112 #define H5_FILTER 0x6
113 #define H5_INTC 0x3a070
114 #define H5_TEMP_DIV 20
115 #define H5_TEMP_BASE_L 233832448
116 #define H5_TEMP_MUL_L 124885
117 #define H5_TEMP_BASE_H_0 271581184
118 #define H5_TEMP_MUL_H_0 152253
119 #define H5_TEMP_BASE_H_1 289406976
120 #define H5_TEMP_MUL_H_1 166723
121 #define H5_CLK_RATE 24000000
122 #define H5_INIT_ALARM 105 /* degC */
123 #define H5_INIT_SHUT 120 /* degC */
124
125 #define TEMP_C_TO_K 273150000
126 #define SENSOR_ENABLE_ALL (SENSOR0_EN|SENSOR1_EN|SENSOR2_EN)
127 #define SHUT_INT_ALL (SHUT_INT0_STS|SHUT_INT1_STS|SHUT_INT2_STS)
128 #define ALARM_INT_ALL (ALARM_INT0_STS)
129
130 #define MAX_SENSORS 3
131
132 #if notyet
133 #define THROTTLE_ENABLE_DEFAULT 1
134
135 /* Enable thermal throttling */
136 static int sunxi_thermal_throttle_enable = THROTTLE_ENABLE_DEFAULT;
137 #endif
138
139 struct sunxi_thermal_sensor {
140 const char *name;
141 const char *desc;
142 int init_alarm;
143 int init_shut;
144 };
145
146 struct sunxi_thermal_config {
147 struct sunxi_thermal_sensor sensors[MAX_SENSORS];
148 int nsensors;
149 uint64_t clk_rate;
150 uint32_t adc_acquire_time;
151 int adc_cali_en;
152 uint32_t filter;
153 uint32_t intc;
154 int (*to_temp)(u_int, uint32_t);
155 uint32_t (*to_reg)(u_int, int);
156 int calib0, calib1;
157 uint32_t calib0_mask, calib1_mask;
158 };
159
160 static int
a83t_to_temp(u_int sensor,uint32_t val)161 a83t_to_temp(u_int sensor, uint32_t val)
162 {
163 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV);
164 }
165
166 static const struct sunxi_thermal_config a83t_config = {
167 .nsensors = 3,
168 .sensors = {
169 [0] = {
170 .name = "cluster0",
171 .desc = "CPU cluster 0 temperature",
172 },
173 [1] = {
174 .name = "cluster1",
175 .desc = "CPU cluster 1 temperature",
176 },
177 [2] = {
178 .name = "gpu",
179 .desc = "GPU temperature",
180 },
181 },
182 .clk_rate = A83T_CLK_RATE,
183 .adc_acquire_time = A83T_ADC_ACQUIRE_TIME,
184 .adc_cali_en = 1,
185 .filter = A83T_FILTER,
186 .intc = A83T_INTC,
187 .to_temp = a83t_to_temp,
188 .calib0_mask = 0xffffffff,
189 .calib1_mask = 0xffffffff,
190 };
191
192 static int
a64_to_temp(u_int sensor,uint32_t val)193 a64_to_temp(u_int sensor, uint32_t val)
194 {
195 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV);
196 }
197
198 static const struct sunxi_thermal_config a64_config = {
199 .nsensors = 3,
200 .sensors = {
201 [0] = {
202 .name = "cpu",
203 .desc = "CPU temperature",
204 },
205 [1] = {
206 .name = "gpu1",
207 .desc = "GPU temperature 1",
208 },
209 [2] = {
210 .name = "gpu2",
211 .desc = "GPU temperature 2",
212 },
213 },
214 .clk_rate = A64_CLK_RATE,
215 .adc_acquire_time = A64_ADC_ACQUIRE_TIME,
216 .filter = A64_FILTER,
217 .intc = A64_INTC,
218 .to_temp = a64_to_temp,
219 };
220
221 static int
h3_to_temp(u_int sensor,uint32_t val)222 h3_to_temp(u_int sensor, uint32_t val)
223 {
224 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV));
225 }
226
227 static uint32_t
h3_to_reg(u_int sensor,int val)228 h3_to_reg(u_int sensor, int val)
229 {
230 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL);
231 }
232
233 static const struct sunxi_thermal_config h3_config = {
234 .nsensors = 1,
235 .sensors = {
236 [0] = {
237 .name = "cpu",
238 .desc = "CPU temperature",
239 .init_alarm = H3_INIT_ALARM,
240 .init_shut = H3_INIT_SHUT,
241 },
242 },
243 .clk_rate = H3_CLK_RATE,
244 .adc_acquire_time = H3_ADC_ACQUIRE_TIME,
245 .filter = H3_FILTER,
246 .intc = H3_INTC,
247 .to_temp = h3_to_temp,
248 .to_reg = h3_to_reg,
249 .calib0_mask = 0xfff,
250 };
251
252 static int
h5_to_temp(u_int sensor,uint32_t val)253 h5_to_temp(u_int sensor, uint32_t val)
254 {
255 int base, mul;
256
257 if (val >= 0x500) {
258 base = H5_TEMP_BASE_L;
259 mul = H5_TEMP_MUL_L;
260 } else {
261 base = sensor == 0 ? H5_TEMP_BASE_H_0 : H5_TEMP_BASE_H_1;
262 mul = sensor == 0 ? H5_TEMP_MUL_H_0 : H5_TEMP_MUL_H_1;
263 }
264
265 return (base - val * mul) >> H5_TEMP_DIV;
266 }
267
268 static uint32_t
h5_to_reg(u_int sensor,int val)269 h5_to_reg(u_int sensor, int val)
270 {
271 int base, mul;
272
273 if (val <= 70) {
274 base = H5_TEMP_BASE_L;
275 mul = H5_TEMP_MUL_L;
276 } else {
277 base = sensor == 0 ? H5_TEMP_BASE_H_0 : H5_TEMP_BASE_H_1;
278 mul = sensor == 0 ? H5_TEMP_MUL_H_0 : H5_TEMP_MUL_H_1;
279 }
280
281 return (base - (val << H5_TEMP_DIV)) / mul;
282 }
283
284 static const struct sunxi_thermal_config h5_config = {
285 .nsensors = 2,
286 .sensors = {
287 [0] = {
288 .name = "cpu",
289 .desc = "CPU temperature",
290 .init_alarm = H5_INIT_ALARM,
291 .init_shut = H5_INIT_SHUT,
292 },
293 [1] = {
294 .name = "gpu",
295 .desc = "GPU temperature",
296 .init_alarm = H5_INIT_ALARM,
297 .init_shut = H5_INIT_SHUT,
298 },
299 },
300 .clk_rate = H5_CLK_RATE,
301 .adc_acquire_time = H5_ADC_ACQUIRE_TIME,
302 .filter = H5_FILTER,
303 .intc = H5_INTC,
304 .to_temp = h5_to_temp,
305 .to_reg = h5_to_reg,
306 };
307
308 static struct device_compatible_entry compat_data[] = {
309 { .compat = "allwinner,sun8i-a83t-ths", .data = &a83t_config },
310 { .compat = "allwinner,sun8i-h3-ths", .data = &h3_config },
311 { .compat = "allwinner,sun50i-a64-ths", .data = &a64_config },
312 { .compat = "allwinner,sun50i-h5-ths", .data = &h5_config },
313
314 /*
315 * DTCOMPAT: Old compat strings. Do not add to this list.
316 */
317 { .compat = "allwinner,sun8i-a83t-ts", .data = &a83t_config },
318 { .compat = "allwinner,sun8i-h3-ts", .data = &h3_config },
319 { .compat = "allwinner,sun50i-a64-ts", .data = &a64_config },
320 { .compat = "allwinner,sun50i-h5-ts", .data = &h5_config },
321 DEVICE_COMPAT_EOL
322 };
323
324 struct sunxi_thermal_softc {
325 device_t dev;
326 int phandle;
327 bus_space_tag_t bst;
328 bus_space_handle_t bsh;
329 const struct sunxi_thermal_config *conf;
330
331 kmutex_t lock;
332 callout_t tick;
333
334 struct sysmon_envsys *sme;
335 envsys_data_t data[MAX_SENSORS];
336 };
337
338 #define RD4(sc, reg) \
339 bus_space_read_4((sc)->bst, (sc)->bsh, (reg))
340 #define WR4(sc, reg, val) \
341 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))
342
343 static int
sunxi_thermal_init(struct sunxi_thermal_softc * sc)344 sunxi_thermal_init(struct sunxi_thermal_softc *sc)
345 {
346 uint32_t calib[2];
347 int error;
348
349 if (sc->conf->calib0_mask != 0 || sc->conf->calib1_mask != 0) {
350 /* Read calibration settings from SRAM */
351 error = sunxi_sid_read_tscalib(calib);
352 if (error != 0)
353 return error;
354
355 calib[0] &= sc->conf->calib0_mask;
356 calib[1] &= sc->conf->calib1_mask;
357
358 /* Write calibration settings to thermal controller */
359 if (calib[0] != 0)
360 WR4(sc, THS_CALIB0, calib[0]);
361 if (calib[1] != 0)
362 WR4(sc, THS_CALIB1, calib[1]);
363 }
364
365 /* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */
366 WR4(sc, THS_CTRL1, ADC_CALI_EN);
367 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
368 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
369
370 /* Enable average filter */
371 WR4(sc, THS_FILTER, sc->conf->filter);
372
373 /* Enable interrupts */
374 WR4(sc, THS_INTS, RD4(sc, THS_INTS));
375 WR4(sc, THS_INTC, sc->conf->intc | SHUT_INT_ALL | ALARM_INT_ALL);
376
377 /* Enable sensors */
378 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
379
380 return 0;
381 }
382
383 static int
sunxi_thermal_gettemp(struct sunxi_thermal_softc * sc,int sensor)384 sunxi_thermal_gettemp(struct sunxi_thermal_softc *sc, int sensor)
385 {
386 uint32_t val;
387
388 val = RD4(sc, THS_DATA0 + (sensor * 4));
389
390 return sc->conf->to_temp(sensor, val);
391 }
392
393 static int
sunxi_thermal_getshut(struct sunxi_thermal_softc * sc,int sensor)394 sunxi_thermal_getshut(struct sunxi_thermal_softc *sc, int sensor)
395 {
396 uint32_t val;
397
398 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
399 val = (val >> SHUT_T_HOT_SHIFT) & SHUT_T_HOT_MASK;
400
401 return sc->conf->to_temp(sensor, val);
402 }
403
404 static void
sunxi_thermal_setshut(struct sunxi_thermal_softc * sc,int sensor,int temp)405 sunxi_thermal_setshut(struct sunxi_thermal_softc *sc, int sensor, int temp)
406 {
407 uint32_t val;
408
409 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
410 val &= ~(SHUT_T_HOT_MASK << SHUT_T_HOT_SHIFT);
411 val |= (sc->conf->to_reg(sensor, temp) << SHUT_T_HOT_SHIFT);
412 WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val);
413 }
414
415 static int
sunxi_thermal_gethyst(struct sunxi_thermal_softc * sc,int sensor)416 sunxi_thermal_gethyst(struct sunxi_thermal_softc *sc, int sensor)
417 {
418 uint32_t val;
419
420 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
421 val = (val >> ALARM_T_HYST_SHIFT) & ALARM_T_HYST_MASK;
422
423 return sc->conf->to_temp(sensor, val);
424 }
425
426 static int
sunxi_thermal_getalarm(struct sunxi_thermal_softc * sc,int sensor)427 sunxi_thermal_getalarm(struct sunxi_thermal_softc *sc, int sensor)
428 {
429 uint32_t val;
430
431 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
432 val = (val >> ALARM_T_HOT_SHIFT) & ALARM_T_HOT_MASK;
433
434 return sc->conf->to_temp(sensor, val);
435 }
436
437 static void
sunxi_thermal_setalarm(struct sunxi_thermal_softc * sc,int sensor,int temp)438 sunxi_thermal_setalarm(struct sunxi_thermal_softc *sc, int sensor, int temp)
439 {
440 uint32_t val;
441
442 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
443 val &= ~(ALARM_T_HOT_MASK << ALARM_T_HOT_SHIFT);
444 val |= (sc->conf->to_reg(sensor, temp) << ALARM_T_HOT_SHIFT);
445 WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val);
446 }
447
448 static void
sunxi_thermal_task_shut(void * arg)449 sunxi_thermal_task_shut(void *arg)
450 {
451 struct sunxi_thermal_softc * const sc = arg;
452
453 device_printf(sc->dev,
454 "WARNING - current temperature exceeds safe limits\n");
455
456 kern_reboot(RB_POWERDOWN, NULL);
457 }
458
459 static void
sunxi_thermal_task_alarm(void * arg)460 sunxi_thermal_task_alarm(void *arg)
461 {
462 struct sunxi_thermal_softc * const sc = arg;
463
464 const int alarm_val = sunxi_thermal_getalarm(sc, 0);
465 const int temp_val = sunxi_thermal_gettemp(sc, 0);
466
467 if (temp_val < alarm_val)
468 pmf_event_inject(NULL, PMFE_THROTTLE_DISABLE);
469 else
470 callout_schedule(&sc->tick, hz);
471 }
472
473 static void
sunxi_thermal_tick(void * arg)474 sunxi_thermal_tick(void *arg)
475 {
476 struct sunxi_thermal_softc * const sc = arg;
477
478 sysmon_task_queue_sched(0, sunxi_thermal_task_alarm, sc);
479 }
480
481 static int
sunxi_thermal_intr(void * arg)482 sunxi_thermal_intr(void *arg)
483 {
484 struct sunxi_thermal_softc * const sc = arg;
485 uint32_t ints;
486
487 mutex_enter(&sc->lock);
488
489 ints = RD4(sc, THS_INTS);
490 WR4(sc, THS_INTS, ints);
491
492 if ((ints & SHUT_INT_ALL) != 0)
493 sysmon_task_queue_sched(0, sunxi_thermal_task_shut, sc);
494
495 if ((ints & ALARM_INT_ALL) != 0) {
496 pmf_event_inject(NULL, PMFE_THROTTLE_ENABLE);
497 sysmon_task_queue_sched(0, sunxi_thermal_task_alarm, sc);
498 }
499
500 mutex_exit(&sc->lock);
501
502 return 1;
503 }
504
505 static void
sunxi_thermal_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)506 sunxi_thermal_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
507 {
508 struct sunxi_thermal_softc * const sc = sme->sme_cookie;
509
510 const int64_t temp = sunxi_thermal_gettemp(sc, edata->private);
511
512 edata->value_cur = temp * 1000000 + TEMP_C_TO_K;
513 edata->state = ENVSYS_SVALID;
514 }
515
516 static int
sunxi_thermal_init_clocks(struct sunxi_thermal_softc * sc)517 sunxi_thermal_init_clocks(struct sunxi_thermal_softc *sc)
518 {
519 struct fdtbus_reset *rst;
520 struct clk *clk;
521 int error;
522
523 clk = fdtbus_clock_get(sc->phandle, "bus");
524 if (clk == NULL) {
525 /* DTCOMPAT */
526 clk = fdtbus_clock_get(sc->phandle, "ahb");
527 }
528 if (clk) {
529 error = clk_enable(clk);
530 if (error != 0)
531 return error;
532 }
533
534 clk = fdtbus_clock_get(sc->phandle, "mod");
535 if (clk == NULL) {
536 /* DTCOMPAT */
537 clk = fdtbus_clock_get(sc->phandle, "ths");
538 }
539 if (clk) {
540 error = clk_set_rate(clk, sc->conf->clk_rate);
541 if (error != 0)
542 return error;
543 error = clk_enable(clk);
544 if (error != 0)
545 return error;
546 }
547
548 rst = fdtbus_reset_get_index(sc->phandle, 0);
549 if (rst) {
550 error = fdtbus_reset_deassert(rst);
551 if (error != 0)
552 return error;
553 }
554
555 return 0;
556 }
557
558 static int
sunxi_thermal_match(device_t parent,cfdata_t cf,void * aux)559 sunxi_thermal_match(device_t parent, cfdata_t cf, void *aux)
560 {
561 struct fdt_attach_args * const faa = aux;
562
563 return of_compatible_match(faa->faa_phandle, compat_data);
564 }
565
566 static void
sunxi_thermal_attach(device_t parent,device_t self,void * aux)567 sunxi_thermal_attach(device_t parent, device_t self, void *aux)
568 {
569 struct sunxi_thermal_softc * const sc = device_private(self);
570 struct fdt_attach_args * const faa = aux;
571 const int phandle = faa->faa_phandle;
572 char intrstr[128];
573 bus_addr_t addr;
574 bus_size_t size;
575 void *ih;
576 int i;
577
578 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
579 aprint_error(": couldn't get registers\n");
580 return;
581 }
582
583 sc->dev = self;
584 sc->phandle = phandle;
585 sc->bst = faa->faa_bst;
586 sc->conf = of_compatible_lookup(phandle, compat_data)->data;
587 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh) != 0) {
588 aprint_error(": couldn't map registers\n");
589 return;
590 }
591 mutex_init(&sc->lock, MUTEX_DEFAULT, IPL_VM);
592 callout_init(&sc->tick, CALLOUT_MPSAFE);
593 callout_setfunc(&sc->tick, sunxi_thermal_tick, sc);
594
595 if (sunxi_thermal_init_clocks(sc) != 0) {
596 aprint_error(": couldn't enable clocks\n");
597 return;
598 }
599
600 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
601 aprint_error(": couldn't decode interrupt\n");
602 return;
603 }
604
605 aprint_naive("\n");
606 aprint_normal(": Thermal sensor controller\n");
607
608 ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
609 sunxi_thermal_intr, sc, device_xname(self));
610 if (ih == NULL) {
611 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
612 intrstr);
613 return;
614 }
615 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
616
617 for (i = 0; i < sc->conf->nsensors; i++) {
618 if (sc->conf->sensors[i].init_alarm > 0)
619 sunxi_thermal_setalarm(sc, i,
620 sc->conf->sensors[i].init_alarm);
621 if (sc->conf->sensors[i].init_shut > 0)
622 sunxi_thermal_setshut(sc, i,
623 sc->conf->sensors[i].init_shut);
624 }
625
626 if (sunxi_thermal_init(sc) != 0) {
627 aprint_error_dev(self, "failed to initialize sensors\n");
628 return;
629 }
630
631 sc->sme = sysmon_envsys_create();
632 sc->sme->sme_name = device_xname(self);
633 sc->sme->sme_cookie = sc;
634 sc->sme->sme_refresh = sunxi_thermal_refresh;
635 for (i = 0; i < sc->conf->nsensors; i++) {
636 sc->data[i].private = i;
637 sc->data[i].units = ENVSYS_STEMP;
638 sc->data[i].state = ENVSYS_SINVALID;
639 strlcpy(sc->data[i].desc, sc->conf->sensors[i].desc,
640 sizeof(sc->data[i].desc));
641 sysmon_envsys_sensor_attach(sc->sme, &sc->data[i]);
642 }
643 sysmon_envsys_register(sc->sme);
644
645 for (i = 0; i < sc->conf->nsensors; i++) {
646 device_printf(self,
647 "%s: alarm %dC hyst %dC shut %dC\n",
648 sc->conf->sensors[i].name,
649 sunxi_thermal_getalarm(sc, i),
650 sunxi_thermal_gethyst(sc, i),
651 sunxi_thermal_getshut(sc, i));
652 }
653 }
654
655 CFATTACH_DECL_NEW(sunxi_thermal, sizeof(struct sunxi_thermal_softc),
656 sunxi_thermal_match, sunxi_thermal_attach, NULL, NULL);
657