1 /* $NetBSD: sunxi_hstimer.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Tobias Nygren <tnn@NetBSD.org>
5 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: sunxi_hstimer.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $");
32
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/timetc.h>
36 #include <dev/fdt/fdtvar.h>
37
38 /* High Speed Timer registers */
39 #define HS_TMR_IRQ_EN_REG 0x0
40 #define HS_TMR_IRQ_EN(n) __BIT(n)
41 #define HS_TMR_IRQ_STAS_REG 0x4
42 #define HS_TMR_STAS_PEND(n) __BIT(n)
43 #define HS_TMR0_CTRL_REG 0x10
44 #define HS_TMR0_CTRL_MODE __BIT(7)
45 #define HS_TMR0_CTRL_CLK_PRESCALE __BITS(6,4)
46 #define HS_TMR0_CTRL_RELOAD __BIT(1)
47 #define HS_TMR0_CTRL_EN __BIT(0)
48 #define HS_TMR0_INTV_LO_REG 0x14
49 #define HS_TMR0_INTV_HI_REG 0x18
50 #define HS_TMR0_CURNT_LO_REG 0x1c
51 #define HS_TMR0_CURNT_HI_REG 0x20
52 #define HS_TMR1_CTRL_REG 0x30
53 #define HS_TMR1_CTRL_MODE __BIT(7)
54 #define HS_TMR1_CTRL_CLK_PRESCALE __BITS(6,4)
55 #define HS_TMR1_CTRL_RELOAD __BIT(1)
56 #define HS_TMR1_CTRL_EN __BIT(0)
57 #define HS_TMR1_INTV_LO_REG 0x34
58 #define HS_TMR1_INTV_HI_REG 0x38
59 #define HS_TMR1_CURNT_LO_REG 0x3c
60 #define HS_TMR1_CURNT_HI_REG 0x40
61 #define HS_TMR2_CTRL_REG 0x50
62 #define HS_TMR2_CTRL_MODE __BIT(7)
63 #define HS_TMR2_CTRL_CLK_PRESCALE __BITS(6,4)
64 #define HS_TMR2_CTRL_RELOAD __BIT(1)
65 #define HS_TMR2_CTRL_EN __BIT(0)
66 #define HS_TMR2_INTV_LO_REG 0x54
67 #define HS_TMR2_INTV_HI_REG 0x58
68 #define HS_TMR2_CURNT_LO_REG 0x5c
69 #define HS_TMR2_CURNT_HI_REG 0x60
70 #define HS_TMR3_CTRL_REG 0x70
71 #define HS_TMR3_CTRL_MODE __BIT(7)
72 #define HS_TMR3_CTRL_CLK_PRESCALE __BITS(6,4)
73 #define HS_TMR3_CTRL_RELOAD __BIT(1)
74 #define HS_TMR3_CTRL_EN __BIT(0)
75 #define HS_TMR3_INTV_LO_REG 0x74
76 #define HS_TMR3_INTV_HI_REG 0x78
77 #define HS_TMR3_CURNT_LO_REG 0x7c
78 #define HS_TMR3_CURNT_HI_REG 0x80
79
80 static const struct device_compatible_entry compat_data[] = {
81 { .compat = "allwinner,sun5i-a13-hstimer" },
82 { .compat = "allwinner,sun6i-a31-hstimer" },
83 { .compat = "allwinner,sun7i-a20-hstimer" },
84 DEVICE_COMPAT_EOL
85 };
86
87 struct sunxi_hstimer_softc {
88 device_t sc_dev;
89 bus_space_tag_t sc_bst;
90 bus_space_handle_t sc_bsh;
91 int sc_phandle;
92 void *sc_ih;
93 struct timecounter sc_tc;
94 };
95
96 #define TIMER_READ(sc, reg) \
97 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
98 #define TIMER_WRITE(sc, reg, val) \
99 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
100
101 static int
sunxi_hstimer_intr(void * arg)102 sunxi_hstimer_intr(void *arg)
103 {
104 struct sunxi_hstimer_softc *sc = arg;
105 uint32_t stas;
106
107 stas = TIMER_READ(sc, HS_TMR_IRQ_STAS_REG);
108 if (stas == 0)
109 return 0;
110 TIMER_WRITE(sc, HS_TMR_IRQ_STAS_REG, stas);
111
112 return 1;
113 }
114
115 static u_int
sunxi_hstimer_get_timecount(struct timecounter * tc)116 sunxi_hstimer_get_timecount(struct timecounter *tc)
117 {
118 struct sunxi_hstimer_softc *sc = tc->tc_priv;
119
120 /*
121 * Timer current value is a 56-bit down counter.
122 * But we only need the lower 32 bits for timecounter.
123 */
124 return ~TIMER_READ(sc, HS_TMR0_CURNT_LO_REG);
125 }
126
127 static int
sunxi_hstimer_match(device_t parent,cfdata_t cf,void * aux)128 sunxi_hstimer_match(device_t parent, cfdata_t cf, void *aux)
129 {
130 struct fdt_attach_args * const faa = aux;
131
132 return of_compatible_match(faa->faa_phandle, compat_data);
133 }
134
135 static void
sunxi_hstimer_attach(device_t parent,device_t self,void * aux)136 sunxi_hstimer_attach(device_t parent, device_t self, void *aux)
137 {
138 struct sunxi_hstimer_softc *sc = device_private(self);
139 struct fdt_attach_args *faa = aux;
140 struct timecounter *tc = &sc->sc_tc;
141 const int phandle = faa->faa_phandle;
142 bus_addr_t addr;
143 bus_size_t size;
144 char intrstr[128];
145 struct clk *clk;
146
147 sc->sc_dev = self;
148 sc->sc_phandle = phandle;
149 sc->sc_bst = faa->faa_bst;
150
151 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL
152 || clk_enable(clk) != 0) {
153 aprint_error(": couldn't enable clock\n");
154 return;
155 }
156
157 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0
158 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
159 aprint_error(": couldn't map registers\n");
160 return;
161 }
162
163 aprint_naive("\n");
164 aprint_normal(": High Speed Timer\n");
165
166 /* Disable IRQs and all timers */
167 TIMER_WRITE(sc, HS_TMR_IRQ_EN_REG, 0);
168 TIMER_WRITE(sc, HS_TMR_IRQ_STAS_REG, TIMER_READ(sc, HS_TMR_IRQ_STAS_REG));
169 /* Enable Timer 0 (timecounter) */
170 TIMER_WRITE(sc, HS_TMR0_CTRL_REG, 0);
171 TIMER_WRITE(sc, HS_TMR0_INTV_LO_REG, ~0u);
172 TIMER_WRITE(sc, HS_TMR0_INTV_HI_REG, ~0u);
173 TIMER_WRITE(sc, HS_TMR0_CTRL_REG,
174 HS_TMR0_CTRL_RELOAD | HS_TMR0_CTRL_EN);
175
176 /* Timecounter setup */
177 tc->tc_get_timecount = sunxi_hstimer_get_timecount;
178 tc->tc_counter_mask = ~0u;
179 tc->tc_frequency = clk_get_rate(clk);
180 tc->tc_name = "hstimer";
181 tc->tc_quality = 300;
182 tc->tc_priv = sc;
183 tc_init(tc);
184
185 if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) {
186 aprint_error_dev(self, "failed to decode interrupt\n");
187 return;
188 }
189 sc->sc_ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,
190 FDT_INTR_MPSAFE, sunxi_hstimer_intr, sc, device_xname(sc->sc_dev));
191 if (sc->sc_ih == NULL) {
192 aprint_error_dev(self, "failed to establish interrupt on %s\n",
193 intrstr);
194 return;
195 }
196 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr);
197 }
198
199 CFATTACH_DECL_NEW(sunxi_hstimer, sizeof(struct sunxi_hstimer_softc),
200 sunxi_hstimer_match, sunxi_hstimer_attach, NULL, NULL);
201
202