1 /* $NetBSD: timerreg.h,v 1.10 2018/01/12 06:01:33 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)timerreg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * Sun-4c counter/timer registers. The timers are implemented within 45 * the cache chip (!). The counter and limit fields below could be 46 * defined as: 47 * 48 * struct { 49 * u_int t_limit:1, // limit reached 50 * t_usec:21, // counter value in microseconds 51 * t_mbz:10; // always zero 52 * }; 53 * 54 * but this is more trouble than it is worth. 55 * 56 * These timers work in a rather peculiar fashion. Most clock counters 57 * run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a 58 * large unsigned number). On the Sun-4c, it counts up to a limit. But 59 * for some reason, when it reaches the limit, it resets to 1, not 0. 60 * Thus, if the limit is set to 4, the counter counts like this: 61 * 62 * 1, 2, 3, 1, 2, 3, ... 63 * 64 * and if we want to divide by N we must set the limit register to N+1. 65 * 66 * Sun-4m counters/timer registers are similar, with these exceptions: 67 * 68 * - the limit and counter registers have changed positions.. 69 * - both limit and counter registers are 22 bits wide, but 70 * they count in 500ns increments (bit 9 being the least 71 * significant bit). 72 * 73 */ 74 #ifndef _LOCORE 75 struct timer_4 { 76 volatile int t_counter; /* counter reg */ 77 volatile int t_limit; /* limit reg */ 78 }; 79 80 struct timerreg_4 { 81 struct timer_4 t_c10; /* counter that interrupts at ipl 10 */ 82 struct timer_4 t_c14; /* counter that interrupts at ipl 14 */ 83 }; 84 85 struct timer_4m { /* counter that interrupts at ipl 10 */ 86 volatile int t_limit; /* limit register */ 87 volatile int t_counter; /* counter register */ 88 volatile int t_limit_nr; /* limit reg, non-resetting */ 89 volatile int t_reserved; 90 volatile int t_cfg; /* a configuration register */ 91 /* 92 * Note: The SparcClassic manual only defines this one bit 93 * I suspect there are more in multi-processor machines. 94 */ 95 #define TMR_CFG_USER 1 96 }; 97 98 struct counter_4m { /* counter that interrupts at ipl 14 */ 99 volatile int t_limit; /* limit register */ 100 volatile int t_counter; /* counter register */ 101 volatile int t_limit_nr; /* limit reg, non-resetting */ 102 volatile int t_ss; /* Start/Stop register */ 103 #define TMR_USER_RUN 1 104 }; 105 #endif /* _LOCORE */ 106 107 #define TMR_LIMIT 0x80000000 /* counter reached its limit */ 108 #define TMR_SHIFT 10 /* shift to obtain microseconds */ 109 #define TMR_MASK 0x1fffff /* 21 bits */ 110 111 /* 112 * Compute a limit that causes the timer to fire every n microseconds. 113 * The Sun4c requires that the timer register be initialized for n+1 114 * microseconds, while the Sun4m requires it be initialized for n. Thus 115 * the two versions of this function. 116 * 117 * Note that the manual for the chipset used in the Sun4m suggests that 118 * the timer be set at n+0.5 microseconds; in practice, this produces 119 * a 50 ppm clock skew, which means that the 0.5 should not be there... 120 */ 121 #define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT) 122 123 #define TMR_SHIFT4M 9 /* shift to obtain microseconds */ 124 #if 1 125 #define tmr_ustolim4m(n) (((2*(n)) + 1) << TMR_SHIFT4M) 126 #else 127 #define tmr_ustolim4m(n) ((n) << TMR_SHIFT) 128 #endif 129 130 /* The number of microseconds represented by a counter register value */ 131 #define tmr_cnttous(c) ((((c) >> TMR_SHIFT) & TMR_MASK) - 1) 132