1 /* $NetBSD: smuio_11_0_0_sh_mask.h,v 1.2 2021/12/18 23:45:23 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _smuio_11_0_0_SH_MASK_HEADER 24 #define _smuio_11_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: smuio_smuio_SmuSmuioDec 28 //SMUSVI0_TEL_PLANE0 29 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0 30 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 31 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL 32 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L 33 //SMUIO_MCM_CONFIG 34 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 35 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 36 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5 37 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6 38 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 39 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL 40 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L 41 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L 42 //CKSVII2C_IC_CON 43 #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 44 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 45 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 46 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 47 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 48 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 49 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 50 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 51 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 52 #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 53 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 54 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 55 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 56 #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 57 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 58 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 59 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 60 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 61 //CKSVII2C_IC_TAR 62 #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 63 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 64 #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 65 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 66 #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 67 #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 68 #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 69 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 70 //CKSVII2C_IC_SAR 71 #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 72 #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 73 //CKSVII2C_IC_HS_MADDR 74 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 75 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 76 //CKSVII2C_IC_DATA_CMD 77 #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 78 #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 79 #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 80 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 81 #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 82 #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 83 #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 84 #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 85 //CKSVII2C_IC_SS_SCL_HCNT 86 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 87 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 88 //CKSVII2C_IC_SS_SCL_LCNT 89 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 90 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 91 //CKSVII2C_IC_FS_SCL_HCNT 92 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 93 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 94 //CKSVII2C_IC_FS_SCL_LCNT 95 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 96 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 97 //CKSVII2C_IC_HS_SCL_HCNT 98 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 99 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 100 //CKSVII2C_IC_HS_SCL_LCNT 101 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 102 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 103 //CKSVII2C_IC_INTR_STAT 104 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 105 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 106 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 107 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 108 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 109 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 110 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 111 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 112 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 113 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 114 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 115 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 116 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 117 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 118 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 119 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 120 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 121 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 122 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 123 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 124 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 125 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 126 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 127 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 128 #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 129 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 130 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 131 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 132 //CKSVII2C_IC_INTR_MASK 133 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 134 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 135 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 136 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 137 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 138 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 139 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 140 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 141 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 142 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 143 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 144 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 145 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 146 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 147 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 148 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 149 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 150 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 151 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 152 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 153 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 154 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 155 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 156 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 157 #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 158 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 159 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 160 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 161 //CKSVII2C_IC_RAW_INTR_STAT 162 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT 0x0 163 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT 0x1 164 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT 0x2 165 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT 0x3 166 #define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 167 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT 0x5 168 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT 0x6 169 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT 0x7 170 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT 0x8 171 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT 0x9 172 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT 0xa 173 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT 0xb 174 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT 0xc 175 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 176 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 177 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK 0x00000002L 178 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK 0x00000004L 179 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK 0x00000008L 180 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 181 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK 0x00000020L 182 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 183 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK 0x00000080L 184 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 185 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK 0x00000200L 186 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK 0x00000400L 187 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 188 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 189 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 190 //CKSVII2C_IC_RX_TL 191 //CKSVII2C_IC_TX_TL 192 //CKSVII2C_IC_CLR_INTR 193 //CKSVII2C_IC_CLR_RX_UNDER 194 //CKSVII2C_IC_CLR_RX_OVER 195 //CKSVII2C_IC_CLR_TX_OVER 196 //CKSVII2C_IC_CLR_RD_REQ 197 //CKSVII2C_IC_CLR_TX_ABRT 198 //CKSVII2C_IC_CLR_RX_DONE 199 //CKSVII2C_IC_CLR_ACTIVITY 200 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT 0x0 201 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK 0x00000001L 202 //CKSVII2C_IC_CLR_STOP_DET 203 //CKSVII2C_IC_CLR_START_DET 204 //CKSVII2C_IC_CLR_GEN_CALL 205 //CKSVII2C_IC_ENABLE 206 #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 207 #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 208 #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 209 #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 210 //CKSVII2C_IC_STATUS 211 #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 212 #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 213 #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 214 #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 215 #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 216 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 217 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 218 #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 219 #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 220 #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 221 #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 222 #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 223 #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 224 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 225 //CKSVII2C_IC_TXFLR 226 //CKSVII2C_IC_RXFLR 227 //CKSVII2C_IC_SDA_HOLD 228 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT 0x0 229 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK 0x00FFFFFFL 230 //CKSVII2C_IC_TX_ABRT_SOURCE 231 232 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT 0x0 233 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT 0x1 234 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT 0x2 235 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT 0x3 236 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK 0x00000001L 237 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK 0x00000002L 238 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK 0x00000004L 239 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK 0x00000008L 240 //CKSVII2C_IC_SLV_DATA_NACK_ONLY 241 //CKSVII2C_IC_DMA_CR 242 //CKSVII2C_IC_DMA_TDLR 243 //CKSVII2C_IC_DMA_RDLR 244 //CKSVII2C_IC_SDA_SETUP 245 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 246 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 247 //CKSVII2C_IC_ACK_GENERAL_CALL 248 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 249 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L 250 //CKSVII2C_IC_ENABLE_STATUS 251 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 252 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT 0x1 253 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2 254 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 255 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK 0x00000002L 256 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L 257 //CKSVII2C_IC_FS_SPKLEN 258 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 259 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL 260 //CKSVII2C_IC_HS_SPKLEN 261 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 262 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL 263 //CKSVII2C_IC_CLR_RESTART_DET 264 //CKSVII2C_IC_COMP_PARAM_1 265 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT 0x0 266 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK 0xFFFFFFFFL 267 //CKSVII2C_IC_COMP_VERSION 268 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 269 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL 270 //CKSVII2C_IC_COMP_TYPE 271 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 272 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL 273 //CKSVII2C1_IC_CON 274 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 275 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 276 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 277 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 278 #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 279 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 280 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 281 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 282 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 283 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 284 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 285 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 286 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 287 #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 288 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 289 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 290 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 291 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 292 //CKSVII2C1_IC_TAR 293 #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 294 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 295 #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 296 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 297 #define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 298 #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 299 #define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 300 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 301 //CKSVII2C1_IC_SAR 302 #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 303 #define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 304 //CKSVII2C1_IC_HS_MADDR 305 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 306 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 307 //CKSVII2C1_IC_DATA_CMD 308 #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 309 #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 310 #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 311 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 312 #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 313 #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 314 #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 315 #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 316 //CKSVII2C1_IC_SS_SCL_HCNT 317 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 318 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 319 //CKSVII2C1_IC_SS_SCL_LCNT 320 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 321 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 322 //CKSVII2C1_IC_FS_SCL_HCNT 323 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 324 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 325 //CKSVII2C1_IC_FS_SCL_LCNT 326 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 327 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 328 //CKSVII2C1_IC_HS_SCL_HCNT 329 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 330 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 331 //CKSVII2C1_IC_HS_SCL_LCNT 332 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 333 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 334 //CKSVII2C1_IC_INTR_STAT 335 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 336 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 337 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 338 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 339 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 340 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 341 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 342 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 343 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 344 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 345 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 346 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 347 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 348 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 349 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 350 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 351 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 352 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 353 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 354 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 355 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 356 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 357 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 358 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 359 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 360 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 361 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 362 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 363 //CKSVII2C1_IC_INTR_MASK 364 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 365 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 366 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 367 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 368 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 369 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 370 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 371 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 372 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 373 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 374 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 375 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 376 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 377 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 378 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 379 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 380 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 381 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 382 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 383 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 384 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 385 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 386 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 387 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 388 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 389 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 390 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 391 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 392 //CKSVII2C1_IC_RAW_INTR_STAT 393 //CKSVII2C1_IC_RX_TL 394 //CKSVII2C1_IC_TX_TL 395 //CKSVII2C1_IC_CLR_INTR 396 //CKSVII2C1_IC_CLR_RX_UNDER 397 //CKSVII2C1_IC_CLR_RX_OVER 398 //CKSVII2C1_IC_CLR_TX_OVER 399 //CKSVII2C1_IC_CLR_RD_REQ 400 //CKSVII2C1_IC_CLR_TX_ABRT 401 //CKSVII2C1_IC_CLR_RX_DONE 402 //CKSVII2C1_IC_CLR_ACTIVITY 403 //CKSVII2C1_IC_CLR_STOP_DET 404 //CKSVII2C1_IC_CLR_START_DET 405 //CKSVII2C1_IC_CLR_GEN_CALL 406 //CKSVII2C1_IC_ENABLE 407 #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 408 #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 409 #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 410 #define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 411 //CKSVII2C1_IC_STATUS 412 #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 413 #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 414 #define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 415 #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 416 #define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 417 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 418 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 419 #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 420 #define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 421 #define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 422 #define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 423 #define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 424 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 425 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 426 //CKSVII2C1_IC_TXFLR 427 //CKSVII2C1_IC_RXFLR 428 //CKSVII2C1_IC_SDA_HOLD 429 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD__SHIFT 0x0 430 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD_MASK 0x00FFFFFFL 431 //CKSVII2C1_IC_TX_ABRT_SOURCE 432 //CKSVII2C1_IC_SLV_DATA_NACK_ONLY 433 //CKSVII2C1_IC_DMA_CR 434 //CKSVII2C1_IC_DMA_TDLR 435 //CKSVII2C1_IC_DMA_RDLR 436 //CKSVII2C1_IC_SDA_SETUP 437 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 438 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 439 //CKSVII2C1_IC_ACK_GENERAL_CALL 440 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 441 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L 442 //CKSVII2C1_IC_ENABLE_STATUS 443 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 444 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED__SHIFT 0x1 445 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2 446 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 447 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED_MASK 0x00000002L 448 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L 449 //SMUIO_MP_RESET_INTR 450 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 451 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 452 //SMUIO_SOC_HALT 453 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 454 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 455 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 456 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 457 //SMUIO_PWRMGT 458 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 459 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 460 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 461 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L 462 //ROM_CNTL 463 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 464 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14 465 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15 466 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16 467 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17 468 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 469 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 470 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 471 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L 472 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L 473 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L 474 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L 475 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L 476 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 477 //PAGE_MIRROR_CNTL 478 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 479 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 480 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 481 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 482 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL 483 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L 484 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 485 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 486 //ROM_STATUS 487 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 488 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 489 //CGTT_ROM_CLK_CTRL0 490 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 491 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 492 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 493 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 494 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 495 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 496 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 497 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 498 //ROM_INDEX 499 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 500 #define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL 501 //ROM_DATA 502 #define ROM_DATA__ROM_DATA__SHIFT 0x0 503 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 504 //ROM_START 505 #define ROM_START__ROM_START__SHIFT 0x0 506 #define ROM_START__ROM_START_MASK 0x00FFFFFFL 507 //ROM_SW_CNTL 508 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 509 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 510 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 511 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 512 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L 513 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L 514 //ROM_SW_STATUS 515 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 516 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 517 //ROM_SW_COMMAND 518 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 519 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 520 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 521 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 522 //ROM_SW_DATA_1 523 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 524 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 525 //ROM_SW_DATA_2 526 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 527 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 528 //ROM_SW_DATA_3 529 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 530 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 531 //ROM_SW_DATA_4 532 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 533 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 534 //ROM_SW_DATA_5 535 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 536 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 537 //ROM_SW_DATA_6 538 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 539 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 540 //ROM_SW_DATA_7 541 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 542 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 543 //ROM_SW_DATA_8 544 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 545 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 546 //ROM_SW_DATA_9 547 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 548 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 549 //ROM_SW_DATA_10 550 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 551 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 552 //ROM_SW_DATA_11 553 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 554 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 555 //ROM_SW_DATA_12 556 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 557 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 558 //ROM_SW_DATA_13 559 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 560 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 561 //ROM_SW_DATA_14 562 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 563 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 564 //ROM_SW_DATA_15 565 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 566 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 567 //ROM_SW_DATA_16 568 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 569 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 570 //ROM_SW_DATA_17 571 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 572 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 573 //ROM_SW_DATA_18 574 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 575 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 576 //ROM_SW_DATA_19 577 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 578 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 579 //ROM_SW_DATA_20 580 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 581 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 582 //ROM_SW_DATA_21 583 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 584 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 585 //ROM_SW_DATA_22 586 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 587 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 588 //ROM_SW_DATA_23 589 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 590 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 591 //ROM_SW_DATA_24 592 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 593 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 594 //ROM_SW_DATA_25 595 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 596 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 597 //ROM_SW_DATA_26 598 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 599 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 600 //ROM_SW_DATA_27 601 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 602 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 603 //ROM_SW_DATA_28 604 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 605 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 606 //ROM_SW_DATA_29 607 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 608 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 609 //ROM_SW_DATA_30 610 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 611 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 612 //ROM_SW_DATA_31 613 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 614 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 615 //ROM_SW_DATA_32 616 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 617 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 618 //ROM_SW_DATA_33 619 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 620 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 621 //ROM_SW_DATA_34 622 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 623 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 624 //ROM_SW_DATA_35 625 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 626 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 627 //ROM_SW_DATA_36 628 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 629 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 630 //ROM_SW_DATA_37 631 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 632 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 633 //ROM_SW_DATA_38 634 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 635 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 636 //ROM_SW_DATA_39 637 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 638 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 639 //ROM_SW_DATA_40 640 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 641 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 642 //ROM_SW_DATA_41 643 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 644 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 645 //ROM_SW_DATA_42 646 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 647 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 648 //ROM_SW_DATA_43 649 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 650 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 651 //ROM_SW_DATA_44 652 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 653 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 654 //ROM_SW_DATA_45 655 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 656 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 657 //ROM_SW_DATA_46 658 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 659 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 660 //ROM_SW_DATA_47 661 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 662 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 663 //ROM_SW_DATA_48 664 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 665 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 666 //ROM_SW_DATA_49 667 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 668 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 669 //ROM_SW_DATA_50 670 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 671 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 672 //ROM_SW_DATA_51 673 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 674 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 675 //ROM_SW_DATA_52 676 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 677 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 678 //ROM_SW_DATA_53 679 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 680 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 681 //ROM_SW_DATA_54 682 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 683 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 684 //ROM_SW_DATA_55 685 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 686 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 687 //ROM_SW_DATA_56 688 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 689 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 690 //ROM_SW_DATA_57 691 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 692 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 693 //ROM_SW_DATA_58 694 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 695 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 696 //ROM_SW_DATA_59 697 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 698 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 699 //ROM_SW_DATA_60 700 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 701 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 702 //ROM_SW_DATA_61 703 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 704 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 705 //ROM_SW_DATA_62 706 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 707 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 708 //ROM_SW_DATA_63 709 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 710 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 711 //ROM_SW_DATA_64 712 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 713 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 714 //SMU_GPIOPAD_SW_INT_STAT 715 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 716 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 717 //SMU_GPIOPAD_MASK 718 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 719 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 720 //SMU_GPIOPAD_A 721 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 722 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 723 //SMU_GPIOPAD_TXIMPSEL 724 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 725 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 726 //SMU_GPIOPAD_EN 727 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 728 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 729 //SMU_GPIOPAD_Y 730 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 731 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 732 //SMU_GPIOPAD_RXEN 733 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 734 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 735 //SMU_GPIOPAD_RCVR_SEL0 736 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 737 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 738 //SMU_GPIOPAD_RCVR_SEL1 739 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 740 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 741 //SMU_GPIOPAD_PU_EN 742 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 743 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 744 //SMU_GPIOPAD_PD_EN 745 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 746 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 747 //SMU_GPIOPAD_PINSTRAPS 748 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 749 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 750 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 751 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 752 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 753 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 754 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 755 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 756 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 757 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 758 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 759 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 760 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 761 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 762 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 763 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 764 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 765 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 766 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 767 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 768 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 769 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 770 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 771 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 772 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 773 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 774 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 775 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 776 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 777 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 778 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 779 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 780 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 781 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 782 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 783 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 784 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 785 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 786 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 787 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 788 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 789 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 790 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 791 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 792 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 793 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 794 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 795 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 796 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 797 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 798 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 799 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 800 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 801 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 802 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 803 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 804 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 805 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 806 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 807 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 808 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 809 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 810 //DFT_PINSTRAPS 811 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 812 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL 813 //SMU_GPIOPAD_INT_STAT_EN 814 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 815 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 816 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 817 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 818 //SMU_GPIOPAD_INT_STAT 819 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 820 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 821 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 822 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 823 //SMU_GPIOPAD_INT_STAT_AK 824 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 825 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 826 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 827 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 828 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 829 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 830 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 831 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 832 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 833 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 834 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 835 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 836 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 837 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 838 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 839 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 840 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 841 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 842 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 843 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 844 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 845 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 846 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 847 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 848 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 849 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 850 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 851 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 852 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 853 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 854 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 855 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 856 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 857 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 858 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 859 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 860 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 861 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 862 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 863 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 864 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 865 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 866 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 867 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 868 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 869 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 870 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 871 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 872 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 873 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 874 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 875 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 876 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 877 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 878 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 879 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 880 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 881 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 882 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 883 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 884 //SMU_GPIOPAD_INT_EN 885 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 886 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 887 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 888 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 889 //SMU_GPIOPAD_INT_TYPE 890 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 891 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 892 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 893 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 894 //SMU_GPIOPAD_INT_POLARITY 895 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 896 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 897 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 898 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 899 //ROM_CC_BIF_PINSTRAP 900 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0 901 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1 902 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4 903 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7 904 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8 905 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9 906 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa 907 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L 908 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL 909 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L 910 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L 911 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L 912 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L 913 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L 914 //IO_SMUIO_PINSTRAP 915 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 916 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 917 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5 918 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8 919 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L 920 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L 921 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L 922 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L 923 //SMUIO_PCC_CONTROL 924 #define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 925 #define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L 926 //SMUIO_PCC_GPIO_SELECT 927 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 928 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 929 //SMUIO_GPIO_INT0_SELECT 930 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 931 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 932 //SMUIO_GPIO_INT1_SELECT 933 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 934 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 935 //SMUIO_GPIO_INT2_SELECT 936 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 937 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 938 //SMUIO_GPIO_INT3_SELECT 939 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 940 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 941 //SMU_GPIOPAD_MP_INT0_STAT 942 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 943 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 944 //SMU_GPIOPAD_MP_INT1_STAT 945 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 946 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 947 //SMU_GPIOPAD_MP_INT2_STAT 948 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 949 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 950 //SMU_GPIOPAD_MP_INT3_STAT 951 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 952 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 953 //SMIO_INDEX 954 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 955 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 956 //S0_VID_SMIO_CNTL 957 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 958 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 959 //S1_VID_SMIO_CNTL 960 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 961 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 962 //OPEN_DRAIN_SELECT 963 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 964 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 965 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 966 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 967 //SMIO_ENABLE 968 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 969 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 970 //SMU_GPIOPAD_S0 971 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 972 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 973 //SMU_GPIOPAD_S1 974 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 975 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 976 //SMU_GPIOPAD_SCL_EN 977 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 978 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 979 //SMU_GPIOPAD_SDA_EN 980 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 981 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 982 //SMU_GPIOPAD_SCHMEN 983 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 984 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 985 986 987 // addressBlock: smuio_smuio_pwr_SmuSmuioDec 988 //IP_DISCOVERY_VERSION 989 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 990 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 991 //SOC_GAP_PWROK 992 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 993 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 994 //GFX_GAP_PWROK 995 #define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0 996 #define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L 997 //PWROK_REFCLK_GAP_CYCLES 998 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 999 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 1000 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 1001 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 1002 //GOLDEN_TSC_INCREMENT_UPPER 1003 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 1004 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 1005 //GOLDEN_TSC_INCREMENT_LOWER 1006 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 1007 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 1008 //GOLDEN_TSC_COUNT_UPPER 1009 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 1010 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 1011 //GOLDEN_TSC_COUNT_LOWER 1012 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 1013 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 1014 //SOC_GOLDEN_TSC_SHADOW_UPPER 1015 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0 1016 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL 1017 //SOC_GOLDEN_TSC_SHADOW_LOWER 1018 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0 1019 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL 1020 //GFX_GOLDEN_TSC_SHADOW_UPPER 1021 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0 1022 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL 1023 //GFX_GOLDEN_TSC_SHADOW_LOWER 1024 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0 1025 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL 1026 //PWR_VIRT_RESET_REQ 1027 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 1028 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 1029 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 1030 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 1031 //SCRATCH_REGISTER0 1032 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 1033 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 1034 //SCRATCH_REGISTER1 1035 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 1036 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 1037 //SCRATCH_REGISTER2 1038 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 1039 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 1040 //SCRATCH_REGISTER3 1041 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 1042 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 1043 //SCRATCH_REGISTER4 1044 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 1045 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 1046 //SCRATCH_REGISTER5 1047 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 1048 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 1049 //SCRATCH_REGISTER6 1050 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 1051 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 1052 //SCRATCH_REGISTER7 1053 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 1054 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 1055 //PWR_DISP_TIMER_CONTROL 1056 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1057 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1058 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1059 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1060 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1061 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1062 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1063 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1064 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1065 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1066 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1067 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1068 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1069 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1070 //PWR_DISP_TIMER2_CONTROL 1071 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1072 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1073 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1074 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1075 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1076 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1077 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1078 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1079 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1080 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1081 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1082 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1083 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1084 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1085 //PWR_DISP_TIMER_GLOBAL_CONTROL 1086 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 1087 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 1088 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 1089 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 1090 //PWR_IH_CONTROL 1091 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 1092 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 1093 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 1094 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 1095 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 1096 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 1097 1098 #endif 1099