1# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) 2# mach: fr550 3# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 4 .include "testutils.inc" 5 6 start 7 8 .global dsr 9dsr: 10 and_spr_immed -4081,tbr ; clear tbr.tt 11 set_gr_spr tbr,gr17 12 inc_gr_immed 0x140,gr17 ; address of exception handler 13 set_bctrlr_0_0 gr17 14 set_spr_immed 128,lcr 15 set_psr_et 1 16 17 set_spr_addr ok0,lr 18 set_gr_immed 0,gr16 19 20 set_gr_immed 0xdeadbeef,gr15 21 set_gr_addr 0xfeff0600,gr17 22bad1: sti gr15,@(gr17,0) ; no interrupt 23 test_gr_immed 0,gr16 24 25 set_gr_immed 0xbeefdead,gr15 26 set_gr_addr 0xfeff7ffc,gr17 27bad2: sti gr15,@(gr17,0) ; no interrupt 28 test_gr_immed 0,gr16 29 30 set_gr_immed 0xbeefbeef,gr15 31 set_gr_addr 0xfe800000,gr17 32bad3: sti gr15,@(gr17,0) ; cause interrupt 33 test_gr_immed 1,gr16 34 35 set_gr_immed 0xdeaddead,gr15 36 set_gr_addr 0xfefefffc,gr17 37bad4: sti gr15,@(gr17,0) ; cause interrupt 38 test_gr_immed 2,gr16 39 40 sti gr0,@(sp,0) ; no interrupt 41 test_gr_immed 2,gr16 42 43 pass 44ok0: 45 ; check interrupts 46 test_spr_immed 0x4000,esfr1 ; esr14 is active 47 test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid 48 test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set 49 test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set 50 51 addi gr16,1,gr16 52 rett 0 53 fail 54