xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/c_interr_timer_reload.S (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c) 
1//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp
2// Spec Reference: interrupt on HW TIMER auto-reload
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Include Files
12//
13
14include(std.inc)
15include(selfcheck.inc)
16
17// Defines
18
19#ifndef TCNTL
20#define TCNTL            0xFFE03000
21#endif
22#ifndef TPERIOD
23#define TPERIOD          0xFFE03004
24#endif
25#ifndef TSCALE
26#define TSCALE           0xFFE03008
27#endif
28#ifndef TCOUNT
29#define TCOUNT           0xFFE0300c
30#endif
31#ifndef EVT
32#define EVT              0xFFE02000
33#endif
34#ifndef EVT15
35#define EVT15            0xFFE0203c
36#endif
37#ifndef EVT_OVERRIDE
38#define EVT_OVERRIDE     0xFFE02100
39#endif
40#ifndef ITABLE
41#define ITABLE           0x000FF000
42#endif
43#ifndef PROGRAM_STACK
44#define PROGRAM_STACK    0x000FF100
45#endif
46#ifndef STACKSIZE
47#define STACKSIZE        0x00000300
48#endif
49
50// Boot code
51
52 BOOT :
53INIT_R_REGS(0);                             // Initialize Dregs
54INIT_P_REGS(0);                             // Initialize Pregs
55
56     // CHECK_INIT(p5,   0x00BFFFFC);
57     // CHECK_INIT(p5,   0xE0000000);
58include(symtable.inc)
59CHECK_INIT_DEF(p5);
60
61
62LD32(sp, 0x000FF200);
63LD32(p0, EVT);              // Setup Event Vectors and Handlers
64
65LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
66        [ P0 ++ ] = R0;
67
68LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
69        [ P0 ++ ] = R0;
70
71LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
72        [ P0 ++ ] = R0;
73
74LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
75        [ P0 ++ ] = R0;
76
77        [ P0 ++ ] = R0;                // IVT4 not used
78
79LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
80        [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
83        [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
86        [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
89        [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
92        [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
95        [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
98        [ P0 ++ ] = R0;
99
100LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
101        [ P0 ++ ] = R0;
102
103LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
104        [ P0 ++ ] = R0;
105
106LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
107        [ P0 ++ ] = R0;
108
109LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
110        [ P0 ++ ] = R0;
111
112LD32(p0, EVT_OVERRIDE);
113        R0 = 0;
114        [ P0 ++ ] = R0;
115        R0 = -1;     // Change this to mask interrupts (*)
116        [ P0 ] = R0;   // IMASK
117
118LD32_LABEL(p1, START);
119
120LD32(p0, EVT15);
121        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
122CSYNC;
123
124RAISE 15;    // after we RTI, INT 15 should be taken
125
126LD32_LABEL(r7, START);
127RETI = r7;
128NOP;        // Workaround for Bug 217
129RTI;
130NOP;
131NOP;
132
133//.code 0x200
134 START :
135        R7 = 0x0;
136        R6 = 0x1;
137        [ -- SP ] = RETI;        // Enable Nested Interrupts
138
139WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
140WR_MMR(TPERIOD, 0x00000020, p0, r0);
141WR_MMR(TCOUNT,  0x00000002, p0, r0);
142WR_MMR(TSCALE,  0x00000005, p0, r0);
143CSYNC;
144        // Read the contents of the Timer
145
146RD_MMR(TPERIOD, p0, r2);
147CHECKREG(r2,    0x00000020);
148
149RD_MMR(TCOUNT, p0, r3);
150CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace
151
152
153WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
154CSYNC;
155
156
157
158NOP; NOP; NOP; NOP; NOP;
159NOP; NOP; NOP; NOP; NOP;
160NOP; NOP; NOP; NOP; NOP;
161
162RD_MMR(TCOUNT, p0, r4);
163CHECKREG(r4,    0x00000000);
164
165RD_MMR(TCNTL, p0, r5);
166CHECKREG(r5,    0x0000000B);
167
168WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
169CSYNC;
170CHECKREG(r7,    0x00000001);
171        R7 = 0;
172NOP;
173WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
174WR_MMR(TPERIOD, 0x00000020, p0, r0);
175WR_MMR(TCOUNT,  0x00000003, p0, r0);
176WR_MMR(TSCALE,  0x00000002, p0, r0);
177WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer auo-reload
178CSYNC;
179NOP; NOP; NOP; NOP; NOP;
180NOP; NOP; NOP; NOP; NOP;
181NOP; NOP; NOP; NOP; NOP;
182NOP; NOP; NOP; NOP; NOP;
183                                                    // With auto reload
184        // Read the contents of the Timer
185
186//      CHECKREG(r7,    0x00000002);
187CC = R7 == 0;
188IF !CC JUMP LABEL1;
189WR_MMR(TPERIOD, 0x00000030, p0, r0);   // SHOULD NOT EXECUTE
190
191LABEL1:
192
193
194RD_MMR(TPERIOD, p0, r2);
195CHECKREG(r2,    0x00000020);
196
197RD_MMR(TCNTL , p0, r3);
198CHECKREG(r3,    0x0000000F);
199
200WR_MMR(TCNTL,   0x00000003, p0, r0);    // Turn ON Timer but not auto-reload
201CSYNC;
202
203NOP; NOP;  NOP; NOP;
204NOP; NOP;  NOP; NOP;
205NOP; NOP;  NOP; NOP;
206NOP; NOP;  NOP; NOP;
207NOP; NOP;  NOP; NOP;
208NOP; NOP;  NOP; NOP;
209NOP; NOP;  NOP; NOP;
210RD_MMR(TCOUNT, p0, r4);
211CHECKREG(r4,    0x00000000);
212
213RD_MMR(TCNTL, p0, r5);
214CHECKREG(r5,    0x0000000B);
215
216WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
217CSYNC;
218NOP; NOP; NOP;
219
220
221
222
223
224dbg_pass;        // Call Endtest Macro
225
226
227
228//*********************************************************************
229//
230// Handlers for Events
231//
232
233EHANDLE:            // Emulation Handler 0
234RTE;
235
236RHANDLE:            // Reset Handler 1
237RTI;
238
239NHANDLE:            // NMI Handler 2
240RTN;
241
242XHANDLE:            // Exception Handler 3
243RTX;
244
245HWHANDLE:           // HW Error Handler 5
246RTI;
247
248THANDLE:            // Timer Handler 6
249        R7 = R7 + R6;
250RTI;
251
252I7HANDLE:           // IVG 7 Handler
253RTI;
254
255I8HANDLE:           // IVG 8 Handler
256RTI;
257
258I9HANDLE:           // IVG 9 Handler
259RTI;
260
261I10HANDLE:          // IVG 10 Handler
262RTI;
263
264I11HANDLE:          // IVG 11 Handler
265RTI;
266
267I12HANDLE:          // IVG 12 Handler
268RTI;
269
270I13HANDLE:          // IVG 13 Handler
271RTI;
272
273I14HANDLE:          // IVG 14 Handler
274RTI;
275
276I15HANDLE:          // IVG 15 Handler
277        R5 = RETI;
278        P0 = R5;
279JUMP ( P0 );
280RTI;
281
282.section MEM_DATA_ADDR_1,"aw"
283
284.space (STACKSIZE);
285STACK:
286NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
287