1//Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp 2// Spec Reference: except_mode_user 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35// 36 37////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table 38 39// 40// Reset/Bootstrap Code 41// (Here we should set the processor operating modes, initialize registers, 42// etc.) 43// 44 45BOOT: 46 47 // in reset mode now 48LD32_LABEL(sp, KSTACK); // setup the stack pointer 49FP = SP; // and frame pointer 50 51LD32(p0, EVT); // Setup Event Vectors and Handlers 52LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 53 [ P0 ++ ] = R0; 54 55LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 56 [ P0 ++ ] = R0; 57 58LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 59 [ P0 ++ ] = R0; 60 61LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 62 [ P0 ++ ] = R0; 63 64 [ P0 ++ ] = R0; // IVT4 not used 65 66LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 67 [ P0 ++ ] = R0; 68 69LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 70 [ P0 ++ ] = R0; 71 72LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 73 [ P0 ++ ] = R0; 74 75LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 76 [ P0 ++ ] = R0; 77 78LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 79 [ P0 ++ ] = R0; 80 81LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 82 [ P0 ++ ] = R0; 83 84LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 85 [ P0 ++ ] = R0; 86 87LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 88 [ P0 ++ ] = R0; 89 90LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 91 [ P0 ++ ] = R0; 92 93LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 94 [ P0 ++ ] = R0; 95 96LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 97 [ P0 ++ ] = R0; 98 99LD32(p0, EVT_OVERRIDE); 100 R0 = 0; 101 [ P0 ++ ] = R0; 102 R0 = -1; // Change this to mask interrupts (*) 103 [ P0 ] = R0; // IMASK 104 105DUMMY: 106 107 R0 = 0 (Z); 108 109LT0 = r0; // set loop counters to something deterministic 110LB0 = r0; 111LC0 = r0; 112LT1 = r0; 113LB1 = r0; 114LC1 = r0; 115 116ASTAT = r0; // reset other internal regs 117 118// The following code sets up the test for running in USER mode 119 120LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 121 // ReturnFromInterrupt (RTI) 122RETI = r0; // We need to load the return address 123 124// Comment the following line for a USER Mode test 125 126// JUMP STARTSUP; // jump to code start for SUPERVISOR mode 127 128RTI; // execute this instr put us in USER mode 129 130STARTSUP: 131LD32_LABEL(p1, BEGIN); 132 133LD32(p0, EVT15); 134 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 135 136RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in 137 // USER MODE & go to different RAISE in USER mode 138 // until the end of the test. 139 140NOP; // Workaround for Bug 217 141RTI; 142 143// 144// The Main Program 145// 146STARTUSER: 147LD32_LABEL(sp, USTACK); // setup the stack pointer 148FP = SP; // set frame pointer 149JUMP BEGIN; 150 151//********************************************************************* 152 153BEGIN: 154 155 // COMMENT the following line for USER MODE tests 156 [ -- SP ] = RETI; // enable interrupts in supervisor mode 157 158 // **** YOUR CODE GOES HERE **** 159 160 161 162 // PUT YOUR TEST HERE! 163 // Can't Raise 0, 3, or 4 164 // Raise 1 requires some intelligence so the test 165 // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) 166RAISE 2; // RTN // exception because we execute this in USER mode 167RAISE 5; // RTI 168RAISE 6; // RTI 169RAISE 7; // RTI 170RAISE 8; // RTI 171RAISE 9; // RTI 172RAISE 10; // RTI 173RAISE 11; // RTI 174RAISE 12; // RTI 175RAISE 13; // RTI 176RAISE 14; // RTI 177 178R0 = I0; 179R1 = I1; 180R2 = I2; 181R3 = I3; 182R4 = M0; 183R5 = M1; 184R6 = M2; 185R7 = M3; 186 187 188CHECKREG(r0, 0x00000018); 189CHECKREG(r2, 0x00000000); 190CHECKREG(r3, 0x00000000); 191CHECKREG(r4, 0x00000000); 192CHECKREG(r5, 0x00000000); 193CHECKREG(r6, 0x00000000); 194CHECKREG(r7, 0x00000000); 195 196 197END: 198dbg_pass; // End the test 199 200//********************************************************************* 201 202// 203// Handlers for Events 204// 205 206EHANDLE: // Emulation Handler 0 207RTE; 208 209RHANDLE: // Reset Handler 1 210RTI; 211 212NHANDLE: // NMI Handler 2 213 R0 = RETN; 214 R0 += 2; 215 I0 += 2; 216 I1 += 2; 217 I2 += 2; 218 I3 += 2; 219RETN = r0; 220RTN; 221 222XHANDLE: // Exception Handler 3 223 R1 = RETX; 224 I0 += 2; 225 R1 += 2; // for return address 226RETX = r1; 227RTX; 228 229HWHANDLE: // HW Error Handler 5 230 R2 = RETI; 231 R2 += 2; 232 I0 += 2; 233 I1 += 2; 234RETI = r2; 235RTI; 236 237THANDLE: // Timer Handler 6 238 R3 = RETI; 239 I0 += 2; 240 I1 += 2; 241 I2 += 2; 242 R3 += 2; 243RETI = r3; 244RTI; 245 246I7HANDLE: // IVG 7 Handler 247 R4 = RETI; 248 I0 += 2; 249 I1 += 2; 250 I3 += 2; 251 R4 += 2; 252RETI = r4; 253RTI; 254 255I8HANDLE: // IVG 8 Handler 256 R5 = RETI; 257 I0 += 2; 258 I1 += 2; 259 I2 += 2; 260 I3 += 2; 261 R5 += 2; 262RETI = r5; 263RTI; 264 265I9HANDLE: // IVG 9 Handler 266 R6 = RETI; 267 I0 += 2; 268 I1 += 2; 269 I2 += 2; 270 I3 += 2; 271 R6 += 2; 272RETI = r6; 273RTI; 274 275I10HANDLE: // IVG 10 Handler 276 R7 = RETI; 277 I0 += 2; 278 I1 += 2; 279 I2 += 2; 280 I3 += 2; 281 R7 += 2; 282RETI = r7; 283RTI; 284 285I11HANDLE: // IVG 11 Handler 286 R0 = RETI; 287 R0 += 2; 288 M0 = I0; 289 M1 = I1; 290 M2 = I2; 291 M3 = I3; 292RETI = r0; 293RTI; 294 295I12HANDLE: // IVG 12 Handler 296 R1 = RETI; 297 I0 += 2; 298 I1 += 2; 299 I2 += 2; 300 I3 += 2; 301 R1 += 2; 302RETI = r1; 303RTI; 304 305I13HANDLE: // IVG 13 Handler 306 R2 = RETI; 307 I0 += 2; 308 I1 += 2; 309 I2 += 2; 310 I3 += 2; 311 R2 += 2; 312RETI = r2; 313RTI; 314 315I14HANDLE: // IVG 14 Handler 316 R3 = RETI; 317 I0 += 2; 318 I1 += 2; 319 I2 += 2; 320 I3 += 2; 321 R3 += 2; 322RETI = r3; 323RTI; 324 325I15HANDLE: // IVG 15 Handler 326 I0 += 2; 327 I1 += 2; 328 I2 += 2; 329 I3 += 2; 330RTI; 331 332// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug 333 334// 335// Data Segment 336// 337 338.data 339DATA: 340 .space (0x10); 341 342// Stack Segments (Both Kernel and User) 343 344 .space (STACKSIZE); 345KSTACK: 346 347 .space (STACKSIZE); 348USTACK: 349// .space (STACKSIZE); // adding this may solve the problem 350