1 /* $NetBSD: sdma1_4_2_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma1_4_2_0_SH_MASK_HEADER 24 #define _sdma1_4_2_0_SH_MASK_HEADER 25 26 27 // addressBlock: sdma1_sdma1dec 28 //SDMA1_UCODE_ADDR 29 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA1_UCODE_DATA 32 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA1_VM_CNTL 35 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA1_VM_CTX_LO 38 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA1_VM_CTX_HI 41 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA1_ACTIVE_FCN_ID 44 #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA1_VM_CTX_CNTL 51 #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA1_VIRT_RESET_REQ 56 #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA1_VF_ENABLE 61 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA1_CONTEXT_REG_TYPE0 64 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA1_CONTEXT_REG_TYPE1 105 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 106 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 121 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA1_CONTEXT_REG_TYPE2 136 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA1_CONTEXT_REG_TYPE3 159 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA1_PUB_REG_TYPE0 162 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 163 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 164 #define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL__SHIFT 0x2 165 #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 166 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 167 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 168 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 169 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 170 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 171 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 172 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 173 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 174 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 175 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 176 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 177 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 178 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 179 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 180 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 181 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 182 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 183 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 184 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 185 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 186 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 187 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 188 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 189 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 190 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 191 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 192 #define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL_MASK 0x00000004L 193 #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 194 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 195 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 196 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 197 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 198 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 199 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 200 #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 201 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 202 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 203 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 204 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 205 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 206 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 207 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 208 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 209 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 210 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 211 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 212 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 213 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 214 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 215 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 216 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 217 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 218 //SDMA1_PUB_REG_TYPE1 219 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 220 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 221 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 222 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 223 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 224 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 225 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 226 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 227 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 228 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 229 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 230 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 231 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 232 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 233 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 234 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 235 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 236 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 237 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 238 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 239 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 240 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 241 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 242 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 243 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 244 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 245 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 246 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 247 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 248 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 249 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 250 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 251 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 252 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 253 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 254 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 255 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 256 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 257 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 258 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 259 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 260 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 261 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 262 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 263 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 264 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 265 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 266 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 267 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 268 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 269 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 270 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 271 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 272 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 273 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 274 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 275 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 276 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 277 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 278 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 279 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 280 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 281 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 282 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 283 //SDMA1_PUB_REG_TYPE2 284 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 285 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 286 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 287 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 288 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 289 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 290 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 291 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 292 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 293 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 294 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 295 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 296 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 297 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 298 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 299 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 300 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 301 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 302 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 303 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 304 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 305 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 306 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 307 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 308 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 309 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 310 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 311 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 312 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 313 #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 314 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 315 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 316 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 317 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 318 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 319 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 320 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 321 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 322 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 323 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 324 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 325 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 326 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 327 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 328 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 329 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 330 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 331 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 332 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 333 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 334 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 335 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 336 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 337 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 338 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 339 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 340 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 341 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 343 #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 //SDMA1_PUB_REG_TYPE3 345 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 //SDMA1_MMHUB_CNTL 352 #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 //SDMA1_CONTEXT_GROUP_BOUNDARY 355 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 //SDMA1_POWER_CNTL 358 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 364 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 365 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 366 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 367 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 368 //SDMA1_CLK_CTRL 369 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 370 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 371 #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 372 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 373 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 374 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 375 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 376 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 378 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 379 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 380 #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 381 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 382 #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 383 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 384 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 385 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 386 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 387 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 388 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 389 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 390 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 391 //SDMA1_CNTL 392 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 393 #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 394 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 395 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 396 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 397 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 398 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 399 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 400 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 402 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 403 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 404 #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 405 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 406 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 407 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 408 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 409 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 410 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 411 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 412 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 413 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 414 //SDMA1_CHICKEN_BITS 415 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 416 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 417 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 418 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 419 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 420 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 421 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 422 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 423 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 424 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 425 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 426 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 427 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 428 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 429 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 430 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 431 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 432 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 433 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 434 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 435 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 436 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 437 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 438 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 439 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 440 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 441 //SDMA1_GB_ADDR_CONFIG 442 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 443 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 444 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 445 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 446 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 447 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 448 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 449 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 450 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 451 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 452 //SDMA1_GB_ADDR_CONFIG_READ 453 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 454 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 455 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 456 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 457 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 458 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 459 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 460 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 461 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 462 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 463 //SDMA1_RB_RPTR_FETCH_HI 464 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 465 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 466 //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 467 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 468 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 469 //SDMA1_RB_RPTR_FETCH 470 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 471 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 472 //SDMA1_IB_OFFSET_FETCH 473 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 474 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 475 //SDMA1_PROGRAM 476 #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 477 #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 478 //SDMA1_STATUS_REG 479 #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 480 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 481 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 482 #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 483 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 484 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 485 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 486 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 487 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 488 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 489 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 490 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 491 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 492 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 493 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 494 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 495 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 496 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 497 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 498 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 499 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 500 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 501 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 502 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 503 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 504 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 505 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 506 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 507 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 508 #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 509 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 510 #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 511 #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 512 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 513 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 514 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 515 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 516 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 517 #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 518 #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 519 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 520 #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 521 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 522 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 523 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 524 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 525 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 526 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 527 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 528 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 529 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 530 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 531 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 532 #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 533 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 534 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 535 #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 536 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 537 //SDMA1_STATUS1_REG 538 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 539 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 540 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 541 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 542 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 543 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 544 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 545 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 546 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 547 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 548 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 549 #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 550 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 551 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 552 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 553 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 554 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 555 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 556 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 557 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 558 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 559 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 560 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 561 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 562 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 563 #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 564 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 565 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 566 //SDMA1_RD_BURST_CNTL 567 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 568 #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 569 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 570 #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 571 //SDMA1_HBM_PAGE_CONFIG 572 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 573 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 574 //SDMA1_UCODE_CHECKSUM 575 #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 576 #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 577 //SDMA1_F32_CNTL 578 #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 579 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 580 #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 581 #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 582 //SDMA1_FREEZE 583 #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 584 #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 585 #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 586 #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 587 #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 588 #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 589 #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 590 #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 591 //SDMA1_PHASE0_QUANTUM 592 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 593 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 594 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 595 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 596 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 597 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 598 //SDMA1_PHASE1_QUANTUM 599 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 600 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 601 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 602 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 603 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 604 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 605 //SDMA1_EDC_CONFIG 606 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 607 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 608 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 609 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 610 //SDMA1_BA_THRESHOLD 611 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 612 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 613 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 614 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 615 //SDMA1_ID 616 #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 617 #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 618 //SDMA1_VERSION 619 #define SDMA1_VERSION__MINVER__SHIFT 0x0 620 #define SDMA1_VERSION__MAJVER__SHIFT 0x8 621 #define SDMA1_VERSION__REV__SHIFT 0x10 622 #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 623 #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 624 #define SDMA1_VERSION__REV_MASK 0x003F0000L 625 //SDMA1_EDC_COUNTER 626 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 627 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 628 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 629 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 630 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 631 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 632 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 633 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 634 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 635 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 636 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 637 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 638 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 639 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 640 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 641 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 642 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 643 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 644 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 645 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 646 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 647 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 648 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 649 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 650 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 651 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 652 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 653 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 654 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 655 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 656 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 657 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 658 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 659 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 660 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 661 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 662 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 663 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 664 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 665 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 666 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 667 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 668 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 669 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 670 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 671 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 672 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 673 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 674 //SDMA1_EDC_COUNTER_CLEAR 675 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 676 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 677 //SDMA1_STATUS2_REG 678 #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 679 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 680 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 681 #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 682 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 683 #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 684 //SDMA1_ATOMIC_CNTL 685 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 686 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 687 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 688 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 689 //SDMA1_ATOMIC_PREOP_LO 690 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 691 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 692 //SDMA1_ATOMIC_PREOP_HI 693 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 694 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 695 //SDMA1_UTCL1_CNTL 696 #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 697 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 698 #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 699 #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 700 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 701 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 702 #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 703 #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 704 #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 705 #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 706 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 707 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 708 //SDMA1_UTCL1_WATERMK 709 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 710 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 711 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 712 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 713 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 714 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 715 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 716 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 717 //SDMA1_UTCL1_RD_STATUS 718 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 719 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 720 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 721 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 722 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 723 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 724 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 725 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 726 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 727 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 728 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 729 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 730 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 731 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 732 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 733 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 734 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 735 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 736 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 737 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 738 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 739 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 740 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 741 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 742 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 743 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 744 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 745 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 746 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 747 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 748 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 749 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 750 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 751 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 752 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 753 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 754 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 755 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 756 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 757 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 758 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 759 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 760 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 761 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 762 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 763 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 764 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 765 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 766 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 767 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 768 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 769 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 770 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 771 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 772 //SDMA1_UTCL1_WR_STATUS 773 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 774 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 775 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 776 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 777 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 778 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 779 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 780 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 781 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 782 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 783 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 784 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 785 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 786 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 787 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 788 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 789 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 790 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 791 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 792 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 793 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 794 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 795 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 796 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 797 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 798 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 799 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 800 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 801 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 802 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 803 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 804 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 805 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 806 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 807 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 808 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 809 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 810 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 811 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 812 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 813 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 814 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 815 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 816 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 817 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 818 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 819 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 820 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 821 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 822 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 823 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 824 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 825 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 826 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 827 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 828 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 829 //SDMA1_UTCL1_INV0 830 #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 831 #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 832 #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 833 #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 834 #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 835 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 836 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 837 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 838 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 839 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 840 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 841 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 842 #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 843 #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 844 #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 845 #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 846 #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 847 #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 848 #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 849 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 850 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 851 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 852 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 853 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 854 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 855 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 856 #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 857 #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 858 //SDMA1_UTCL1_INV1 859 #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 860 #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 861 //SDMA1_UTCL1_INV2 862 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 863 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 864 //SDMA1_UTCL1_RD_XNACK0 865 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 866 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 867 //SDMA1_UTCL1_RD_XNACK1 868 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 869 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 870 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 871 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 872 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 873 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 874 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 875 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 876 //SDMA1_UTCL1_WR_XNACK0 877 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 878 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 879 //SDMA1_UTCL1_WR_XNACK1 880 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 881 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 882 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 883 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 884 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 885 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 886 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 887 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 888 //SDMA1_UTCL1_TIMEOUT 889 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 890 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 891 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 892 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 893 //SDMA1_UTCL1_PAGE 894 #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 895 #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 896 #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 897 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 898 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 899 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 900 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 901 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 902 //SDMA1_POWER_CNTL_IDLE 903 #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 904 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 905 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 906 #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 907 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 908 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 909 //SDMA1_RELAX_ORDERING_LUT 910 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 911 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 912 #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 913 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 914 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 915 #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 916 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 917 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 918 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 919 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 920 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 921 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 922 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 923 #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 924 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 925 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 926 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 927 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 928 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 929 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 930 #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 931 #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 932 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 933 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 934 #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 935 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 936 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 937 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 938 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 939 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 940 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 941 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 942 #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 943 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 944 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 945 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 946 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 947 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 948 //SDMA1_CHICKEN_BITS_2 949 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 950 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 951 //SDMA1_STATUS3_REG 952 #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 953 #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 954 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 955 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 956 #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 957 #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 958 #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 959 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 960 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 961 #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 962 //SDMA1_PHYSICAL_ADDR_LO 963 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 964 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 965 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 966 #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 967 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 968 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 969 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 970 #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 971 //SDMA1_PHYSICAL_ADDR_HI 972 #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 973 #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 974 //SDMA1_PHASE2_QUANTUM 975 #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 976 #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 977 #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 978 #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 979 #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 980 #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 981 //SDMA1_ERROR_LOG 982 #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 983 #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 984 #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 985 #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 986 //SDMA1_PUB_DUMMY_REG0 987 #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 988 #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 989 //SDMA1_PUB_DUMMY_REG1 990 #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 991 #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 992 //SDMA1_PUB_DUMMY_REG2 993 #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 994 #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 995 //SDMA1_PUB_DUMMY_REG3 996 #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 997 #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 998 //SDMA1_F32_COUNTER 999 #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 1000 #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1001 //SDMA1_PERFMON_CNTL 1002 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1003 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1004 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1005 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1006 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1007 #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1008 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1009 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1010 #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1011 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1012 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1013 #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1014 //SDMA1_PERFCOUNTER0_RESULT 1015 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1016 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1017 //SDMA1_PERFCOUNTER1_RESULT 1018 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1019 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1020 //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1021 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1022 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1023 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1024 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1025 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1026 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1027 //SDMA1_CRD_CNTL 1028 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1029 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1030 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1031 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1032 //SDMA1_GPU_IOV_VIOLATION_LOG 1033 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1034 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1035 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1036 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1037 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1038 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1039 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1040 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1041 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1042 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1043 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1044 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1045 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1046 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1047 //SDMA1_ULV_CNTL 1048 #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1050 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1051 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1052 #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1053 #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1054 #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1055 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1056 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1057 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1058 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1059 #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1060 //SDMA1_EA_DBIT_ADDR_DATA 1061 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1062 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1063 //SDMA1_EA_DBIT_ADDR_INDEX 1064 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1065 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1066 //SDMA1_GFX_RB_CNTL 1067 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1068 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1069 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1070 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1071 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1072 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1073 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1074 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1075 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1076 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1077 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1078 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1079 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1080 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1081 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1082 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1083 //SDMA1_GFX_RB_BASE 1084 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1085 #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1086 //SDMA1_GFX_RB_BASE_HI 1087 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1088 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1089 //SDMA1_GFX_RB_RPTR 1090 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1091 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1092 //SDMA1_GFX_RB_RPTR_HI 1093 #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1094 #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1095 //SDMA1_GFX_RB_WPTR 1096 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1097 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1098 //SDMA1_GFX_RB_WPTR_HI 1099 #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1100 #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1101 //SDMA1_GFX_RB_WPTR_POLL_CNTL 1102 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1103 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1104 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1105 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1106 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1107 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1108 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1109 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1110 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1111 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1112 //SDMA1_GFX_RB_RPTR_ADDR_HI 1113 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1114 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1115 //SDMA1_GFX_RB_RPTR_ADDR_LO 1116 #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1117 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1118 #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1119 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1120 //SDMA1_GFX_IB_CNTL 1121 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1122 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1123 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1124 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1125 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1126 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1127 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1128 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1129 //SDMA1_GFX_IB_RPTR 1130 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1131 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1132 //SDMA1_GFX_IB_OFFSET 1133 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1134 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1135 //SDMA1_GFX_IB_BASE_LO 1136 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1137 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1138 //SDMA1_GFX_IB_BASE_HI 1139 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1140 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1141 //SDMA1_GFX_IB_SIZE 1142 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1143 #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1144 //SDMA1_GFX_SKIP_CNTL 1145 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1146 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1147 //SDMA1_GFX_CONTEXT_STATUS 1148 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1149 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1150 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1151 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1152 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1153 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1154 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1155 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1156 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1157 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1158 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1159 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1160 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1161 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1162 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1163 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1164 //SDMA1_GFX_DOORBELL 1165 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1166 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1167 #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1168 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1169 //SDMA1_GFX_CONTEXT_CNTL 1170 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1171 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1172 //SDMA1_GFX_STATUS 1173 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1174 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1175 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1176 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1177 //SDMA1_GFX_DOORBELL_LOG 1178 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1179 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1180 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1181 #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1182 //SDMA1_GFX_WATERMARK 1183 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1184 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1185 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1186 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1187 //SDMA1_GFX_DOORBELL_OFFSET 1188 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1189 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1190 //SDMA1_GFX_CSA_ADDR_LO 1191 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1192 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1193 //SDMA1_GFX_CSA_ADDR_HI 1194 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1195 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1196 //SDMA1_GFX_IB_SUB_REMAIN 1197 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1198 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1199 //SDMA1_GFX_PREEMPT 1200 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1201 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1202 //SDMA1_GFX_DUMMY_REG 1203 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1204 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1205 //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1206 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1207 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1208 //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1209 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1210 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1211 //SDMA1_GFX_RB_AQL_CNTL 1212 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1213 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1214 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1215 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1216 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1217 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1218 //SDMA1_GFX_MINOR_PTR_UPDATE 1219 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1220 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1221 //SDMA1_GFX_MIDCMD_DATA0 1222 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1223 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1224 //SDMA1_GFX_MIDCMD_DATA1 1225 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1226 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1227 //SDMA1_GFX_MIDCMD_DATA2 1228 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1229 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1230 //SDMA1_GFX_MIDCMD_DATA3 1231 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1232 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1233 //SDMA1_GFX_MIDCMD_DATA4 1234 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1235 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1236 //SDMA1_GFX_MIDCMD_DATA5 1237 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1238 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1239 //SDMA1_GFX_MIDCMD_DATA6 1240 #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1241 #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1242 //SDMA1_GFX_MIDCMD_DATA7 1243 #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1244 #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1245 //SDMA1_GFX_MIDCMD_DATA8 1246 #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1247 #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1248 //SDMA1_GFX_MIDCMD_CNTL 1249 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1250 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1251 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1252 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1253 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1254 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1255 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1256 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1257 //SDMA1_PAGE_RB_CNTL 1258 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1259 #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1260 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1261 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1262 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1263 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1264 #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1265 #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1266 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1267 #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1268 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1269 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1270 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1271 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1272 #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1273 #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1274 //SDMA1_PAGE_RB_BASE 1275 #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1276 #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1277 //SDMA1_PAGE_RB_BASE_HI 1278 #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1279 #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1280 //SDMA1_PAGE_RB_RPTR 1281 #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1282 #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1283 //SDMA1_PAGE_RB_RPTR_HI 1284 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1285 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1286 //SDMA1_PAGE_RB_WPTR 1287 #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1288 #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1289 //SDMA1_PAGE_RB_WPTR_HI 1290 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1291 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1292 //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1293 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1294 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1295 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1296 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1297 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1298 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1299 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1300 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1301 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1302 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1303 //SDMA1_PAGE_RB_RPTR_ADDR_HI 1304 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1305 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1306 //SDMA1_PAGE_RB_RPTR_ADDR_LO 1307 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1308 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1309 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1310 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1311 //SDMA1_PAGE_IB_CNTL 1312 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1313 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1314 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1315 #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1316 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1317 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1318 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1319 #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1320 //SDMA1_PAGE_IB_RPTR 1321 #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1322 #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1323 //SDMA1_PAGE_IB_OFFSET 1324 #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1325 #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1326 //SDMA1_PAGE_IB_BASE_LO 1327 #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1328 #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1329 //SDMA1_PAGE_IB_BASE_HI 1330 #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1331 #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1332 //SDMA1_PAGE_IB_SIZE 1333 #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1334 #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1335 //SDMA1_PAGE_SKIP_CNTL 1336 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1337 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1338 //SDMA1_PAGE_CONTEXT_STATUS 1339 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1340 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1341 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1342 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1343 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1344 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1345 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1346 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1347 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1348 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1349 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1350 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1351 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1352 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1353 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1354 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1355 //SDMA1_PAGE_DOORBELL 1356 #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1357 #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1358 #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1359 #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1360 //SDMA1_PAGE_STATUS 1361 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1362 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1363 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1364 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1365 //SDMA1_PAGE_DOORBELL_LOG 1366 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1367 #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1368 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1369 #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1370 //SDMA1_PAGE_WATERMARK 1371 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1372 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1373 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1374 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1375 //SDMA1_PAGE_DOORBELL_OFFSET 1376 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1377 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1378 //SDMA1_PAGE_CSA_ADDR_LO 1379 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1380 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1381 //SDMA1_PAGE_CSA_ADDR_HI 1382 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1383 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1384 //SDMA1_PAGE_IB_SUB_REMAIN 1385 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1386 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1387 //SDMA1_PAGE_PREEMPT 1388 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1389 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1390 //SDMA1_PAGE_DUMMY_REG 1391 #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1392 #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1393 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1394 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1395 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1396 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1397 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1398 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1399 //SDMA1_PAGE_RB_AQL_CNTL 1400 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1401 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1402 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1403 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1404 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1405 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1406 //SDMA1_PAGE_MINOR_PTR_UPDATE 1407 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1408 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1409 //SDMA1_PAGE_MIDCMD_DATA0 1410 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1411 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1412 //SDMA1_PAGE_MIDCMD_DATA1 1413 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1414 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1415 //SDMA1_PAGE_MIDCMD_DATA2 1416 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1417 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1418 //SDMA1_PAGE_MIDCMD_DATA3 1419 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1420 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1421 //SDMA1_PAGE_MIDCMD_DATA4 1422 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1423 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1424 //SDMA1_PAGE_MIDCMD_DATA5 1425 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1426 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1427 //SDMA1_PAGE_MIDCMD_DATA6 1428 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1429 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1430 //SDMA1_PAGE_MIDCMD_DATA7 1431 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1432 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1433 //SDMA1_PAGE_MIDCMD_DATA8 1434 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1435 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1436 //SDMA1_PAGE_MIDCMD_CNTL 1437 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1438 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1439 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1440 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1441 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1442 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1443 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1444 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1445 //SDMA1_RLC0_RB_CNTL 1446 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1447 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1448 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1449 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1450 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1451 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1452 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1453 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1454 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1455 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1456 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1457 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1458 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1459 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1460 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1461 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1462 //SDMA1_RLC0_RB_BASE 1463 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1464 #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1465 //SDMA1_RLC0_RB_BASE_HI 1466 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1467 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1468 //SDMA1_RLC0_RB_RPTR 1469 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1470 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1471 //SDMA1_RLC0_RB_RPTR_HI 1472 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1473 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1474 //SDMA1_RLC0_RB_WPTR 1475 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1476 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1477 //SDMA1_RLC0_RB_WPTR_HI 1478 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1479 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1480 //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1481 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1482 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1483 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1484 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1485 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1486 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1487 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1488 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1489 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1490 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1491 //SDMA1_RLC0_RB_RPTR_ADDR_HI 1492 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1493 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1494 //SDMA1_RLC0_RB_RPTR_ADDR_LO 1495 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1496 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1497 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1498 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1499 //SDMA1_RLC0_IB_CNTL 1500 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1501 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1502 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1503 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1504 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1505 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1506 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1507 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1508 //SDMA1_RLC0_IB_RPTR 1509 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1510 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1511 //SDMA1_RLC0_IB_OFFSET 1512 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1513 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1514 //SDMA1_RLC0_IB_BASE_LO 1515 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1516 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1517 //SDMA1_RLC0_IB_BASE_HI 1518 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1519 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1520 //SDMA1_RLC0_IB_SIZE 1521 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1522 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1523 //SDMA1_RLC0_SKIP_CNTL 1524 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1525 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1526 //SDMA1_RLC0_CONTEXT_STATUS 1527 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1528 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1529 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1530 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1531 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1532 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1533 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1534 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1535 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1536 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1537 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1538 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1539 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1540 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1541 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1542 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1543 //SDMA1_RLC0_DOORBELL 1544 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1545 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1546 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1547 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1548 //SDMA1_RLC0_STATUS 1549 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1550 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1551 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1552 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1553 //SDMA1_RLC0_DOORBELL_LOG 1554 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1555 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1556 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1557 #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1558 //SDMA1_RLC0_WATERMARK 1559 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1560 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1561 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1562 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1563 //SDMA1_RLC0_DOORBELL_OFFSET 1564 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1565 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1566 //SDMA1_RLC0_CSA_ADDR_LO 1567 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1568 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1569 //SDMA1_RLC0_CSA_ADDR_HI 1570 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1571 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1572 //SDMA1_RLC0_IB_SUB_REMAIN 1573 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1574 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1575 //SDMA1_RLC0_PREEMPT 1576 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1577 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1578 //SDMA1_RLC0_DUMMY_REG 1579 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1580 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1581 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1582 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1583 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1584 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1585 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1586 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1587 //SDMA1_RLC0_RB_AQL_CNTL 1588 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1589 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1590 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1591 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1592 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1593 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1594 //SDMA1_RLC0_MINOR_PTR_UPDATE 1595 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1596 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1597 //SDMA1_RLC0_MIDCMD_DATA0 1598 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1599 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1600 //SDMA1_RLC0_MIDCMD_DATA1 1601 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1602 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1603 //SDMA1_RLC0_MIDCMD_DATA2 1604 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1605 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1606 //SDMA1_RLC0_MIDCMD_DATA3 1607 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1608 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1609 //SDMA1_RLC0_MIDCMD_DATA4 1610 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1611 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1612 //SDMA1_RLC0_MIDCMD_DATA5 1613 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1614 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1615 //SDMA1_RLC0_MIDCMD_DATA6 1616 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1617 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1618 //SDMA1_RLC0_MIDCMD_DATA7 1619 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1620 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1621 //SDMA1_RLC0_MIDCMD_DATA8 1622 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1623 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1624 //SDMA1_RLC0_MIDCMD_CNTL 1625 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1626 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1627 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1628 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1629 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1630 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1631 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1632 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1633 //SDMA1_RLC1_RB_CNTL 1634 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1635 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1636 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1637 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1638 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1639 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1640 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1641 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1642 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1643 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1644 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1645 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1646 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1647 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1648 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1649 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1650 //SDMA1_RLC1_RB_BASE 1651 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1652 #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1653 //SDMA1_RLC1_RB_BASE_HI 1654 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1655 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1656 //SDMA1_RLC1_RB_RPTR 1657 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1658 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1659 //SDMA1_RLC1_RB_RPTR_HI 1660 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1661 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1662 //SDMA1_RLC1_RB_WPTR 1663 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1664 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1665 //SDMA1_RLC1_RB_WPTR_HI 1666 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1667 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1668 //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1669 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1670 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1671 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1672 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1673 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1674 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1675 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1676 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1677 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1678 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1679 //SDMA1_RLC1_RB_RPTR_ADDR_HI 1680 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1681 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1682 //SDMA1_RLC1_RB_RPTR_ADDR_LO 1683 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1684 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1685 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1686 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1687 //SDMA1_RLC1_IB_CNTL 1688 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1689 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1690 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1691 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1692 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1693 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1694 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1695 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1696 //SDMA1_RLC1_IB_RPTR 1697 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1698 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1699 //SDMA1_RLC1_IB_OFFSET 1700 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1701 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1702 //SDMA1_RLC1_IB_BASE_LO 1703 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1704 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1705 //SDMA1_RLC1_IB_BASE_HI 1706 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1707 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1708 //SDMA1_RLC1_IB_SIZE 1709 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1710 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1711 //SDMA1_RLC1_SKIP_CNTL 1712 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1713 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1714 //SDMA1_RLC1_CONTEXT_STATUS 1715 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1716 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1717 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1718 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1719 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1720 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1721 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1722 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1723 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1724 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1725 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1726 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1727 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1728 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1729 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1730 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1731 //SDMA1_RLC1_DOORBELL 1732 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1733 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1734 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1735 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1736 //SDMA1_RLC1_STATUS 1737 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1738 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1739 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1740 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1741 //SDMA1_RLC1_DOORBELL_LOG 1742 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1743 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1744 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1745 #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1746 //SDMA1_RLC1_WATERMARK 1747 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1748 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1749 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1750 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1751 //SDMA1_RLC1_DOORBELL_OFFSET 1752 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1753 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1754 //SDMA1_RLC1_CSA_ADDR_LO 1755 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1756 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1757 //SDMA1_RLC1_CSA_ADDR_HI 1758 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1759 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1760 //SDMA1_RLC1_IB_SUB_REMAIN 1761 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1762 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1763 //SDMA1_RLC1_PREEMPT 1764 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1765 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1766 //SDMA1_RLC1_DUMMY_REG 1767 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1768 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1769 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1770 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1771 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1772 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1773 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1774 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1775 //SDMA1_RLC1_RB_AQL_CNTL 1776 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1777 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1778 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1779 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1780 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1781 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1782 //SDMA1_RLC1_MINOR_PTR_UPDATE 1783 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1784 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1785 //SDMA1_RLC1_MIDCMD_DATA0 1786 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1787 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1788 //SDMA1_RLC1_MIDCMD_DATA1 1789 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1790 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1791 //SDMA1_RLC1_MIDCMD_DATA2 1792 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1793 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1794 //SDMA1_RLC1_MIDCMD_DATA3 1795 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1796 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1797 //SDMA1_RLC1_MIDCMD_DATA4 1798 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1799 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1800 //SDMA1_RLC1_MIDCMD_DATA5 1801 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1802 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1803 //SDMA1_RLC1_MIDCMD_DATA6 1804 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1805 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1806 //SDMA1_RLC1_MIDCMD_DATA7 1807 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1808 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1809 //SDMA1_RLC1_MIDCMD_DATA8 1810 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1811 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1812 //SDMA1_RLC1_MIDCMD_CNTL 1813 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1814 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1815 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1816 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1817 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1818 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1819 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1820 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1821 //SDMA1_RLC2_RB_CNTL 1822 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1823 #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1824 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1825 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1826 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1827 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1828 #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1829 #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1830 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1831 #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1832 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1833 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1834 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1835 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1836 #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1837 #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1838 //SDMA1_RLC2_RB_BASE 1839 #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 1840 #define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1841 //SDMA1_RLC2_RB_BASE_HI 1842 #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1843 #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1844 //SDMA1_RLC2_RB_RPTR 1845 #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1846 #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1847 //SDMA1_RLC2_RB_RPTR_HI 1848 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1849 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1850 //SDMA1_RLC2_RB_WPTR 1851 #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1852 #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1853 //SDMA1_RLC2_RB_WPTR_HI 1854 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1855 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1856 //SDMA1_RLC2_RB_WPTR_POLL_CNTL 1857 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1858 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1859 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1860 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1861 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1862 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1863 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1864 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1865 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1866 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1867 //SDMA1_RLC2_RB_RPTR_ADDR_HI 1868 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1869 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1870 //SDMA1_RLC2_RB_RPTR_ADDR_LO 1871 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1872 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1873 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1874 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1875 //SDMA1_RLC2_IB_CNTL 1876 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1877 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1878 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1879 #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1880 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1881 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1882 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1883 #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1884 //SDMA1_RLC2_IB_RPTR 1885 #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1886 #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1887 //SDMA1_RLC2_IB_OFFSET 1888 #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1889 #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1890 //SDMA1_RLC2_IB_BASE_LO 1891 #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1892 #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1893 //SDMA1_RLC2_IB_BASE_HI 1894 #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1895 #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1896 //SDMA1_RLC2_IB_SIZE 1897 #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1898 #define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1899 //SDMA1_RLC2_SKIP_CNTL 1900 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1901 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1902 //SDMA1_RLC2_CONTEXT_STATUS 1903 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1904 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1905 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1906 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1907 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1908 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1909 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1910 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1911 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1912 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1913 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1914 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1915 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1916 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1917 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1918 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1919 //SDMA1_RLC2_DOORBELL 1920 #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1921 #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1922 #define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1923 #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1924 //SDMA1_RLC2_STATUS 1925 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1926 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1927 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1928 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1929 //SDMA1_RLC2_DOORBELL_LOG 1930 #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1931 #define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1932 #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1933 #define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1934 //SDMA1_RLC2_WATERMARK 1935 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1936 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1937 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1938 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1939 //SDMA1_RLC2_DOORBELL_OFFSET 1940 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1941 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1942 //SDMA1_RLC2_CSA_ADDR_LO 1943 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1944 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1945 //SDMA1_RLC2_CSA_ADDR_HI 1946 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1947 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1948 //SDMA1_RLC2_IB_SUB_REMAIN 1949 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1950 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1951 //SDMA1_RLC2_PREEMPT 1952 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1953 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1954 //SDMA1_RLC2_DUMMY_REG 1955 #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1956 #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1957 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 1958 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1959 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1960 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 1961 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1962 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1963 //SDMA1_RLC2_RB_AQL_CNTL 1964 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1965 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1966 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1967 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1968 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1969 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1970 //SDMA1_RLC2_MINOR_PTR_UPDATE 1971 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1972 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1973 //SDMA1_RLC2_MIDCMD_DATA0 1974 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 1975 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1976 //SDMA1_RLC2_MIDCMD_DATA1 1977 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 1978 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1979 //SDMA1_RLC2_MIDCMD_DATA2 1980 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 1981 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1982 //SDMA1_RLC2_MIDCMD_DATA3 1983 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 1984 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1985 //SDMA1_RLC2_MIDCMD_DATA4 1986 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 1987 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1988 //SDMA1_RLC2_MIDCMD_DATA5 1989 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 1990 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1991 //SDMA1_RLC2_MIDCMD_DATA6 1992 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 1993 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1994 //SDMA1_RLC2_MIDCMD_DATA7 1995 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 1996 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1997 //SDMA1_RLC2_MIDCMD_DATA8 1998 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 1999 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2000 //SDMA1_RLC2_MIDCMD_CNTL 2001 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2002 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2003 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2004 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2005 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2006 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2007 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2008 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2009 //SDMA1_RLC3_RB_CNTL 2010 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2011 #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2012 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2013 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2014 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2015 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2016 #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2017 #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2018 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2019 #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2020 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2021 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2022 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2023 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2024 #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2025 #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2026 //SDMA1_RLC3_RB_BASE 2027 #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 2028 #define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2029 //SDMA1_RLC3_RB_BASE_HI 2030 #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2031 #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2032 //SDMA1_RLC3_RB_RPTR 2033 #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2034 #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2035 //SDMA1_RLC3_RB_RPTR_HI 2036 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2037 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2038 //SDMA1_RLC3_RB_WPTR 2039 #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2040 #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2041 //SDMA1_RLC3_RB_WPTR_HI 2042 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2043 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2044 //SDMA1_RLC3_RB_WPTR_POLL_CNTL 2045 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2046 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2047 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2048 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2049 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2050 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2051 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2052 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2053 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2054 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2055 //SDMA1_RLC3_RB_RPTR_ADDR_HI 2056 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2057 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2058 //SDMA1_RLC3_RB_RPTR_ADDR_LO 2059 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2060 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2061 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2062 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2063 //SDMA1_RLC3_IB_CNTL 2064 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2065 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2066 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2067 #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2068 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2069 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2070 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2071 #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2072 //SDMA1_RLC3_IB_RPTR 2073 #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2074 #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2075 //SDMA1_RLC3_IB_OFFSET 2076 #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2077 #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2078 //SDMA1_RLC3_IB_BASE_LO 2079 #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2080 #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2081 //SDMA1_RLC3_IB_BASE_HI 2082 #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2083 #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2084 //SDMA1_RLC3_IB_SIZE 2085 #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2086 #define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2087 //SDMA1_RLC3_SKIP_CNTL 2088 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2089 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2090 //SDMA1_RLC3_CONTEXT_STATUS 2091 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2092 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2093 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2094 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2095 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2096 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2097 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2098 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2099 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2100 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2101 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2102 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2103 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2104 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2105 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2106 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2107 //SDMA1_RLC3_DOORBELL 2108 #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2109 #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2110 #define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2111 #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2112 //SDMA1_RLC3_STATUS 2113 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2114 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2115 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2116 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2117 //SDMA1_RLC3_DOORBELL_LOG 2118 #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2119 #define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2120 #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2121 #define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2122 //SDMA1_RLC3_WATERMARK 2123 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2124 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2125 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2126 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2127 //SDMA1_RLC3_DOORBELL_OFFSET 2128 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2129 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2130 //SDMA1_RLC3_CSA_ADDR_LO 2131 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2132 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2133 //SDMA1_RLC3_CSA_ADDR_HI 2134 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2135 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2136 //SDMA1_RLC3_IB_SUB_REMAIN 2137 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2138 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2139 //SDMA1_RLC3_PREEMPT 2140 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2141 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2142 //SDMA1_RLC3_DUMMY_REG 2143 #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2144 #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2145 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 2146 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2147 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2148 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 2149 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2150 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2151 //SDMA1_RLC3_RB_AQL_CNTL 2152 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2153 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2154 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2155 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2156 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2157 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2158 //SDMA1_RLC3_MINOR_PTR_UPDATE 2159 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2160 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2161 //SDMA1_RLC3_MIDCMD_DATA0 2162 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2163 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2164 //SDMA1_RLC3_MIDCMD_DATA1 2165 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2166 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2167 //SDMA1_RLC3_MIDCMD_DATA2 2168 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2169 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2170 //SDMA1_RLC3_MIDCMD_DATA3 2171 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2172 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2173 //SDMA1_RLC3_MIDCMD_DATA4 2174 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2175 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2176 //SDMA1_RLC3_MIDCMD_DATA5 2177 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2178 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2179 //SDMA1_RLC3_MIDCMD_DATA6 2180 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2181 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2182 //SDMA1_RLC3_MIDCMD_DATA7 2183 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2184 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2185 //SDMA1_RLC3_MIDCMD_DATA8 2186 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2187 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2188 //SDMA1_RLC3_MIDCMD_CNTL 2189 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2190 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2191 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2192 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2193 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2194 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2195 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2196 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2197 //SDMA1_RLC4_RB_CNTL 2198 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2199 #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2200 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2201 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2202 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2203 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2204 #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2205 #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2206 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2207 #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2208 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2209 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2210 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2211 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2212 #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2213 #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2214 //SDMA1_RLC4_RB_BASE 2215 #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 2216 #define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2217 //SDMA1_RLC4_RB_BASE_HI 2218 #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2219 #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2220 //SDMA1_RLC4_RB_RPTR 2221 #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2222 #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2223 //SDMA1_RLC4_RB_RPTR_HI 2224 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2225 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2226 //SDMA1_RLC4_RB_WPTR 2227 #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2228 #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2229 //SDMA1_RLC4_RB_WPTR_HI 2230 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2231 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2232 //SDMA1_RLC4_RB_WPTR_POLL_CNTL 2233 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2234 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2235 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2236 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2237 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2238 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2239 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2240 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2241 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2242 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2243 //SDMA1_RLC4_RB_RPTR_ADDR_HI 2244 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2245 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2246 //SDMA1_RLC4_RB_RPTR_ADDR_LO 2247 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2248 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2249 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2250 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2251 //SDMA1_RLC4_IB_CNTL 2252 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2253 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2254 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2255 #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2256 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2257 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2258 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2259 #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2260 //SDMA1_RLC4_IB_RPTR 2261 #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2262 #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2263 //SDMA1_RLC4_IB_OFFSET 2264 #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2265 #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2266 //SDMA1_RLC4_IB_BASE_LO 2267 #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2268 #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2269 //SDMA1_RLC4_IB_BASE_HI 2270 #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2271 #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2272 //SDMA1_RLC4_IB_SIZE 2273 #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2274 #define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2275 //SDMA1_RLC4_SKIP_CNTL 2276 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2277 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2278 //SDMA1_RLC4_CONTEXT_STATUS 2279 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2280 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2281 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2282 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2283 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2284 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2285 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2286 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2287 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2288 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2289 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2290 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2291 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2292 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2293 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2294 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2295 //SDMA1_RLC4_DOORBELL 2296 #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2297 #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2298 #define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2299 #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2300 //SDMA1_RLC4_STATUS 2301 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2302 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2303 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2304 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2305 //SDMA1_RLC4_DOORBELL_LOG 2306 #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2307 #define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2308 #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2309 #define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2310 //SDMA1_RLC4_WATERMARK 2311 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2312 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2313 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2314 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2315 //SDMA1_RLC4_DOORBELL_OFFSET 2316 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2317 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2318 //SDMA1_RLC4_CSA_ADDR_LO 2319 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2320 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2321 //SDMA1_RLC4_CSA_ADDR_HI 2322 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2323 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2324 //SDMA1_RLC4_IB_SUB_REMAIN 2325 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2326 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2327 //SDMA1_RLC4_PREEMPT 2328 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2329 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2330 //SDMA1_RLC4_DUMMY_REG 2331 #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2332 #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2333 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 2334 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2335 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2336 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 2337 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2338 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2339 //SDMA1_RLC4_RB_AQL_CNTL 2340 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2341 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2342 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2343 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2344 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2345 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2346 //SDMA1_RLC4_MINOR_PTR_UPDATE 2347 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2348 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2349 //SDMA1_RLC4_MIDCMD_DATA0 2350 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2351 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2352 //SDMA1_RLC4_MIDCMD_DATA1 2353 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2354 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2355 //SDMA1_RLC4_MIDCMD_DATA2 2356 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2357 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2358 //SDMA1_RLC4_MIDCMD_DATA3 2359 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2360 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2361 //SDMA1_RLC4_MIDCMD_DATA4 2362 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2363 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2364 //SDMA1_RLC4_MIDCMD_DATA5 2365 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2366 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2367 //SDMA1_RLC4_MIDCMD_DATA6 2368 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2369 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2370 //SDMA1_RLC4_MIDCMD_DATA7 2371 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2372 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2373 //SDMA1_RLC4_MIDCMD_DATA8 2374 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2375 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2376 //SDMA1_RLC4_MIDCMD_CNTL 2377 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2378 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2379 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2380 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2381 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2382 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2383 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2384 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2385 //SDMA1_RLC5_RB_CNTL 2386 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2387 #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2388 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2389 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2390 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2391 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2392 #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2393 #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2394 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2395 #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2396 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2397 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2398 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2399 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2400 #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2401 #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2402 //SDMA1_RLC5_RB_BASE 2403 #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 2404 #define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2405 //SDMA1_RLC5_RB_BASE_HI 2406 #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2407 #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2408 //SDMA1_RLC5_RB_RPTR 2409 #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2410 #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2411 //SDMA1_RLC5_RB_RPTR_HI 2412 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2413 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2414 //SDMA1_RLC5_RB_WPTR 2415 #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2416 #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2417 //SDMA1_RLC5_RB_WPTR_HI 2418 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2419 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2420 //SDMA1_RLC5_RB_WPTR_POLL_CNTL 2421 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2422 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2423 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2424 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2425 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2426 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2427 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2428 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2429 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2430 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2431 //SDMA1_RLC5_RB_RPTR_ADDR_HI 2432 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2433 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2434 //SDMA1_RLC5_RB_RPTR_ADDR_LO 2435 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2436 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2437 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2438 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2439 //SDMA1_RLC5_IB_CNTL 2440 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2441 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2442 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2443 #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2444 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2445 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2446 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2447 #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2448 //SDMA1_RLC5_IB_RPTR 2449 #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2450 #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2451 //SDMA1_RLC5_IB_OFFSET 2452 #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2453 #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2454 //SDMA1_RLC5_IB_BASE_LO 2455 #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2456 #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2457 //SDMA1_RLC5_IB_BASE_HI 2458 #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2459 #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2460 //SDMA1_RLC5_IB_SIZE 2461 #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2462 #define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2463 //SDMA1_RLC5_SKIP_CNTL 2464 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2465 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2466 //SDMA1_RLC5_CONTEXT_STATUS 2467 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2468 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2469 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2470 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2471 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2472 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2473 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2474 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2475 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2476 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2477 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2478 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2479 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2480 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2481 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2482 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2483 //SDMA1_RLC5_DOORBELL 2484 #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2485 #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2486 #define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2487 #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2488 //SDMA1_RLC5_STATUS 2489 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2490 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2491 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2492 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2493 //SDMA1_RLC5_DOORBELL_LOG 2494 #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2495 #define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2496 #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2497 #define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2498 //SDMA1_RLC5_WATERMARK 2499 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2500 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2501 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2502 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2503 //SDMA1_RLC5_DOORBELL_OFFSET 2504 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2505 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2506 //SDMA1_RLC5_CSA_ADDR_LO 2507 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2508 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2509 //SDMA1_RLC5_CSA_ADDR_HI 2510 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2511 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2512 //SDMA1_RLC5_IB_SUB_REMAIN 2513 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2514 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2515 //SDMA1_RLC5_PREEMPT 2516 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2517 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2518 //SDMA1_RLC5_DUMMY_REG 2519 #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2520 #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2521 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 2522 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2523 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2524 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 2525 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2526 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2527 //SDMA1_RLC5_RB_AQL_CNTL 2528 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2529 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2530 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2531 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2532 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2533 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2534 //SDMA1_RLC5_MINOR_PTR_UPDATE 2535 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2536 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2537 //SDMA1_RLC5_MIDCMD_DATA0 2538 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2539 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2540 //SDMA1_RLC5_MIDCMD_DATA1 2541 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2542 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2543 //SDMA1_RLC5_MIDCMD_DATA2 2544 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2545 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2546 //SDMA1_RLC5_MIDCMD_DATA3 2547 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2548 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2549 //SDMA1_RLC5_MIDCMD_DATA4 2550 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2551 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2552 //SDMA1_RLC5_MIDCMD_DATA5 2553 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2554 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2555 //SDMA1_RLC5_MIDCMD_DATA6 2556 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2557 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2558 //SDMA1_RLC5_MIDCMD_DATA7 2559 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2560 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2561 //SDMA1_RLC5_MIDCMD_DATA8 2562 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2563 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2564 //SDMA1_RLC5_MIDCMD_CNTL 2565 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2566 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2567 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2568 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2569 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2570 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2571 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2572 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2573 //SDMA1_RLC6_RB_CNTL 2574 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2575 #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2576 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2577 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2578 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2579 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2580 #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2581 #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2582 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2583 #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2584 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2585 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2586 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2587 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2588 #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2589 #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2590 //SDMA1_RLC6_RB_BASE 2591 #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 2592 #define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2593 //SDMA1_RLC6_RB_BASE_HI 2594 #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2595 #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2596 //SDMA1_RLC6_RB_RPTR 2597 #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2598 #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2599 //SDMA1_RLC6_RB_RPTR_HI 2600 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2601 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2602 //SDMA1_RLC6_RB_WPTR 2603 #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2604 #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2605 //SDMA1_RLC6_RB_WPTR_HI 2606 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2607 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2608 //SDMA1_RLC6_RB_WPTR_POLL_CNTL 2609 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2610 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2611 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2612 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2613 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2614 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2615 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2616 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2617 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2618 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2619 //SDMA1_RLC6_RB_RPTR_ADDR_HI 2620 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2621 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2622 //SDMA1_RLC6_RB_RPTR_ADDR_LO 2623 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2624 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2625 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2626 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2627 //SDMA1_RLC6_IB_CNTL 2628 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2629 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2630 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2631 #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2632 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2633 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2634 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2635 #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2636 //SDMA1_RLC6_IB_RPTR 2637 #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2638 #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2639 //SDMA1_RLC6_IB_OFFSET 2640 #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2641 #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2642 //SDMA1_RLC6_IB_BASE_LO 2643 #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2644 #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2645 //SDMA1_RLC6_IB_BASE_HI 2646 #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2647 #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2648 //SDMA1_RLC6_IB_SIZE 2649 #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2650 #define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2651 //SDMA1_RLC6_SKIP_CNTL 2652 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2653 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2654 //SDMA1_RLC6_CONTEXT_STATUS 2655 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2656 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2657 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2658 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2659 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2660 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2661 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2662 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2663 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2664 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2665 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2666 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2667 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2668 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2669 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2670 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2671 //SDMA1_RLC6_DOORBELL 2672 #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2673 #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2674 #define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2675 #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2676 //SDMA1_RLC6_STATUS 2677 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2678 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2679 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2680 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2681 //SDMA1_RLC6_DOORBELL_LOG 2682 #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2683 #define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2684 #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2685 #define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2686 //SDMA1_RLC6_WATERMARK 2687 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2688 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2689 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2690 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2691 //SDMA1_RLC6_DOORBELL_OFFSET 2692 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2693 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2694 //SDMA1_RLC6_CSA_ADDR_LO 2695 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2696 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2697 //SDMA1_RLC6_CSA_ADDR_HI 2698 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2699 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2700 //SDMA1_RLC6_IB_SUB_REMAIN 2701 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2702 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2703 //SDMA1_RLC6_PREEMPT 2704 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2705 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2706 //SDMA1_RLC6_DUMMY_REG 2707 #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2708 #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2709 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 2710 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2711 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2712 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 2713 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2714 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2715 //SDMA1_RLC6_RB_AQL_CNTL 2716 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2717 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2718 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2719 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2720 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2721 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2722 //SDMA1_RLC6_MINOR_PTR_UPDATE 2723 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2724 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2725 //SDMA1_RLC6_MIDCMD_DATA0 2726 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2727 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2728 //SDMA1_RLC6_MIDCMD_DATA1 2729 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2730 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2731 //SDMA1_RLC6_MIDCMD_DATA2 2732 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2733 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2734 //SDMA1_RLC6_MIDCMD_DATA3 2735 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2736 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2737 //SDMA1_RLC6_MIDCMD_DATA4 2738 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2739 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2740 //SDMA1_RLC6_MIDCMD_DATA5 2741 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2742 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2743 //SDMA1_RLC6_MIDCMD_DATA6 2744 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2745 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2746 //SDMA1_RLC6_MIDCMD_DATA7 2747 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2748 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2749 //SDMA1_RLC6_MIDCMD_DATA8 2750 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2751 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2752 //SDMA1_RLC6_MIDCMD_CNTL 2753 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2754 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2755 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2756 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2757 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2758 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2759 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2760 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2761 //SDMA1_RLC7_RB_CNTL 2762 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2763 #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2764 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2765 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2766 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2767 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2768 #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2769 #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2770 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2771 #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2772 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2773 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2774 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2775 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2776 #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2777 #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2778 //SDMA1_RLC7_RB_BASE 2779 #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 2780 #define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2781 //SDMA1_RLC7_RB_BASE_HI 2782 #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2783 #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2784 //SDMA1_RLC7_RB_RPTR 2785 #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2786 #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2787 //SDMA1_RLC7_RB_RPTR_HI 2788 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2789 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2790 //SDMA1_RLC7_RB_WPTR 2791 #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2792 #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2793 //SDMA1_RLC7_RB_WPTR_HI 2794 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2795 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2796 //SDMA1_RLC7_RB_WPTR_POLL_CNTL 2797 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2798 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2799 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2800 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2801 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2802 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2803 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2804 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2805 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2806 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2807 //SDMA1_RLC7_RB_RPTR_ADDR_HI 2808 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2809 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2810 //SDMA1_RLC7_RB_RPTR_ADDR_LO 2811 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2812 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2813 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2814 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2815 //SDMA1_RLC7_IB_CNTL 2816 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2817 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2818 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2819 #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2820 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2821 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2822 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2823 #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2824 //SDMA1_RLC7_IB_RPTR 2825 #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2826 #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2827 //SDMA1_RLC7_IB_OFFSET 2828 #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2829 #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2830 //SDMA1_RLC7_IB_BASE_LO 2831 #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2832 #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2833 //SDMA1_RLC7_IB_BASE_HI 2834 #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2835 #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2836 //SDMA1_RLC7_IB_SIZE 2837 #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2838 #define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2839 //SDMA1_RLC7_SKIP_CNTL 2840 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2841 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2842 //SDMA1_RLC7_CONTEXT_STATUS 2843 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2844 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2845 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2846 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2847 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2848 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2849 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2850 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2851 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2852 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2853 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2854 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2855 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2856 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2857 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2858 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2859 //SDMA1_RLC7_DOORBELL 2860 #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2861 #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2862 #define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2863 #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2864 //SDMA1_RLC7_STATUS 2865 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2866 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2867 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2868 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2869 //SDMA1_RLC7_DOORBELL_LOG 2870 #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2871 #define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2872 #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2873 #define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2874 //SDMA1_RLC7_WATERMARK 2875 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2876 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2877 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2878 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2879 //SDMA1_RLC7_DOORBELL_OFFSET 2880 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2881 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2882 //SDMA1_RLC7_CSA_ADDR_LO 2883 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2884 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2885 //SDMA1_RLC7_CSA_ADDR_HI 2886 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2887 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2888 //SDMA1_RLC7_IB_SUB_REMAIN 2889 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2890 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2891 //SDMA1_RLC7_PREEMPT 2892 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2893 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2894 //SDMA1_RLC7_DUMMY_REG 2895 #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2896 #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2897 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 2898 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2899 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2900 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 2901 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2902 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2903 //SDMA1_RLC7_RB_AQL_CNTL 2904 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2905 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2906 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2907 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2908 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2909 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2910 //SDMA1_RLC7_MINOR_PTR_UPDATE 2911 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2912 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2913 //SDMA1_RLC7_MIDCMD_DATA0 2914 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2915 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2916 //SDMA1_RLC7_MIDCMD_DATA1 2917 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2918 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2919 //SDMA1_RLC7_MIDCMD_DATA2 2920 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2921 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2922 //SDMA1_RLC7_MIDCMD_DATA3 2923 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2924 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2925 //SDMA1_RLC7_MIDCMD_DATA4 2926 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2927 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2928 //SDMA1_RLC7_MIDCMD_DATA5 2929 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2930 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2931 //SDMA1_RLC7_MIDCMD_DATA6 2932 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2933 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2934 //SDMA1_RLC7_MIDCMD_DATA7 2935 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2936 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2937 //SDMA1_RLC7_MIDCMD_DATA8 2938 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2939 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2940 //SDMA1_RLC7_MIDCMD_CNTL 2941 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2942 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2943 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2944 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2945 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2946 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2947 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2948 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2949 2950 #endif 2951