1 /* $NetBSD: sdma1_4_0_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma1_4_0_SH_MASK_HEADER 24 #define _sdma1_4_0_SH_MASK_HEADER 25 26 27 // addressBlock: sdma1_sdma1dec 28 //SDMA1_UCODE_ADDR 29 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA1_UCODE_DATA 32 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA1_VM_CNTL 35 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA1_VM_CTX_LO 38 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA1_VM_CTX_HI 41 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA1_ACTIVE_FCN_ID 44 #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA1_VM_CTX_CNTL 51 #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA1_VIRT_RESET_REQ 56 #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA1_VF_ENABLE 61 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA1_CONTEXT_REG_TYPE0 64 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA1_CONTEXT_REG_TYPE1 105 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 106 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 121 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA1_CONTEXT_REG_TYPE2 136 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA1_CONTEXT_REG_TYPE3 159 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA1_PUB_REG_TYPE0 162 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 163 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 164 #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 165 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 166 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 167 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 168 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 169 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 170 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 171 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 172 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 173 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 174 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 175 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 176 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 177 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 178 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 179 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 180 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 181 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 182 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 183 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 185 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 186 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 187 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 188 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 189 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 190 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 191 #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 193 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 194 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 195 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 196 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 197 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 198 #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 204 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 205 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 206 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 207 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 208 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 209 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 211 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 212 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 213 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 214 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 215 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 //SDMA1_PUB_REG_TYPE1 217 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 218 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 220 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 221 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 222 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 223 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 224 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 225 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 226 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 227 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 228 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 229 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 230 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 231 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 236 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 237 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 238 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 239 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 240 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 241 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 242 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 243 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 244 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 245 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 246 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 247 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 248 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 249 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 252 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 253 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 254 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 255 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 256 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 257 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 258 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 259 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 260 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 261 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 262 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 263 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 268 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 269 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 270 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 271 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 272 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 274 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 275 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 276 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 277 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 278 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 279 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 280 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 281 //SDMA1_PUB_REG_TYPE2 282 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 283 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 284 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 285 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 286 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 287 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 288 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 289 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 290 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 291 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 292 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 293 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 294 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 295 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 296 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 297 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 298 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 299 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 300 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 301 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 302 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 303 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 304 #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 305 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 306 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 307 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 308 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 309 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 310 #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c 311 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 312 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 313 #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 314 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 315 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 316 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 317 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 318 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 319 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 320 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 321 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 322 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 323 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 324 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 325 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 326 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 327 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 328 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 329 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 330 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 331 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 332 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 333 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 334 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 335 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 336 #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L 337 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 338 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 339 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 340 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 341 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 342 #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L 343 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 344 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 345 #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 346 //SDMA1_PUB_REG_TYPE3 347 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 348 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 349 #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 350 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 351 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 352 #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 353 //SDMA1_MMHUB_CNTL 354 #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 355 #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 356 //SDMA1_CONTEXT_GROUP_BOUNDARY 357 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 358 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 359 //SDMA1_POWER_CNTL 360 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 361 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 362 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 363 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 364 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 365 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 366 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 367 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 368 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 369 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 370 //SDMA1_CLK_CTRL 371 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 372 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 373 #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 374 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 375 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 376 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 378 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 379 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 380 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 381 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 382 #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 383 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 384 #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 385 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 386 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 387 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 388 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 389 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 390 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 391 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 392 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 393 //SDMA1_CNTL 394 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 395 #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 396 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 397 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 398 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 399 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 400 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 401 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 402 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 403 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 404 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 405 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 406 #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 407 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 408 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 409 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 410 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 411 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 412 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 413 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 414 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 415 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 416 //SDMA1_CHICKEN_BITS 417 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 418 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 419 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 420 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 421 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 422 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 423 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 424 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 425 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 426 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 427 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 428 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 429 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 430 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 431 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 432 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 433 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 434 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 435 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 436 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 437 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 438 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 439 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 440 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 441 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 442 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 443 //SDMA1_GB_ADDR_CONFIG 444 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 445 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 446 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 447 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 448 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 449 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 450 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 451 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 452 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 453 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 454 //SDMA1_GB_ADDR_CONFIG_READ 455 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 456 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 457 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 458 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 459 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 460 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 461 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 462 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 463 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 464 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 465 //SDMA1_RB_RPTR_FETCH_HI 466 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 467 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 468 //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 469 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 470 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 471 //SDMA1_RB_RPTR_FETCH 472 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 473 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 474 //SDMA1_IB_OFFSET_FETCH 475 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 476 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 477 //SDMA1_PROGRAM 478 #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 479 #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 480 //SDMA1_STATUS_REG 481 #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 482 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 483 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 484 #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 485 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 486 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 487 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 488 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 489 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 490 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 491 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 492 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 493 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 494 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 495 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 496 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 497 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 498 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 499 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 500 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 501 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 502 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 503 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 504 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 505 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 506 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 507 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 508 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 509 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 510 #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 511 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 512 #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 513 #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 514 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 515 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 516 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 517 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 518 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 519 #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 520 #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 521 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 522 #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 523 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 524 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 525 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 526 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 527 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 528 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 529 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 530 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 531 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 532 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 533 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 534 #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 535 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 536 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 537 #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 538 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 539 //SDMA1_STATUS1_REG 540 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 541 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 542 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 543 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 544 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 545 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 546 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 547 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 548 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 549 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 550 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 551 #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 552 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 553 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 554 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 555 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 556 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 557 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 558 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 559 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 560 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 561 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 562 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 563 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 564 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 565 #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 566 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 567 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 568 //SDMA1_RD_BURST_CNTL 569 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 570 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 571 //SDMA1_HBM_PAGE_CONFIG 572 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 573 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 574 //SDMA1_UCODE_CHECKSUM 575 #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 576 #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 577 //SDMA1_F32_CNTL 578 #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 579 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 580 #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 581 #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 582 //SDMA1_FREEZE 583 #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 584 #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 585 #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 586 #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 587 #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 588 #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 589 #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 590 #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 591 //SDMA1_PHASE0_QUANTUM 592 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 593 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 594 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 595 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 596 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 597 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 598 //SDMA1_PHASE1_QUANTUM 599 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 600 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 601 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 602 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 603 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 604 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 605 //SDMA1_EDC_CONFIG 606 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 607 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 608 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 609 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 610 //SDMA1_BA_THRESHOLD 611 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 612 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 613 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 614 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 615 //SDMA1_ID 616 #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 617 #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 618 //SDMA1_VERSION 619 #define SDMA1_VERSION__MINVER__SHIFT 0x0 620 #define SDMA1_VERSION__MAJVER__SHIFT 0x8 621 #define SDMA1_VERSION__REV__SHIFT 0x10 622 #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 623 #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 624 #define SDMA1_VERSION__REV_MASK 0x003F0000L 625 //SDMA1_EDC_COUNTER 626 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 627 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 628 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 629 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 630 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 631 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 632 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 633 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 634 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 635 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 636 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 637 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 638 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 639 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 640 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 641 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 642 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 643 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 644 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 645 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 646 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 647 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 648 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 649 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 650 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 651 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 652 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 653 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 654 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 655 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 656 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 657 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 658 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 659 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 660 //SDMA1_EDC_COUNTER_CLEAR 661 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 662 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 663 //SDMA1_STATUS2_REG 664 #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 665 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 666 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 667 #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 668 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 669 #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 670 //SDMA1_ATOMIC_CNTL 671 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 672 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 673 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 674 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 675 //SDMA1_ATOMIC_PREOP_LO 676 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 677 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 678 //SDMA1_ATOMIC_PREOP_HI 679 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 680 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 681 //SDMA1_UTCL1_CNTL 682 #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 683 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 684 #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 685 #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 686 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 687 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 688 #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 689 #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 690 #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 691 #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 692 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 693 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 694 //SDMA1_UTCL1_WATERMK 695 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 696 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 697 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 698 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 699 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 700 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 701 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 702 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 703 //SDMA1_UTCL1_RD_STATUS 704 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 705 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 706 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 707 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 708 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 709 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 710 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 711 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 712 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 713 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 714 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 715 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 716 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 717 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 718 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 719 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 720 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 721 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 722 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 723 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 724 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 725 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 726 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 727 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 728 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 729 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 730 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 731 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 732 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 733 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 734 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 735 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 736 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 737 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 738 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 739 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 740 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 741 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 742 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 743 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 744 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 745 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 746 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 747 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 748 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 749 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 750 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 751 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 752 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 753 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 754 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 755 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 756 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 757 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 758 //SDMA1_UTCL1_WR_STATUS 759 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 760 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 761 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 762 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 763 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 764 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 765 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 766 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 767 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 768 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 769 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 770 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 771 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 772 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 773 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 774 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 775 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 776 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 777 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 778 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 779 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 780 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 781 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 782 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 783 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 784 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 785 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 786 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 787 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 788 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 789 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 790 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 791 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 792 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 793 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 794 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 795 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 796 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 797 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 798 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 799 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 800 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 801 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 802 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 803 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 804 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 805 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 806 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 807 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 808 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 809 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 810 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 811 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 812 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 813 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 814 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 815 //SDMA1_UTCL1_INV0 816 #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 817 #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 818 #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 819 #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 820 #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 821 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 822 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 823 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 824 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 825 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 826 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 827 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 828 #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 829 #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 830 #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 831 #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 832 #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 833 #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 834 #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 835 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 836 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 837 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 838 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 839 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 840 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 841 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 842 #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 843 #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 844 //SDMA1_UTCL1_INV1 845 #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 846 #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 847 //SDMA1_UTCL1_INV2 848 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 849 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 850 //SDMA1_UTCL1_RD_XNACK0 851 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 852 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 853 //SDMA1_UTCL1_RD_XNACK1 854 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 855 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 856 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 857 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 858 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 859 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 860 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 861 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 862 //SDMA1_UTCL1_WR_XNACK0 863 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 864 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 865 //SDMA1_UTCL1_WR_XNACK1 866 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 867 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 868 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 869 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 870 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 871 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 872 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 873 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 874 //SDMA1_UTCL1_TIMEOUT 875 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 876 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 877 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 878 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 879 //SDMA1_UTCL1_PAGE 880 #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 881 #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 882 #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 883 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 884 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 885 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 886 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 887 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 888 //SDMA1_POWER_CNTL_IDLE 889 #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 890 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 891 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 892 #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 893 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 894 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 895 //SDMA1_RELAX_ORDERING_LUT 896 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 897 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 898 #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 899 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 900 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 901 #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 902 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 903 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 904 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 905 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 906 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 907 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 908 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 909 #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 910 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 911 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 912 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 913 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 914 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 915 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 916 #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 917 #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 918 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 919 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 920 #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 921 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 922 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 923 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 924 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 925 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 926 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 927 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 928 #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 929 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 930 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 931 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 932 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 933 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 934 //SDMA1_CHICKEN_BITS_2 935 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 936 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 937 //SDMA1_STATUS3_REG 938 #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 939 #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 940 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 941 #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 942 #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 943 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 944 //SDMA1_PHYSICAL_ADDR_LO 945 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 946 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 947 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 948 #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 949 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 950 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 951 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 952 #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 953 //SDMA1_PHYSICAL_ADDR_HI 954 #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 955 #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 956 //SDMA1_PHASE2_QUANTUM 957 #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 958 #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 959 #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 960 #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 961 #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 962 #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 963 //SDMA1_ERROR_LOG 964 #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 965 #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 966 #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 967 #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 968 //SDMA1_PUB_DUMMY_REG0 969 #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 970 #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 971 //SDMA1_PUB_DUMMY_REG1 972 #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 973 #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 974 //SDMA1_PUB_DUMMY_REG2 975 #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 976 #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 977 //SDMA1_PUB_DUMMY_REG3 978 #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 979 #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 980 //SDMA1_F32_COUNTER 981 #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 982 #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 983 //SDMA1_UNBREAKABLE 984 #define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 985 #define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L 986 //SDMA1_PERFMON_CNTL 987 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 988 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 989 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 990 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 991 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 992 #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 993 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 994 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 995 #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 996 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 997 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 998 #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 999 //SDMA1_PERFCOUNTER0_RESULT 1000 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1001 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1002 //SDMA1_PERFCOUNTER1_RESULT 1003 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1004 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1005 //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1006 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1007 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1008 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1009 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1010 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1011 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1012 //SDMA1_CRD_CNTL 1013 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1014 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1015 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1016 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1017 //SDMA1_MMHUB_TRUSTLVL 1018 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1019 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1020 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1021 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1022 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1023 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1024 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1025 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1026 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1027 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1028 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1029 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1030 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1031 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1032 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1033 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1034 //SDMA1_GPU_IOV_VIOLATION_LOG 1035 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1036 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1037 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1038 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1039 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1040 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1041 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1042 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1043 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1044 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1045 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1046 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1047 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1048 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1049 //SDMA1_ULV_CNTL 1050 #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1051 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1052 #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1053 #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1054 #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1055 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1056 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1057 #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1058 //SDMA1_EA_DBIT_ADDR_DATA 1059 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1060 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1061 //SDMA1_EA_DBIT_ADDR_INDEX 1062 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1063 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1064 //SDMA1_GFX_RB_CNTL 1065 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1066 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1067 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1068 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1069 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1070 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1071 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1072 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1073 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1074 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1075 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1076 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1077 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1078 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1079 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1080 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1081 //SDMA1_GFX_RB_BASE 1082 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1083 #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1084 //SDMA1_GFX_RB_BASE_HI 1085 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1086 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1087 //SDMA1_GFX_RB_RPTR 1088 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1089 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1090 //SDMA1_GFX_RB_RPTR_HI 1091 #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1092 #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1093 //SDMA1_GFX_RB_WPTR 1094 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1095 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1096 //SDMA1_GFX_RB_WPTR_HI 1097 #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1098 #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1099 //SDMA1_GFX_RB_WPTR_POLL_CNTL 1100 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1101 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1102 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1103 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1104 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1105 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1106 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1107 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1108 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1109 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1110 //SDMA1_GFX_RB_RPTR_ADDR_HI 1111 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1112 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1113 //SDMA1_GFX_RB_RPTR_ADDR_LO 1114 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1115 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1116 //SDMA1_GFX_IB_CNTL 1117 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1118 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1119 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1120 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1121 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1122 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1123 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1124 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1125 //SDMA1_GFX_IB_RPTR 1126 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1127 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1128 //SDMA1_GFX_IB_OFFSET 1129 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1130 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1131 //SDMA1_GFX_IB_BASE_LO 1132 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1133 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1134 //SDMA1_GFX_IB_BASE_HI 1135 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1136 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1137 //SDMA1_GFX_IB_SIZE 1138 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1139 #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1140 //SDMA1_GFX_SKIP_CNTL 1141 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1142 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1143 //SDMA1_GFX_CONTEXT_STATUS 1144 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1145 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1146 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1147 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1148 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1149 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1150 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1151 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1152 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1153 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1154 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1155 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1156 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1157 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1158 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1159 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1160 //SDMA1_GFX_DOORBELL 1161 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1162 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1163 #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1164 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1165 //SDMA1_GFX_CONTEXT_CNTL 1166 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1167 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1168 //SDMA1_GFX_STATUS 1169 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1170 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1171 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1172 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1173 //SDMA1_GFX_DOORBELL_LOG 1174 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1175 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1176 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1177 #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1178 //SDMA1_GFX_WATERMARK 1179 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1180 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1181 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1182 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1183 //SDMA1_GFX_DOORBELL_OFFSET 1184 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1185 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1186 //SDMA1_GFX_CSA_ADDR_LO 1187 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1188 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1189 //SDMA1_GFX_CSA_ADDR_HI 1190 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1191 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1192 //SDMA1_GFX_IB_SUB_REMAIN 1193 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1194 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1195 //SDMA1_GFX_PREEMPT 1196 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1197 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1198 //SDMA1_GFX_DUMMY_REG 1199 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1200 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1201 //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1202 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1203 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1204 //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1205 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1206 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1207 //SDMA1_GFX_RB_AQL_CNTL 1208 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1209 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1210 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1211 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1212 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1213 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1214 //SDMA1_GFX_MINOR_PTR_UPDATE 1215 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1216 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1217 //SDMA1_GFX_MIDCMD_DATA0 1218 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1219 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1220 //SDMA1_GFX_MIDCMD_DATA1 1221 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1222 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1223 //SDMA1_GFX_MIDCMD_DATA2 1224 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1225 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1226 //SDMA1_GFX_MIDCMD_DATA3 1227 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1228 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1229 //SDMA1_GFX_MIDCMD_DATA4 1230 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1231 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1232 //SDMA1_GFX_MIDCMD_DATA5 1233 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1234 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1235 //SDMA1_GFX_MIDCMD_DATA6 1236 #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1237 #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1238 //SDMA1_GFX_MIDCMD_DATA7 1239 #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1240 #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1241 //SDMA1_GFX_MIDCMD_DATA8 1242 #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1243 #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1244 //SDMA1_GFX_MIDCMD_CNTL 1245 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1246 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1247 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1248 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1249 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1250 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1251 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1252 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1253 //SDMA1_PAGE_RB_CNTL 1254 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1255 #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1256 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1257 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1258 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1259 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1260 #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1261 #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1262 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1263 #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1264 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1265 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1266 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1267 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1268 #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1269 #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1270 //SDMA1_PAGE_RB_BASE 1271 #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1272 #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1273 //SDMA1_PAGE_RB_BASE_HI 1274 #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1275 #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1276 //SDMA1_PAGE_RB_RPTR 1277 #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1278 #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1279 //SDMA1_PAGE_RB_RPTR_HI 1280 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1281 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1282 //SDMA1_PAGE_RB_WPTR 1283 #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1284 #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1285 //SDMA1_PAGE_RB_WPTR_HI 1286 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1287 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1288 //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1289 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1290 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1291 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1292 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1293 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1294 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1295 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1296 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1297 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1298 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1299 //SDMA1_PAGE_RB_RPTR_ADDR_HI 1300 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1301 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1302 //SDMA1_PAGE_RB_RPTR_ADDR_LO 1303 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1304 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1305 //SDMA1_PAGE_IB_CNTL 1306 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1307 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1308 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1309 #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1310 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1311 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1312 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1313 #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1314 //SDMA1_PAGE_IB_RPTR 1315 #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1316 #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1317 //SDMA1_PAGE_IB_OFFSET 1318 #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1319 #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1320 //SDMA1_PAGE_IB_BASE_LO 1321 #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1322 #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1323 //SDMA1_PAGE_IB_BASE_HI 1324 #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1325 #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1326 //SDMA1_PAGE_IB_SIZE 1327 #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1328 #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1329 //SDMA1_PAGE_SKIP_CNTL 1330 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1331 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1332 //SDMA1_PAGE_CONTEXT_STATUS 1333 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1334 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1335 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1336 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1337 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1338 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1339 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1340 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1341 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1342 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1343 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1344 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1345 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1346 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1347 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1348 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1349 //SDMA1_PAGE_DOORBELL 1350 #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1351 #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1352 #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1353 #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1354 //SDMA1_PAGE_STATUS 1355 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1356 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1357 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1358 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1359 //SDMA1_PAGE_DOORBELL_LOG 1360 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1361 #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1362 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1363 #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1364 //SDMA1_PAGE_WATERMARK 1365 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1366 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1367 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1368 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1369 //SDMA1_PAGE_DOORBELL_OFFSET 1370 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1371 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1372 //SDMA1_PAGE_CSA_ADDR_LO 1373 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1374 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1375 //SDMA1_PAGE_CSA_ADDR_HI 1376 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1377 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1378 //SDMA1_PAGE_IB_SUB_REMAIN 1379 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1380 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1381 //SDMA1_PAGE_PREEMPT 1382 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1383 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1384 //SDMA1_PAGE_DUMMY_REG 1385 #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1386 #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1387 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1388 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1389 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1390 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1391 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1392 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1393 //SDMA1_PAGE_RB_AQL_CNTL 1394 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1395 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1396 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1397 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1398 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1399 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1400 //SDMA1_PAGE_MINOR_PTR_UPDATE 1401 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1402 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1403 //SDMA1_PAGE_MIDCMD_DATA0 1404 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1405 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1406 //SDMA1_PAGE_MIDCMD_DATA1 1407 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1408 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1409 //SDMA1_PAGE_MIDCMD_DATA2 1410 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1411 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1412 //SDMA1_PAGE_MIDCMD_DATA3 1413 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1414 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1415 //SDMA1_PAGE_MIDCMD_DATA4 1416 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1417 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1418 //SDMA1_PAGE_MIDCMD_DATA5 1419 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1420 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1421 //SDMA1_PAGE_MIDCMD_DATA6 1422 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1423 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1424 //SDMA1_PAGE_MIDCMD_DATA7 1425 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1426 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1427 //SDMA1_PAGE_MIDCMD_DATA8 1428 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1429 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1430 //SDMA1_PAGE_MIDCMD_CNTL 1431 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1432 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1433 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1434 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1435 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1436 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1437 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1438 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1439 //SDMA1_RLC0_RB_CNTL 1440 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1441 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1442 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1443 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1444 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1445 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1446 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1447 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1448 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1449 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1450 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1451 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1452 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1453 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1454 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1455 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1456 //SDMA1_RLC0_RB_BASE 1457 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1458 #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1459 //SDMA1_RLC0_RB_BASE_HI 1460 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1461 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1462 //SDMA1_RLC0_RB_RPTR 1463 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1464 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1465 //SDMA1_RLC0_RB_RPTR_HI 1466 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1467 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1468 //SDMA1_RLC0_RB_WPTR 1469 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1470 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1471 //SDMA1_RLC0_RB_WPTR_HI 1472 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1473 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1474 //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1475 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1476 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1477 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1478 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1479 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1480 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1481 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1482 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1483 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1484 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1485 //SDMA1_RLC0_RB_RPTR_ADDR_HI 1486 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1487 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1488 //SDMA1_RLC0_RB_RPTR_ADDR_LO 1489 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1490 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1491 //SDMA1_RLC0_IB_CNTL 1492 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1493 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1494 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1495 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1496 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1497 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1498 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1499 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1500 //SDMA1_RLC0_IB_RPTR 1501 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1502 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1503 //SDMA1_RLC0_IB_OFFSET 1504 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1505 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1506 //SDMA1_RLC0_IB_BASE_LO 1507 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1508 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1509 //SDMA1_RLC0_IB_BASE_HI 1510 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1511 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1512 //SDMA1_RLC0_IB_SIZE 1513 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1514 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1515 //SDMA1_RLC0_SKIP_CNTL 1516 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1517 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1518 //SDMA1_RLC0_CONTEXT_STATUS 1519 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1520 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1521 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1522 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1523 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1524 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1525 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1526 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1527 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1528 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1529 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1530 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1531 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1532 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1533 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1534 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1535 //SDMA1_RLC0_DOORBELL 1536 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1537 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1538 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1539 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1540 //SDMA1_RLC0_STATUS 1541 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1542 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1543 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1544 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1545 //SDMA1_RLC0_DOORBELL_LOG 1546 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1547 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1548 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1549 #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1550 //SDMA1_RLC0_WATERMARK 1551 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1552 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1553 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1554 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1555 //SDMA1_RLC0_DOORBELL_OFFSET 1556 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1557 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1558 //SDMA1_RLC0_CSA_ADDR_LO 1559 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1560 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1561 //SDMA1_RLC0_CSA_ADDR_HI 1562 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1563 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1564 //SDMA1_RLC0_IB_SUB_REMAIN 1565 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1566 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1567 //SDMA1_RLC0_PREEMPT 1568 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1569 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1570 //SDMA1_RLC0_DUMMY_REG 1571 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1572 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1573 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1574 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1575 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1576 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1577 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1578 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1579 //SDMA1_RLC0_RB_AQL_CNTL 1580 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1581 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1582 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1583 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1584 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1585 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1586 //SDMA1_RLC0_MINOR_PTR_UPDATE 1587 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1588 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1589 //SDMA1_RLC0_MIDCMD_DATA0 1590 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1591 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1592 //SDMA1_RLC0_MIDCMD_DATA1 1593 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1594 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1595 //SDMA1_RLC0_MIDCMD_DATA2 1596 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1597 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1598 //SDMA1_RLC0_MIDCMD_DATA3 1599 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1600 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1601 //SDMA1_RLC0_MIDCMD_DATA4 1602 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1603 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1604 //SDMA1_RLC0_MIDCMD_DATA5 1605 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1606 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1607 //SDMA1_RLC0_MIDCMD_DATA6 1608 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1609 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1610 //SDMA1_RLC0_MIDCMD_DATA7 1611 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1612 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1613 //SDMA1_RLC0_MIDCMD_DATA8 1614 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1615 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1616 //SDMA1_RLC0_MIDCMD_CNTL 1617 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1618 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1619 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1620 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1621 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1622 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1623 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1624 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1625 //SDMA1_RLC1_RB_CNTL 1626 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1627 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1628 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1629 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1630 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1631 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1632 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1633 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1634 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1635 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1636 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1637 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1638 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1639 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1640 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1641 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1642 //SDMA1_RLC1_RB_BASE 1643 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1644 #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1645 //SDMA1_RLC1_RB_BASE_HI 1646 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1647 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1648 //SDMA1_RLC1_RB_RPTR 1649 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1650 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1651 //SDMA1_RLC1_RB_RPTR_HI 1652 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1653 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1654 //SDMA1_RLC1_RB_WPTR 1655 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1656 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1657 //SDMA1_RLC1_RB_WPTR_HI 1658 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1659 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1660 //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1661 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1662 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1663 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1664 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1665 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1666 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1667 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1668 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1669 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1670 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1671 //SDMA1_RLC1_RB_RPTR_ADDR_HI 1672 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1673 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1674 //SDMA1_RLC1_RB_RPTR_ADDR_LO 1675 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1676 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1677 //SDMA1_RLC1_IB_CNTL 1678 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1679 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1680 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1681 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1682 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1683 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1684 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1685 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1686 //SDMA1_RLC1_IB_RPTR 1687 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1688 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1689 //SDMA1_RLC1_IB_OFFSET 1690 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1691 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1692 //SDMA1_RLC1_IB_BASE_LO 1693 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1694 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1695 //SDMA1_RLC1_IB_BASE_HI 1696 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1697 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1698 //SDMA1_RLC1_IB_SIZE 1699 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1700 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1701 //SDMA1_RLC1_SKIP_CNTL 1702 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1703 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1704 //SDMA1_RLC1_CONTEXT_STATUS 1705 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1706 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1707 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1708 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1709 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1710 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1711 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1712 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1713 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1714 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1715 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1716 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1717 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1718 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1719 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1720 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1721 //SDMA1_RLC1_DOORBELL 1722 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1723 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1724 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1725 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1726 //SDMA1_RLC1_STATUS 1727 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1728 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1729 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1730 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1731 //SDMA1_RLC1_DOORBELL_LOG 1732 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1733 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1734 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1735 #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1736 //SDMA1_RLC1_WATERMARK 1737 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1738 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1739 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1740 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1741 //SDMA1_RLC1_DOORBELL_OFFSET 1742 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1743 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1744 //SDMA1_RLC1_CSA_ADDR_LO 1745 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1746 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1747 //SDMA1_RLC1_CSA_ADDR_HI 1748 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1749 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1750 //SDMA1_RLC1_IB_SUB_REMAIN 1751 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1752 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1753 //SDMA1_RLC1_PREEMPT 1754 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1755 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1756 //SDMA1_RLC1_DUMMY_REG 1757 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1758 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1759 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1760 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1761 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1762 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1763 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1764 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1765 //SDMA1_RLC1_RB_AQL_CNTL 1766 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1767 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1768 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1769 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1770 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1771 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1772 //SDMA1_RLC1_MINOR_PTR_UPDATE 1773 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1774 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1775 //SDMA1_RLC1_MIDCMD_DATA0 1776 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1777 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1778 //SDMA1_RLC1_MIDCMD_DATA1 1779 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1780 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1781 //SDMA1_RLC1_MIDCMD_DATA2 1782 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1783 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1784 //SDMA1_RLC1_MIDCMD_DATA3 1785 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1786 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1787 //SDMA1_RLC1_MIDCMD_DATA4 1788 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1789 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1790 //SDMA1_RLC1_MIDCMD_DATA5 1791 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1792 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1793 //SDMA1_RLC1_MIDCMD_DATA6 1794 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1795 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1796 //SDMA1_RLC1_MIDCMD_DATA7 1797 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1798 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1799 //SDMA1_RLC1_MIDCMD_DATA8 1800 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1801 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1802 //SDMA1_RLC1_MIDCMD_CNTL 1803 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1804 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1805 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1806 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1807 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1808 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1809 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1810 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1811 1812 #endif 1813