1 /* $NetBSD: sdma0_4_2_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma0_4_2_0_SH_MASK_HEADER 24 #define _sdma0_4_2_0_SH_MASK_HEADER 25 26 27 // addressBlock: sdma0_sdma0dec 28 //SDMA0_UCODE_ADDR 29 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA0_UCODE_DATA 32 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA0_VM_CNTL 35 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA0_VM_CTX_LO 38 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA0_VM_CTX_HI 41 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA0_ACTIVE_FCN_ID 44 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA0_VM_CTX_CNTL 51 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA0_VIRT_RESET_REQ 56 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA0_VF_ENABLE 61 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA0_CONTEXT_REG_TYPE0 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA0_CONTEXT_REG_TYPE1 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA0_CONTEXT_REG_TYPE2 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA0_CONTEXT_REG_TYPE3 159 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA0_PUB_REG_TYPE0 162 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 164 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 169 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 171 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 179 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 181 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 189 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 191 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 196 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 198 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 206 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 208 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 214 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 215 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 //SDMA0_PUB_REG_TYPE1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 229 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 230 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 231 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 261 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 279 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 280 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 281 //SDMA0_PUB_REG_TYPE2 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 308 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 339 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 340 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 341 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 342 //SDMA0_PUB_REG_TYPE3 343 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 344 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 345 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 346 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 347 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 348 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 349 //SDMA0_MMHUB_CNTL 350 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 351 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 352 //SDMA0_CONTEXT_GROUP_BOUNDARY 353 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 354 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 355 //SDMA0_POWER_CNTL 356 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 357 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 358 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 359 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 360 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 361 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 362 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 363 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 364 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 365 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 366 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 367 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 368 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 369 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 370 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 371 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 372 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 373 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 374 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 375 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 376 //SDMA0_CLK_CTRL 377 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 378 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 379 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 380 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 381 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 384 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 385 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 386 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 387 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 388 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 389 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 390 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 392 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 393 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 394 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 395 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 396 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 397 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 398 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 399 //SDMA0_CNTL 400 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 401 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 402 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 403 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 404 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 405 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 406 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 407 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 408 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 409 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 410 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 411 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 412 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 413 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 414 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 415 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 416 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 417 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 418 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 419 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 420 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 421 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 422 //SDMA0_CHICKEN_BITS 423 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 424 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 425 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 426 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 427 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 428 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 429 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 430 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 431 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 432 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 433 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 434 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 435 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 436 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 437 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 438 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 439 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 440 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 441 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 442 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 443 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 444 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 445 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 446 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 447 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 448 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 449 //SDMA0_GB_ADDR_CONFIG 450 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 451 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 452 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 453 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 454 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 455 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 456 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 457 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 458 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 459 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 460 //SDMA0_GB_ADDR_CONFIG_READ 461 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 462 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 463 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 464 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 465 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 466 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 467 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 468 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 469 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 470 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 471 //SDMA0_RB_RPTR_FETCH_HI 472 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 473 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 474 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 475 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 476 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 477 //SDMA0_RB_RPTR_FETCH 478 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 479 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 480 //SDMA0_IB_OFFSET_FETCH 481 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 482 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 483 //SDMA0_PROGRAM 484 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 485 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 486 //SDMA0_STATUS_REG 487 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 488 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 489 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 490 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 491 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 492 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 493 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 494 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 495 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 496 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 497 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 498 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 499 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 500 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 501 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 502 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 503 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 504 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 505 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 506 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 507 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 508 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 509 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 510 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 511 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 512 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 513 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 514 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 515 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 516 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 517 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 518 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 519 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 520 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 521 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 522 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 523 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 524 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 525 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 526 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 527 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 528 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 529 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 530 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 531 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 532 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 533 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 534 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 535 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 536 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 537 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 538 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 539 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 540 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 541 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 542 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 543 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 544 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 545 //SDMA0_STATUS1_REG 546 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 547 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 548 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 549 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 550 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 551 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 552 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 553 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 554 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 555 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 556 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 557 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 558 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 559 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 560 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 561 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 562 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 563 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 564 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 565 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 566 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 567 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 568 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 569 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 570 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 571 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 572 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 573 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 574 //SDMA0_RD_BURST_CNTL 575 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 576 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 577 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 578 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 579 //SDMA0_HBM_PAGE_CONFIG 580 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 581 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 582 //SDMA0_UCODE_CHECKSUM 583 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 584 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 585 //SDMA0_F32_CNTL 586 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 587 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 588 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 589 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 590 //SDMA0_FREEZE 591 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 592 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 593 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 594 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 595 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 596 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 597 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 598 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 599 //SDMA0_PHASE0_QUANTUM 600 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 601 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 602 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 603 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 604 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 605 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 606 //SDMA0_PHASE1_QUANTUM 607 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 608 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 609 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 610 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 611 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 612 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 613 //SDMA_POWER_GATING 614 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 615 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 616 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 617 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 618 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 619 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 620 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 621 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 622 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 623 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 624 //SDMA_PGFSM_CONFIG 625 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 626 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 627 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 628 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 629 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 630 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 631 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 632 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 633 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 634 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 635 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 636 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 637 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 638 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 639 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 640 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 641 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 642 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 643 //SDMA_PGFSM_WRITE 644 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 645 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 646 //SDMA_PGFSM_READ 647 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 648 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 649 //SDMA0_EDC_CONFIG 650 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 651 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 652 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 653 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 654 //SDMA0_BA_THRESHOLD 655 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 656 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 657 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 658 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 659 //SDMA0_ID 660 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 661 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 662 //SDMA0_VERSION 663 #define SDMA0_VERSION__MINVER__SHIFT 0x0 664 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 665 #define SDMA0_VERSION__REV__SHIFT 0x10 666 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 667 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 668 #define SDMA0_VERSION__REV_MASK 0x003F0000L 669 //SDMA0_EDC_COUNTER 670 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 671 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 672 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 673 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 674 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 675 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 676 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 677 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 678 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 679 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 680 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 681 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 682 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 683 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 684 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 685 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 686 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 687 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 688 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 689 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 690 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 691 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 692 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 693 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 694 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 695 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 696 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 697 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 698 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 699 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 700 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 701 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 702 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 703 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 704 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 705 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 706 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 707 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 708 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 709 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 710 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 711 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 712 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 713 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 714 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 715 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 716 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 717 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 718 //SDMA0_EDC_COUNTER_CLEAR 719 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 720 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 721 //SDMA0_STATUS2_REG 722 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 723 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 724 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 725 #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 726 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 727 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 728 //SDMA0_ATOMIC_CNTL 729 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 730 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 731 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 732 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 733 //SDMA0_ATOMIC_PREOP_LO 734 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 735 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 736 //SDMA0_ATOMIC_PREOP_HI 737 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 738 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 739 //SDMA0_UTCL1_CNTL 740 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 741 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 742 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 743 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 744 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 745 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 746 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 747 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 748 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 749 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 750 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 751 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 752 //SDMA0_UTCL1_WATERMK 753 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 754 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 755 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 756 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 757 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 758 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 759 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 760 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 761 //SDMA0_UTCL1_RD_STATUS 762 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 763 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 764 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 765 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 766 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 767 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 768 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 769 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 770 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 771 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 772 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 773 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 774 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 775 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 776 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 777 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 778 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 779 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 780 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 781 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 782 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 783 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 784 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 785 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 786 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 787 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 788 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 789 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 790 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 791 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 792 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 793 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 794 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 795 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 796 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 797 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 798 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 799 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 800 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 801 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 802 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 803 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 804 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 805 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 806 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 807 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 808 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 809 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 810 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 811 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 812 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 813 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 814 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 815 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 816 //SDMA0_UTCL1_WR_STATUS 817 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 818 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 819 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 820 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 821 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 822 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 823 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 824 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 825 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 826 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 827 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 828 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 829 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 830 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 831 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 832 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 833 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 834 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 835 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 836 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 837 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 838 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 839 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 840 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 841 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 842 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 843 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 844 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 845 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 846 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 847 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 848 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 849 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 850 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 851 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 852 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 853 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 854 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 855 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 856 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 857 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 858 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 859 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 860 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 861 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 862 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 863 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 864 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 865 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 866 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 867 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 868 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 869 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 870 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 871 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 872 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 873 //SDMA0_UTCL1_INV0 874 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 875 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 876 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 877 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 878 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 879 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 880 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 881 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 882 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 883 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 884 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 885 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 886 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 887 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 888 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 889 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 890 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 891 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 892 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 893 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 894 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 895 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 896 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 897 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 898 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 899 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 900 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 901 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 902 //SDMA0_UTCL1_INV1 903 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 904 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 905 //SDMA0_UTCL1_INV2 906 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 907 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 908 //SDMA0_UTCL1_RD_XNACK0 909 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 910 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 911 //SDMA0_UTCL1_RD_XNACK1 912 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 913 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 914 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 915 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 916 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 917 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 918 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 919 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 920 //SDMA0_UTCL1_WR_XNACK0 921 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 922 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 923 //SDMA0_UTCL1_WR_XNACK1 924 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 925 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 926 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 927 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 928 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 929 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 930 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 931 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 932 //SDMA0_UTCL1_TIMEOUT 933 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 934 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 935 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 936 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 937 //SDMA0_UTCL1_PAGE 938 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 939 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 940 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 941 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 942 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 943 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 944 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 945 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 946 //SDMA0_POWER_CNTL_IDLE 947 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 948 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 949 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 950 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 951 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 952 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 953 //SDMA0_RELAX_ORDERING_LUT 954 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 955 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 956 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 957 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 958 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 959 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 960 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 961 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 962 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 963 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 964 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 965 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 966 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 967 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 968 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 969 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 970 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 971 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 972 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 973 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 974 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 975 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 976 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 977 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 978 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 979 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 980 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 981 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 982 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 983 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 984 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 985 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 986 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 987 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 988 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 989 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 990 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 991 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 992 //SDMA0_CHICKEN_BITS_2 993 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 994 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 995 //SDMA0_STATUS3_REG 996 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 997 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 998 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 999 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 1000 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 1001 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1002 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1003 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1004 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1005 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1006 //SDMA0_PHYSICAL_ADDR_LO 1007 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1008 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1009 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1010 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1011 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1012 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1013 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1014 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1015 //SDMA0_PHYSICAL_ADDR_HI 1016 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1017 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1018 //SDMA0_PHASE2_QUANTUM 1019 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1020 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1021 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1022 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1023 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1024 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1025 //SDMA0_ERROR_LOG 1026 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1027 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1028 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1029 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1030 //SDMA0_PUB_DUMMY_REG0 1031 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1032 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1033 //SDMA0_PUB_DUMMY_REG1 1034 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1035 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1036 //SDMA0_PUB_DUMMY_REG2 1037 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1038 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1039 //SDMA0_PUB_DUMMY_REG3 1040 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1041 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1042 //SDMA0_F32_COUNTER 1043 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1044 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1045 //SDMA0_PERFMON_CNTL 1046 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1047 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1048 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1049 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1050 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1051 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1052 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1053 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1054 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1055 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1056 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1057 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1058 //SDMA0_PERFCOUNTER0_RESULT 1059 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1060 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1061 //SDMA0_PERFCOUNTER1_RESULT 1062 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1063 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1064 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1065 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1066 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1067 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1068 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1069 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1070 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1071 //SDMA0_CRD_CNTL 1072 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1073 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1074 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1075 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1076 //SDMA0_GPU_IOV_VIOLATION_LOG 1077 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1078 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1079 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1080 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1081 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1082 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1083 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1084 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1085 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1089 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1090 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1091 //SDMA0_ULV_CNTL 1092 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1093 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1094 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1095 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1096 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1097 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1098 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1099 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1100 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1101 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1102 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1103 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1104 //SDMA0_EA_DBIT_ADDR_DATA 1105 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1106 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1107 //SDMA0_EA_DBIT_ADDR_INDEX 1108 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1109 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1110 //SDMA0_GFX_RB_CNTL 1111 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1112 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1113 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1114 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1115 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1116 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1117 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1118 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1119 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1120 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1121 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1122 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1123 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1124 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1125 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1126 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1127 //SDMA0_GFX_RB_BASE 1128 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1129 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1130 //SDMA0_GFX_RB_BASE_HI 1131 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1132 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1133 //SDMA0_GFX_RB_RPTR 1134 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1135 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1136 //SDMA0_GFX_RB_RPTR_HI 1137 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1138 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1139 //SDMA0_GFX_RB_WPTR 1140 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1141 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1142 //SDMA0_GFX_RB_WPTR_HI 1143 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1144 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1145 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1146 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1147 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1148 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1149 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1150 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1151 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1152 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1153 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1154 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1155 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1156 //SDMA0_GFX_RB_RPTR_ADDR_HI 1157 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1158 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1159 //SDMA0_GFX_RB_RPTR_ADDR_LO 1160 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1161 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1162 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1163 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1164 //SDMA0_GFX_IB_CNTL 1165 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1166 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1167 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1168 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1169 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1170 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1171 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1172 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1173 //SDMA0_GFX_IB_RPTR 1174 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1175 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1176 //SDMA0_GFX_IB_OFFSET 1177 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1178 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1179 //SDMA0_GFX_IB_BASE_LO 1180 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1181 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1182 //SDMA0_GFX_IB_BASE_HI 1183 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1184 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1185 //SDMA0_GFX_IB_SIZE 1186 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1187 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1188 //SDMA0_GFX_SKIP_CNTL 1189 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1190 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1191 //SDMA0_GFX_CONTEXT_STATUS 1192 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1193 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1194 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1195 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1196 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1197 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1198 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1199 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1200 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1201 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1202 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1203 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1204 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1205 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1206 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1207 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1208 //SDMA0_GFX_DOORBELL 1209 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1210 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1211 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1212 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1213 //SDMA0_GFX_CONTEXT_CNTL 1214 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1215 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1216 //SDMA0_GFX_STATUS 1217 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1218 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1219 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1220 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1221 //SDMA0_GFX_DOORBELL_LOG 1222 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1223 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1224 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1225 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1226 //SDMA0_GFX_WATERMARK 1227 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1228 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1229 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1230 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1231 //SDMA0_GFX_DOORBELL_OFFSET 1232 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1233 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1234 //SDMA0_GFX_CSA_ADDR_LO 1235 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1236 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1237 //SDMA0_GFX_CSA_ADDR_HI 1238 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1239 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1240 //SDMA0_GFX_IB_SUB_REMAIN 1241 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1242 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1243 //SDMA0_GFX_PREEMPT 1244 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1245 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1246 //SDMA0_GFX_DUMMY_REG 1247 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1248 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1249 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1250 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1251 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1252 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1253 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1254 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1255 //SDMA0_GFX_RB_AQL_CNTL 1256 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1257 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1258 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1259 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1260 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1261 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1262 //SDMA0_GFX_MINOR_PTR_UPDATE 1263 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1264 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1265 //SDMA0_GFX_MIDCMD_DATA0 1266 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1267 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1268 //SDMA0_GFX_MIDCMD_DATA1 1269 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1270 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1271 //SDMA0_GFX_MIDCMD_DATA2 1272 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1273 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1274 //SDMA0_GFX_MIDCMD_DATA3 1275 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1276 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1277 //SDMA0_GFX_MIDCMD_DATA4 1278 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1279 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1280 //SDMA0_GFX_MIDCMD_DATA5 1281 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1282 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1283 //SDMA0_GFX_MIDCMD_DATA6 1284 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1285 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1286 //SDMA0_GFX_MIDCMD_DATA7 1287 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1288 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1289 //SDMA0_GFX_MIDCMD_DATA8 1290 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1291 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1292 //SDMA0_GFX_MIDCMD_CNTL 1293 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1294 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1295 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1296 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1297 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1298 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1299 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1300 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1301 //SDMA0_PAGE_RB_CNTL 1302 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1303 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1304 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1305 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1306 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1307 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1308 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1309 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1310 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1311 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1312 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1313 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1314 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1315 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1316 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1317 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1318 //SDMA0_PAGE_RB_BASE 1319 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1320 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1321 //SDMA0_PAGE_RB_BASE_HI 1322 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1323 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1324 //SDMA0_PAGE_RB_RPTR 1325 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1326 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1327 //SDMA0_PAGE_RB_RPTR_HI 1328 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1329 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1330 //SDMA0_PAGE_RB_WPTR 1331 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1332 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1333 //SDMA0_PAGE_RB_WPTR_HI 1334 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1335 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1336 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1337 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1338 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1339 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1340 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1341 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1342 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1343 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1344 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1345 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1346 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1347 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1348 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1349 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1350 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1351 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1352 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1353 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1354 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1355 //SDMA0_PAGE_IB_CNTL 1356 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1357 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1358 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1359 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1360 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1361 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1362 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1363 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1364 //SDMA0_PAGE_IB_RPTR 1365 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1366 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1367 //SDMA0_PAGE_IB_OFFSET 1368 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1369 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1370 //SDMA0_PAGE_IB_BASE_LO 1371 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1372 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1373 //SDMA0_PAGE_IB_BASE_HI 1374 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1375 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1376 //SDMA0_PAGE_IB_SIZE 1377 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1378 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1379 //SDMA0_PAGE_SKIP_CNTL 1380 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1381 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1382 //SDMA0_PAGE_CONTEXT_STATUS 1383 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1384 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1385 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1386 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1387 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1388 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1389 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1390 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1391 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1392 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1393 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1394 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1395 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1396 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1397 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1398 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1399 //SDMA0_PAGE_DOORBELL 1400 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1401 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1402 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1403 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1404 //SDMA0_PAGE_STATUS 1405 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1406 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1407 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1408 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1409 //SDMA0_PAGE_DOORBELL_LOG 1410 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1411 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1412 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1413 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1414 //SDMA0_PAGE_WATERMARK 1415 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1416 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1417 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1418 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1419 //SDMA0_PAGE_DOORBELL_OFFSET 1420 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1421 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1422 //SDMA0_PAGE_CSA_ADDR_LO 1423 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1424 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1425 //SDMA0_PAGE_CSA_ADDR_HI 1426 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1427 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1428 //SDMA0_PAGE_IB_SUB_REMAIN 1429 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1430 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1431 //SDMA0_PAGE_PREEMPT 1432 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1433 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1434 //SDMA0_PAGE_DUMMY_REG 1435 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1436 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1437 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1438 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1439 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1440 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1441 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1442 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1443 //SDMA0_PAGE_RB_AQL_CNTL 1444 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1445 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1446 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1447 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1448 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1449 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1450 //SDMA0_PAGE_MINOR_PTR_UPDATE 1451 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1452 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1453 //SDMA0_PAGE_MIDCMD_DATA0 1454 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1455 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1456 //SDMA0_PAGE_MIDCMD_DATA1 1457 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1458 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1459 //SDMA0_PAGE_MIDCMD_DATA2 1460 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1461 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1462 //SDMA0_PAGE_MIDCMD_DATA3 1463 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1464 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1465 //SDMA0_PAGE_MIDCMD_DATA4 1466 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1467 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1468 //SDMA0_PAGE_MIDCMD_DATA5 1469 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1470 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1471 //SDMA0_PAGE_MIDCMD_DATA6 1472 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1473 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1474 //SDMA0_PAGE_MIDCMD_DATA7 1475 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1476 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1477 //SDMA0_PAGE_MIDCMD_DATA8 1478 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1479 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1480 //SDMA0_PAGE_MIDCMD_CNTL 1481 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1482 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1483 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1484 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1485 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1486 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1487 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1488 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1489 //SDMA0_RLC0_RB_CNTL 1490 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1491 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1492 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1493 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1494 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1495 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1496 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1497 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1498 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1499 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1500 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1501 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1502 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1503 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1504 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1505 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1506 //SDMA0_RLC0_RB_BASE 1507 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1508 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1509 //SDMA0_RLC0_RB_BASE_HI 1510 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1511 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1512 //SDMA0_RLC0_RB_RPTR 1513 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1514 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1515 //SDMA0_RLC0_RB_RPTR_HI 1516 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1517 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1518 //SDMA0_RLC0_RB_WPTR 1519 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1520 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1521 //SDMA0_RLC0_RB_WPTR_HI 1522 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1523 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1524 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1525 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1526 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1527 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1528 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1529 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1530 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1531 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1532 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1533 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1534 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1535 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1536 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1537 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1538 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1539 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1540 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1541 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1542 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1543 //SDMA0_RLC0_IB_CNTL 1544 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1545 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1546 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1547 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1548 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1549 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1550 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1551 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1552 //SDMA0_RLC0_IB_RPTR 1553 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1554 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1555 //SDMA0_RLC0_IB_OFFSET 1556 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1557 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1558 //SDMA0_RLC0_IB_BASE_LO 1559 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1560 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1561 //SDMA0_RLC0_IB_BASE_HI 1562 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1563 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1564 //SDMA0_RLC0_IB_SIZE 1565 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1566 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1567 //SDMA0_RLC0_SKIP_CNTL 1568 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1569 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1570 //SDMA0_RLC0_CONTEXT_STATUS 1571 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1572 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1573 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1574 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1575 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1576 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1577 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1578 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1579 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1580 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1581 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1582 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1583 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1584 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1585 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1586 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1587 //SDMA0_RLC0_DOORBELL 1588 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1589 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1590 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1591 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1592 //SDMA0_RLC0_STATUS 1593 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1594 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1595 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1596 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1597 //SDMA0_RLC0_DOORBELL_LOG 1598 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1599 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1600 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1601 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1602 //SDMA0_RLC0_WATERMARK 1603 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1604 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1605 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1606 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1607 //SDMA0_RLC0_DOORBELL_OFFSET 1608 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1609 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1610 //SDMA0_RLC0_CSA_ADDR_LO 1611 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1612 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1613 //SDMA0_RLC0_CSA_ADDR_HI 1614 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1615 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1616 //SDMA0_RLC0_IB_SUB_REMAIN 1617 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1618 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1619 //SDMA0_RLC0_PREEMPT 1620 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1621 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1622 //SDMA0_RLC0_DUMMY_REG 1623 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1624 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1625 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1626 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1627 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1628 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1629 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1630 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1631 //SDMA0_RLC0_RB_AQL_CNTL 1632 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1633 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1634 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1635 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1636 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1637 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1638 //SDMA0_RLC0_MINOR_PTR_UPDATE 1639 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1640 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1641 //SDMA0_RLC0_MIDCMD_DATA0 1642 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1643 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1644 //SDMA0_RLC0_MIDCMD_DATA1 1645 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1646 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1647 //SDMA0_RLC0_MIDCMD_DATA2 1648 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1649 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1650 //SDMA0_RLC0_MIDCMD_DATA3 1651 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1652 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1653 //SDMA0_RLC0_MIDCMD_DATA4 1654 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1655 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1656 //SDMA0_RLC0_MIDCMD_DATA5 1657 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1658 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1659 //SDMA0_RLC0_MIDCMD_DATA6 1660 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1661 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1662 //SDMA0_RLC0_MIDCMD_DATA7 1663 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1664 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1665 //SDMA0_RLC0_MIDCMD_DATA8 1666 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1667 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1668 //SDMA0_RLC0_MIDCMD_CNTL 1669 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1670 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1671 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1672 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1673 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1674 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1675 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1676 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1677 //SDMA0_RLC1_RB_CNTL 1678 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1679 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1680 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1681 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1682 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1683 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1684 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1685 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1686 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1687 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1688 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1689 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1690 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1691 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1692 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1693 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1694 //SDMA0_RLC1_RB_BASE 1695 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1696 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1697 //SDMA0_RLC1_RB_BASE_HI 1698 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1699 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1700 //SDMA0_RLC1_RB_RPTR 1701 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1702 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1703 //SDMA0_RLC1_RB_RPTR_HI 1704 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1705 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1706 //SDMA0_RLC1_RB_WPTR 1707 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1708 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1709 //SDMA0_RLC1_RB_WPTR_HI 1710 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1711 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1712 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1713 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1714 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1715 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1716 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1717 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1718 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1719 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1720 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1721 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1722 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1723 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1724 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1725 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1726 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1727 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1728 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1729 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1730 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1731 //SDMA0_RLC1_IB_CNTL 1732 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1733 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1734 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1735 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1736 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1737 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1738 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1739 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1740 //SDMA0_RLC1_IB_RPTR 1741 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1742 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1743 //SDMA0_RLC1_IB_OFFSET 1744 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1745 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1746 //SDMA0_RLC1_IB_BASE_LO 1747 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1748 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1749 //SDMA0_RLC1_IB_BASE_HI 1750 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1751 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1752 //SDMA0_RLC1_IB_SIZE 1753 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1754 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1755 //SDMA0_RLC1_SKIP_CNTL 1756 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1757 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1758 //SDMA0_RLC1_CONTEXT_STATUS 1759 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1760 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1761 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1762 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1763 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1764 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1765 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1766 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1767 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1768 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1769 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1770 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1771 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1772 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1773 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1774 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1775 //SDMA0_RLC1_DOORBELL 1776 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1777 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1778 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1779 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1780 //SDMA0_RLC1_STATUS 1781 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1782 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1783 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1784 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1785 //SDMA0_RLC1_DOORBELL_LOG 1786 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1787 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1788 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1789 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1790 //SDMA0_RLC1_WATERMARK 1791 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1792 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1793 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1794 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1795 //SDMA0_RLC1_DOORBELL_OFFSET 1796 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1797 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1798 //SDMA0_RLC1_CSA_ADDR_LO 1799 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1800 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1801 //SDMA0_RLC1_CSA_ADDR_HI 1802 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1803 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1804 //SDMA0_RLC1_IB_SUB_REMAIN 1805 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1806 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1807 //SDMA0_RLC1_PREEMPT 1808 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1809 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1810 //SDMA0_RLC1_DUMMY_REG 1811 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1812 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1813 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1814 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1815 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1816 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1817 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1818 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1819 //SDMA0_RLC1_RB_AQL_CNTL 1820 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1821 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1822 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1823 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1824 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1825 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1826 //SDMA0_RLC1_MINOR_PTR_UPDATE 1827 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1828 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1829 //SDMA0_RLC1_MIDCMD_DATA0 1830 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1831 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1832 //SDMA0_RLC1_MIDCMD_DATA1 1833 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1834 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1835 //SDMA0_RLC1_MIDCMD_DATA2 1836 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1837 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1838 //SDMA0_RLC1_MIDCMD_DATA3 1839 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1840 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1841 //SDMA0_RLC1_MIDCMD_DATA4 1842 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1843 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1844 //SDMA0_RLC1_MIDCMD_DATA5 1845 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1846 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1847 //SDMA0_RLC1_MIDCMD_DATA6 1848 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1849 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1850 //SDMA0_RLC1_MIDCMD_DATA7 1851 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1852 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1853 //SDMA0_RLC1_MIDCMD_DATA8 1854 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1855 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1856 //SDMA0_RLC1_MIDCMD_CNTL 1857 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1858 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1859 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1860 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1861 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1862 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1863 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1864 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1865 //SDMA0_RLC2_RB_CNTL 1866 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1867 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1868 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1869 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1870 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1871 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1872 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1873 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1874 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1875 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1876 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1877 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1878 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1879 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1880 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1881 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1882 //SDMA0_RLC2_RB_BASE 1883 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1884 #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1885 //SDMA0_RLC2_RB_BASE_HI 1886 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1887 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1888 //SDMA0_RLC2_RB_RPTR 1889 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1890 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1891 //SDMA0_RLC2_RB_RPTR_HI 1892 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1893 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1894 //SDMA0_RLC2_RB_WPTR 1895 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1896 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1897 //SDMA0_RLC2_RB_WPTR_HI 1898 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1899 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1900 //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1901 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1902 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1903 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1904 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1905 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1906 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1907 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1908 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1909 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1910 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1911 //SDMA0_RLC2_RB_RPTR_ADDR_HI 1912 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1913 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1914 //SDMA0_RLC2_RB_RPTR_ADDR_LO 1915 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1916 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1917 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1918 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1919 //SDMA0_RLC2_IB_CNTL 1920 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1921 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1922 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1923 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1924 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1925 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1926 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1927 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1928 //SDMA0_RLC2_IB_RPTR 1929 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1930 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1931 //SDMA0_RLC2_IB_OFFSET 1932 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1933 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1934 //SDMA0_RLC2_IB_BASE_LO 1935 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1936 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1937 //SDMA0_RLC2_IB_BASE_HI 1938 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1939 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1940 //SDMA0_RLC2_IB_SIZE 1941 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1942 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1943 //SDMA0_RLC2_SKIP_CNTL 1944 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1945 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1946 //SDMA0_RLC2_CONTEXT_STATUS 1947 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1948 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1949 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1950 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1951 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1952 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1953 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1954 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1955 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1956 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1957 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1958 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1959 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1960 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1961 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1962 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1963 //SDMA0_RLC2_DOORBELL 1964 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1965 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1966 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1967 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1968 //SDMA0_RLC2_STATUS 1969 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1970 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1971 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1972 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1973 //SDMA0_RLC2_DOORBELL_LOG 1974 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1975 #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1976 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1977 #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1978 //SDMA0_RLC2_WATERMARK 1979 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1980 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1981 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1982 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1983 //SDMA0_RLC2_DOORBELL_OFFSET 1984 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1985 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1986 //SDMA0_RLC2_CSA_ADDR_LO 1987 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1988 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1989 //SDMA0_RLC2_CSA_ADDR_HI 1990 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1991 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1992 //SDMA0_RLC2_IB_SUB_REMAIN 1993 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1994 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1995 //SDMA0_RLC2_PREEMPT 1996 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1997 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1998 //SDMA0_RLC2_DUMMY_REG 1999 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 2000 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2001 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2002 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2003 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2004 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2005 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2006 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2007 //SDMA0_RLC2_RB_AQL_CNTL 2008 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2009 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2010 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2011 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2012 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2013 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2014 //SDMA0_RLC2_MINOR_PTR_UPDATE 2015 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2016 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2017 //SDMA0_RLC2_MIDCMD_DATA0 2018 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2019 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2020 //SDMA0_RLC2_MIDCMD_DATA1 2021 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2022 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2023 //SDMA0_RLC2_MIDCMD_DATA2 2024 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2025 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2026 //SDMA0_RLC2_MIDCMD_DATA3 2027 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2028 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2029 //SDMA0_RLC2_MIDCMD_DATA4 2030 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2031 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2032 //SDMA0_RLC2_MIDCMD_DATA5 2033 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2034 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2035 //SDMA0_RLC2_MIDCMD_DATA6 2036 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2037 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2038 //SDMA0_RLC2_MIDCMD_DATA7 2039 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2040 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2041 //SDMA0_RLC2_MIDCMD_DATA8 2042 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2043 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2044 //SDMA0_RLC2_MIDCMD_CNTL 2045 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2046 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2047 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2048 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2049 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2050 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2051 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2052 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2053 //SDMA0_RLC3_RB_CNTL 2054 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2055 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2056 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2057 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2058 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2059 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2060 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2061 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2062 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2063 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2064 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2065 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2066 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2067 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2068 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2069 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2070 //SDMA0_RLC3_RB_BASE 2071 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2072 #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2073 //SDMA0_RLC3_RB_BASE_HI 2074 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2075 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2076 //SDMA0_RLC3_RB_RPTR 2077 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2078 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2079 //SDMA0_RLC3_RB_RPTR_HI 2080 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2081 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2082 //SDMA0_RLC3_RB_WPTR 2083 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2084 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2085 //SDMA0_RLC3_RB_WPTR_HI 2086 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2087 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2088 //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2089 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2090 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2091 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2092 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2093 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2094 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2095 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2096 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2097 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2098 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2099 //SDMA0_RLC3_RB_RPTR_ADDR_HI 2100 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2101 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2102 //SDMA0_RLC3_RB_RPTR_ADDR_LO 2103 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2104 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2105 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2106 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2107 //SDMA0_RLC3_IB_CNTL 2108 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2109 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2110 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2111 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2112 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2113 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2114 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2115 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2116 //SDMA0_RLC3_IB_RPTR 2117 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2118 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2119 //SDMA0_RLC3_IB_OFFSET 2120 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2121 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2122 //SDMA0_RLC3_IB_BASE_LO 2123 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2124 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2125 //SDMA0_RLC3_IB_BASE_HI 2126 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2127 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2128 //SDMA0_RLC3_IB_SIZE 2129 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2130 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2131 //SDMA0_RLC3_SKIP_CNTL 2132 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2133 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2134 //SDMA0_RLC3_CONTEXT_STATUS 2135 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2136 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2137 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2138 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2139 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2140 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2141 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2142 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2143 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2144 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2145 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2146 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2147 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2148 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2149 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2150 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2151 //SDMA0_RLC3_DOORBELL 2152 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2153 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2154 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2155 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2156 //SDMA0_RLC3_STATUS 2157 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2158 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2159 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2160 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2161 //SDMA0_RLC3_DOORBELL_LOG 2162 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2163 #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2164 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2165 #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2166 //SDMA0_RLC3_WATERMARK 2167 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2168 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2169 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2170 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2171 //SDMA0_RLC3_DOORBELL_OFFSET 2172 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2173 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2174 //SDMA0_RLC3_CSA_ADDR_LO 2175 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2176 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2177 //SDMA0_RLC3_CSA_ADDR_HI 2178 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2179 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2180 //SDMA0_RLC3_IB_SUB_REMAIN 2181 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2182 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2183 //SDMA0_RLC3_PREEMPT 2184 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2185 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2186 //SDMA0_RLC3_DUMMY_REG 2187 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2188 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2189 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2190 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2191 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2192 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2193 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2194 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2195 //SDMA0_RLC3_RB_AQL_CNTL 2196 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2197 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2198 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2199 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2200 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2201 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2202 //SDMA0_RLC3_MINOR_PTR_UPDATE 2203 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2204 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2205 //SDMA0_RLC3_MIDCMD_DATA0 2206 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2207 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2208 //SDMA0_RLC3_MIDCMD_DATA1 2209 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2210 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2211 //SDMA0_RLC3_MIDCMD_DATA2 2212 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2213 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2214 //SDMA0_RLC3_MIDCMD_DATA3 2215 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2216 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2217 //SDMA0_RLC3_MIDCMD_DATA4 2218 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2219 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2220 //SDMA0_RLC3_MIDCMD_DATA5 2221 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2222 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2223 //SDMA0_RLC3_MIDCMD_DATA6 2224 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2225 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2226 //SDMA0_RLC3_MIDCMD_DATA7 2227 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2228 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2229 //SDMA0_RLC3_MIDCMD_DATA8 2230 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2231 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2232 //SDMA0_RLC3_MIDCMD_CNTL 2233 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2234 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2235 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2236 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2237 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2238 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2239 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2240 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2241 //SDMA0_RLC4_RB_CNTL 2242 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2243 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2244 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2245 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2246 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2247 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2248 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2249 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2250 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2251 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2252 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2253 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2254 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2255 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2256 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2257 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2258 //SDMA0_RLC4_RB_BASE 2259 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2260 #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2261 //SDMA0_RLC4_RB_BASE_HI 2262 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2263 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2264 //SDMA0_RLC4_RB_RPTR 2265 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2266 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2267 //SDMA0_RLC4_RB_RPTR_HI 2268 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2269 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2270 //SDMA0_RLC4_RB_WPTR 2271 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2272 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2273 //SDMA0_RLC4_RB_WPTR_HI 2274 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2275 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2276 //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2277 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2278 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2279 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2280 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2281 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2282 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2283 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2284 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2285 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2286 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2287 //SDMA0_RLC4_RB_RPTR_ADDR_HI 2288 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2289 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2290 //SDMA0_RLC4_RB_RPTR_ADDR_LO 2291 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2292 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2293 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2294 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2295 //SDMA0_RLC4_IB_CNTL 2296 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2297 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2298 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2299 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2300 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2301 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2302 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2303 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2304 //SDMA0_RLC4_IB_RPTR 2305 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2306 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2307 //SDMA0_RLC4_IB_OFFSET 2308 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2309 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2310 //SDMA0_RLC4_IB_BASE_LO 2311 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2312 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2313 //SDMA0_RLC4_IB_BASE_HI 2314 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2315 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2316 //SDMA0_RLC4_IB_SIZE 2317 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2318 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2319 //SDMA0_RLC4_SKIP_CNTL 2320 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2321 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2322 //SDMA0_RLC4_CONTEXT_STATUS 2323 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2324 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2325 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2326 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2327 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2328 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2329 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2330 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2331 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2332 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2333 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2334 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2335 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2336 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2337 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2338 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2339 //SDMA0_RLC4_DOORBELL 2340 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2341 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2342 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2343 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2344 //SDMA0_RLC4_STATUS 2345 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2346 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2347 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2348 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2349 //SDMA0_RLC4_DOORBELL_LOG 2350 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2351 #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2352 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2353 #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2354 //SDMA0_RLC4_WATERMARK 2355 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2356 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2357 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2358 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2359 //SDMA0_RLC4_DOORBELL_OFFSET 2360 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2361 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2362 //SDMA0_RLC4_CSA_ADDR_LO 2363 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2364 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2365 //SDMA0_RLC4_CSA_ADDR_HI 2366 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2367 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2368 //SDMA0_RLC4_IB_SUB_REMAIN 2369 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2370 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2371 //SDMA0_RLC4_PREEMPT 2372 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2373 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2374 //SDMA0_RLC4_DUMMY_REG 2375 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2376 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2377 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2378 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2379 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2380 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2381 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2382 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2383 //SDMA0_RLC4_RB_AQL_CNTL 2384 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2385 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2386 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2387 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2388 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2389 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2390 //SDMA0_RLC4_MINOR_PTR_UPDATE 2391 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2392 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2393 //SDMA0_RLC4_MIDCMD_DATA0 2394 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2395 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2396 //SDMA0_RLC4_MIDCMD_DATA1 2397 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2398 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2399 //SDMA0_RLC4_MIDCMD_DATA2 2400 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2401 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2402 //SDMA0_RLC4_MIDCMD_DATA3 2403 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2404 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2405 //SDMA0_RLC4_MIDCMD_DATA4 2406 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2407 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2408 //SDMA0_RLC4_MIDCMD_DATA5 2409 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2410 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2411 //SDMA0_RLC4_MIDCMD_DATA6 2412 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2413 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2414 //SDMA0_RLC4_MIDCMD_DATA7 2415 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2416 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2417 //SDMA0_RLC4_MIDCMD_DATA8 2418 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2419 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2420 //SDMA0_RLC4_MIDCMD_CNTL 2421 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2422 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2423 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2424 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2425 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2426 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2427 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2428 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2429 //SDMA0_RLC5_RB_CNTL 2430 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2431 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2432 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2433 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2434 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2435 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2436 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2437 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2438 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2439 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2440 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2441 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2442 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2443 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2444 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2445 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2446 //SDMA0_RLC5_RB_BASE 2447 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2448 #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2449 //SDMA0_RLC5_RB_BASE_HI 2450 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2451 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2452 //SDMA0_RLC5_RB_RPTR 2453 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2454 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2455 //SDMA0_RLC5_RB_RPTR_HI 2456 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2457 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2458 //SDMA0_RLC5_RB_WPTR 2459 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2460 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2461 //SDMA0_RLC5_RB_WPTR_HI 2462 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2463 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2464 //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2465 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2466 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2467 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2468 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2469 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2470 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2471 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2472 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2473 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2474 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2475 //SDMA0_RLC5_RB_RPTR_ADDR_HI 2476 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2477 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2478 //SDMA0_RLC5_RB_RPTR_ADDR_LO 2479 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2480 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2481 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2482 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2483 //SDMA0_RLC5_IB_CNTL 2484 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2485 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2486 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2487 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2488 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2489 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2490 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2491 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2492 //SDMA0_RLC5_IB_RPTR 2493 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2494 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2495 //SDMA0_RLC5_IB_OFFSET 2496 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2497 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2498 //SDMA0_RLC5_IB_BASE_LO 2499 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2500 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2501 //SDMA0_RLC5_IB_BASE_HI 2502 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2503 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2504 //SDMA0_RLC5_IB_SIZE 2505 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2506 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2507 //SDMA0_RLC5_SKIP_CNTL 2508 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2509 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2510 //SDMA0_RLC5_CONTEXT_STATUS 2511 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2512 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2513 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2514 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2515 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2516 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2517 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2518 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2519 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2520 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2521 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2522 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2523 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2524 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2525 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2526 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2527 //SDMA0_RLC5_DOORBELL 2528 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2529 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2530 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2531 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2532 //SDMA0_RLC5_STATUS 2533 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2534 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2535 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2536 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2537 //SDMA0_RLC5_DOORBELL_LOG 2538 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2539 #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2540 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2541 #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2542 //SDMA0_RLC5_WATERMARK 2543 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2544 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2545 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2546 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2547 //SDMA0_RLC5_DOORBELL_OFFSET 2548 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2549 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2550 //SDMA0_RLC5_CSA_ADDR_LO 2551 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2552 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2553 //SDMA0_RLC5_CSA_ADDR_HI 2554 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2555 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2556 //SDMA0_RLC5_IB_SUB_REMAIN 2557 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2558 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2559 //SDMA0_RLC5_PREEMPT 2560 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2561 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2562 //SDMA0_RLC5_DUMMY_REG 2563 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2564 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2565 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2566 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2567 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2568 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2569 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2570 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2571 //SDMA0_RLC5_RB_AQL_CNTL 2572 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2573 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2574 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2575 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2576 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2577 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2578 //SDMA0_RLC5_MINOR_PTR_UPDATE 2579 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2580 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2581 //SDMA0_RLC5_MIDCMD_DATA0 2582 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2583 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2584 //SDMA0_RLC5_MIDCMD_DATA1 2585 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2586 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2587 //SDMA0_RLC5_MIDCMD_DATA2 2588 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2589 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2590 //SDMA0_RLC5_MIDCMD_DATA3 2591 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2592 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2593 //SDMA0_RLC5_MIDCMD_DATA4 2594 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2595 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2596 //SDMA0_RLC5_MIDCMD_DATA5 2597 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2598 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2599 //SDMA0_RLC5_MIDCMD_DATA6 2600 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2601 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2602 //SDMA0_RLC5_MIDCMD_DATA7 2603 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2604 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2605 //SDMA0_RLC5_MIDCMD_DATA8 2606 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2607 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2608 //SDMA0_RLC5_MIDCMD_CNTL 2609 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2610 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2611 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2612 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2613 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2614 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2615 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2616 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2617 //SDMA0_RLC6_RB_CNTL 2618 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2619 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2620 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2621 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2622 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2623 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2624 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2625 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2626 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2627 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2628 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2629 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2630 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2631 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2632 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2633 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2634 //SDMA0_RLC6_RB_BASE 2635 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2636 #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2637 //SDMA0_RLC6_RB_BASE_HI 2638 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2639 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2640 //SDMA0_RLC6_RB_RPTR 2641 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2642 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2643 //SDMA0_RLC6_RB_RPTR_HI 2644 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2645 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2646 //SDMA0_RLC6_RB_WPTR 2647 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2648 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2649 //SDMA0_RLC6_RB_WPTR_HI 2650 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2651 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2652 //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2653 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2654 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2655 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2656 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2657 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2658 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2659 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2660 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2661 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2662 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2663 //SDMA0_RLC6_RB_RPTR_ADDR_HI 2664 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2665 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2666 //SDMA0_RLC6_RB_RPTR_ADDR_LO 2667 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2668 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2669 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2670 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2671 //SDMA0_RLC6_IB_CNTL 2672 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2673 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2674 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2675 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2676 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2677 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2678 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2679 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2680 //SDMA0_RLC6_IB_RPTR 2681 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2682 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2683 //SDMA0_RLC6_IB_OFFSET 2684 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2685 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2686 //SDMA0_RLC6_IB_BASE_LO 2687 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2688 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2689 //SDMA0_RLC6_IB_BASE_HI 2690 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2691 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2692 //SDMA0_RLC6_IB_SIZE 2693 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2694 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2695 //SDMA0_RLC6_SKIP_CNTL 2696 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2697 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2698 //SDMA0_RLC6_CONTEXT_STATUS 2699 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2700 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2701 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2702 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2703 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2704 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2705 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2706 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2707 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2708 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2709 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2710 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2711 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2712 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2713 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2714 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2715 //SDMA0_RLC6_DOORBELL 2716 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2717 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2718 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2719 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2720 //SDMA0_RLC6_STATUS 2721 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2722 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2723 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2724 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2725 //SDMA0_RLC6_DOORBELL_LOG 2726 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2727 #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2728 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2729 #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2730 //SDMA0_RLC6_WATERMARK 2731 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2732 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2733 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2734 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2735 //SDMA0_RLC6_DOORBELL_OFFSET 2736 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2737 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2738 //SDMA0_RLC6_CSA_ADDR_LO 2739 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2740 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2741 //SDMA0_RLC6_CSA_ADDR_HI 2742 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2743 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2744 //SDMA0_RLC6_IB_SUB_REMAIN 2745 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2746 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2747 //SDMA0_RLC6_PREEMPT 2748 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2749 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2750 //SDMA0_RLC6_DUMMY_REG 2751 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2752 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2753 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2754 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2755 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2756 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2757 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2758 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2759 //SDMA0_RLC6_RB_AQL_CNTL 2760 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2761 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2762 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2763 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2764 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2765 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2766 //SDMA0_RLC6_MINOR_PTR_UPDATE 2767 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2768 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2769 //SDMA0_RLC6_MIDCMD_DATA0 2770 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2771 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2772 //SDMA0_RLC6_MIDCMD_DATA1 2773 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2774 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2775 //SDMA0_RLC6_MIDCMD_DATA2 2776 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2777 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2778 //SDMA0_RLC6_MIDCMD_DATA3 2779 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2780 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2781 //SDMA0_RLC6_MIDCMD_DATA4 2782 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2783 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2784 //SDMA0_RLC6_MIDCMD_DATA5 2785 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2786 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2787 //SDMA0_RLC6_MIDCMD_DATA6 2788 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2789 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2790 //SDMA0_RLC6_MIDCMD_DATA7 2791 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2792 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2793 //SDMA0_RLC6_MIDCMD_DATA8 2794 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2795 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2796 //SDMA0_RLC6_MIDCMD_CNTL 2797 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2798 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2799 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2800 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2801 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2802 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2803 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2804 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2805 //SDMA0_RLC7_RB_CNTL 2806 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2807 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2808 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2809 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2810 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2811 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2812 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2813 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2814 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2815 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2816 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2817 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2818 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2819 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2820 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2821 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2822 //SDMA0_RLC7_RB_BASE 2823 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2824 #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2825 //SDMA0_RLC7_RB_BASE_HI 2826 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2827 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2828 //SDMA0_RLC7_RB_RPTR 2829 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2830 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2831 //SDMA0_RLC7_RB_RPTR_HI 2832 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2833 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2834 //SDMA0_RLC7_RB_WPTR 2835 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2836 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2837 //SDMA0_RLC7_RB_WPTR_HI 2838 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2839 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2840 //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2841 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2842 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2843 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2844 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2845 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2846 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2847 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2848 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2849 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2850 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2851 //SDMA0_RLC7_RB_RPTR_ADDR_HI 2852 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2853 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2854 //SDMA0_RLC7_RB_RPTR_ADDR_LO 2855 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2856 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2857 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2858 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2859 //SDMA0_RLC7_IB_CNTL 2860 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2861 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2862 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2863 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2864 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2865 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2866 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2867 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2868 //SDMA0_RLC7_IB_RPTR 2869 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2870 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2871 //SDMA0_RLC7_IB_OFFSET 2872 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2873 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2874 //SDMA0_RLC7_IB_BASE_LO 2875 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2876 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2877 //SDMA0_RLC7_IB_BASE_HI 2878 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2879 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2880 //SDMA0_RLC7_IB_SIZE 2881 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2882 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2883 //SDMA0_RLC7_SKIP_CNTL 2884 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2885 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2886 //SDMA0_RLC7_CONTEXT_STATUS 2887 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2888 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2889 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2890 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2891 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2892 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2893 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2894 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2895 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2896 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2897 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2898 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2899 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2900 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2901 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2902 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2903 //SDMA0_RLC7_DOORBELL 2904 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2905 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2906 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2907 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2908 //SDMA0_RLC7_STATUS 2909 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2910 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2911 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2912 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2913 //SDMA0_RLC7_DOORBELL_LOG 2914 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2915 #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2916 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2917 #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2918 //SDMA0_RLC7_WATERMARK 2919 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2920 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2921 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2922 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2923 //SDMA0_RLC7_DOORBELL_OFFSET 2924 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2925 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2926 //SDMA0_RLC7_CSA_ADDR_LO 2927 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2928 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2929 //SDMA0_RLC7_CSA_ADDR_HI 2930 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2931 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2932 //SDMA0_RLC7_IB_SUB_REMAIN 2933 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2934 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2935 //SDMA0_RLC7_PREEMPT 2936 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2937 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2938 //SDMA0_RLC7_DUMMY_REG 2939 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2940 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2941 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2942 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2943 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2944 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2945 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2946 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2947 //SDMA0_RLC7_RB_AQL_CNTL 2948 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2949 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2950 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2951 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2952 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2953 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2954 //SDMA0_RLC7_MINOR_PTR_UPDATE 2955 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2956 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2957 //SDMA0_RLC7_MIDCMD_DATA0 2958 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2959 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2960 //SDMA0_RLC7_MIDCMD_DATA1 2961 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2962 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2963 //SDMA0_RLC7_MIDCMD_DATA2 2964 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2965 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2966 //SDMA0_RLC7_MIDCMD_DATA3 2967 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2968 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2969 //SDMA0_RLC7_MIDCMD_DATA4 2970 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2971 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2972 //SDMA0_RLC7_MIDCMD_DATA5 2973 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2974 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2975 //SDMA0_RLC7_MIDCMD_DATA6 2976 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2977 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2978 //SDMA0_RLC7_MIDCMD_DATA7 2979 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2980 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2981 //SDMA0_RLC7_MIDCMD_DATA8 2982 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2983 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2984 //SDMA0_RLC7_MIDCMD_CNTL 2985 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2986 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2987 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2988 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2989 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2990 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2991 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2992 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2993 2994 #endif 2995