1 /* $NetBSD: sdma0_4_0_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma0_4_0_SH_MASK_HEADER 24 #define _sdma0_4_0_SH_MASK_HEADER 25 26 27 // addressBlock: sdma0_sdma0dec 28 //SDMA0_UCODE_ADDR 29 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA0_UCODE_DATA 32 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA0_VM_CNTL 35 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA0_VM_CTX_LO 38 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA0_VM_CTX_HI 41 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA0_ACTIVE_FCN_ID 44 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA0_VM_CTX_CNTL 51 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA0_VIRT_RESET_REQ 56 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA0_VF_ENABLE 61 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA0_CONTEXT_REG_TYPE0 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA0_CONTEXT_REG_TYPE1 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA0_CONTEXT_REG_TYPE2 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA0_CONTEXT_REG_TYPE3 159 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA0_PUB_REG_TYPE0 162 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 164 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 169 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 171 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 179 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 181 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 189 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 191 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 196 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 198 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 206 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 208 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 214 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 215 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 //SDMA0_PUB_REG_TYPE1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 229 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 230 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 231 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 261 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 279 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 280 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 281 //SDMA0_PUB_REG_TYPE2 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 308 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 309 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 310 #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 311 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 313 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 339 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 340 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 341 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 342 #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 343 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 344 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 345 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 346 //SDMA0_PUB_REG_TYPE3 347 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 348 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 349 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 350 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 351 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 352 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 353 //SDMA0_MMHUB_CNTL 354 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 355 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 356 //SDMA0_CONTEXT_GROUP_BOUNDARY 357 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 358 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 359 //SDMA0_POWER_CNTL 360 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 361 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 362 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 363 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 364 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 365 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 366 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 367 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 368 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 369 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 370 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 371 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 372 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 373 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 374 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 375 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 376 //SDMA0_CLK_CTRL 377 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 378 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 379 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 380 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 381 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 384 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 385 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 386 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 387 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 388 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 389 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 390 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 392 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 393 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 394 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 395 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 396 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 397 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 398 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 399 //SDMA0_CNTL 400 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 401 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 402 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 403 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 404 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 405 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 406 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 407 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 408 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 409 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 410 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 411 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 412 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 413 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 414 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 415 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 416 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 417 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 418 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 419 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 420 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 421 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 422 //SDMA0_CHICKEN_BITS 423 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 424 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 425 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 426 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 427 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 428 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 429 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 430 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 431 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 432 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 433 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 434 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 435 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 436 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 437 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 438 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 439 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 440 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 441 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 442 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 443 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 444 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 445 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 446 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 447 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 448 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 449 //SDMA0_GB_ADDR_CONFIG 450 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 451 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 452 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 453 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 454 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 455 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 456 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 457 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 458 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 459 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 460 //SDMA0_GB_ADDR_CONFIG_READ 461 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 462 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 463 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 464 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 465 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 466 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 467 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 468 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 469 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 470 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 471 //SDMA0_RB_RPTR_FETCH_HI 472 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 473 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 474 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 475 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 476 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 477 //SDMA0_RB_RPTR_FETCH 478 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 479 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 480 //SDMA0_IB_OFFSET_FETCH 481 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 482 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 483 //SDMA0_PROGRAM 484 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 485 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 486 //SDMA0_STATUS_REG 487 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 488 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 489 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 490 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 491 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 492 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 493 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 494 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 495 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 496 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 497 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 498 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 499 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 500 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 501 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 502 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 503 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 504 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 505 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 506 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 507 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 508 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 509 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 510 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 511 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 512 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 513 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 514 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 515 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 516 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 517 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 518 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 519 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 520 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 521 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 522 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 523 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 524 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 525 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 526 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 527 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 528 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 529 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 530 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 531 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 532 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 533 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 534 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 535 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 536 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 537 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 538 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 539 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 540 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 541 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 542 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 543 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 544 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 545 //SDMA0_STATUS1_REG 546 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 547 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 548 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 549 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 550 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 551 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 552 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 553 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 554 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 555 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 556 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 557 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 558 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 559 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 560 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 561 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 562 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 563 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 564 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 565 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 566 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 567 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 568 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 569 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 570 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 571 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 572 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 573 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 574 //SDMA0_RD_BURST_CNTL 575 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 576 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 577 //SDMA0_HBM_PAGE_CONFIG 578 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 579 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 580 //SDMA0_UCODE_CHECKSUM 581 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 582 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 583 //SDMA0_F32_CNTL 584 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 585 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 586 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 587 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 588 //SDMA0_FREEZE 589 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 590 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 591 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 592 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 593 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 594 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 595 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 596 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 597 //SDMA0_PHASE0_QUANTUM 598 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 599 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 600 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 601 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 602 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 603 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 604 //SDMA0_PHASE1_QUANTUM 605 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 606 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 607 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 608 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 609 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 610 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 611 //SDMA_POWER_GATING 612 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 613 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 614 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 615 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 616 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 617 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 618 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 619 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 620 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 621 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 622 //SDMA_PGFSM_CONFIG 623 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 624 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 625 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 626 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 627 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 628 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 629 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 630 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 631 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 632 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 633 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 634 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 635 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 636 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 637 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 638 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 639 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 640 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 641 //SDMA_PGFSM_WRITE 642 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 643 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 644 //SDMA_PGFSM_READ 645 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 646 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 647 //SDMA0_EDC_CONFIG 648 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 649 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 650 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 651 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 652 //SDMA0_BA_THRESHOLD 653 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 654 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 655 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 656 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 657 //SDMA0_ID 658 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 659 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 660 //SDMA0_VERSION 661 #define SDMA0_VERSION__MINVER__SHIFT 0x0 662 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 663 #define SDMA0_VERSION__REV__SHIFT 0x10 664 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 665 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 666 #define SDMA0_VERSION__REV_MASK 0x003F0000L 667 //SDMA0_EDC_COUNTER 668 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 669 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 670 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 671 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 672 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 673 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 674 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 675 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 676 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 677 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 678 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 679 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 680 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 681 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 682 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 683 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 684 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 685 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 686 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 687 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 688 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 689 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 690 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 691 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 692 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 693 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 694 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 695 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 696 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 697 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 698 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 699 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 700 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 701 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 702 //SDMA0_EDC_COUNTER_CLEAR 703 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 704 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 705 //SDMA0_STATUS2_REG 706 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 707 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 708 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 709 #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 710 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 711 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 712 //SDMA0_ATOMIC_CNTL 713 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 714 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 715 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 716 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 717 //SDMA0_ATOMIC_PREOP_LO 718 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 719 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 720 //SDMA0_ATOMIC_PREOP_HI 721 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 722 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 723 //SDMA0_UTCL1_CNTL 724 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 725 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 726 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 727 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 728 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 729 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 730 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 731 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 732 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 733 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 734 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 735 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 736 //SDMA0_UTCL1_WATERMK 737 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 738 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 739 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 740 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 741 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 742 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 743 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 744 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 745 //SDMA0_UTCL1_RD_STATUS 746 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 747 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 748 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 749 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 750 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 751 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 752 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 753 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 754 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 755 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 756 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 757 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 758 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 759 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 760 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 761 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 762 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 763 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 764 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 765 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 766 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 767 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 768 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 769 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 770 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 771 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 772 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 773 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 774 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 775 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 776 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 777 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 778 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 779 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 780 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 781 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 782 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 783 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 784 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 785 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 786 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 787 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 788 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 789 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 790 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 791 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 792 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 793 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 794 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 795 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 796 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 797 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 798 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 799 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 800 //SDMA0_UTCL1_WR_STATUS 801 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 802 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 803 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 804 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 805 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 806 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 807 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 808 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 809 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 810 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 811 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 812 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 813 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 814 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 815 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 816 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 817 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 818 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 819 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 820 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 821 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 822 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 823 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 824 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 825 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 826 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 827 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 828 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 829 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 830 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 831 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 832 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 833 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 834 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 835 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 836 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 837 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 838 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 839 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 840 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 841 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 842 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 843 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 844 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 845 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 846 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 847 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 848 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 849 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 850 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 851 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 852 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 853 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 854 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 855 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 856 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 857 //SDMA0_UTCL1_INV0 858 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 859 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 860 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 861 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 862 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 863 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 864 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 865 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 866 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 867 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 868 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 869 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 870 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 871 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 872 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 873 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 874 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 875 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 876 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 877 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 878 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 879 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 880 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 881 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 882 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 883 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 884 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 885 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 886 //SDMA0_UTCL1_INV1 887 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 888 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 889 //SDMA0_UTCL1_INV2 890 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 891 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 892 //SDMA0_UTCL1_RD_XNACK0 893 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 894 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 895 //SDMA0_UTCL1_RD_XNACK1 896 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 897 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 898 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 899 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 900 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 901 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 902 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 903 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 904 //SDMA0_UTCL1_WR_XNACK0 905 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 906 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 907 //SDMA0_UTCL1_WR_XNACK1 908 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 909 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 910 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 911 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 912 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 913 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 914 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 915 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 916 //SDMA0_UTCL1_TIMEOUT 917 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 918 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 919 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 920 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 921 //SDMA0_UTCL1_PAGE 922 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 923 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 924 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 925 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 926 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 927 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 928 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 929 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 930 //SDMA0_POWER_CNTL_IDLE 931 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 932 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 933 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 934 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 935 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 936 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 937 //SDMA0_RELAX_ORDERING_LUT 938 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 939 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 940 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 941 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 942 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 943 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 944 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 945 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 946 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 947 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 948 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 949 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 950 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 951 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 952 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 953 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 954 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 955 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 956 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 957 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 958 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 959 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 960 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 961 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 962 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 963 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 964 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 965 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 966 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 967 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 968 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 969 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 970 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 971 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 972 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 973 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 974 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 975 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 976 //SDMA0_CHICKEN_BITS_2 977 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 978 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 979 //SDMA0_STATUS3_REG 980 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 981 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 982 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 983 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 984 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 985 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 986 //SDMA0_PHYSICAL_ADDR_LO 987 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 988 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 989 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 990 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 991 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 992 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 993 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 994 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 995 //SDMA0_PHYSICAL_ADDR_HI 996 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 997 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 998 //SDMA0_PHASE2_QUANTUM 999 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1000 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1001 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1002 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1003 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1004 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1005 //SDMA0_ERROR_LOG 1006 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1007 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1008 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1009 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1010 //SDMA0_PUB_DUMMY_REG0 1011 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1012 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1013 //SDMA0_PUB_DUMMY_REG1 1014 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1015 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1016 //SDMA0_PUB_DUMMY_REG2 1017 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1018 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1019 //SDMA0_PUB_DUMMY_REG3 1020 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1021 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1022 //SDMA0_F32_COUNTER 1023 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1024 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1025 //SDMA0_UNBREAKABLE 1026 #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1027 #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1028 //SDMA0_PERFMON_CNTL 1029 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1030 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1031 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1032 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1033 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1034 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1035 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1036 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1037 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1038 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1039 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1040 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1041 //SDMA0_PERFCOUNTER0_RESULT 1042 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1043 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1044 //SDMA0_PERFCOUNTER1_RESULT 1045 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1046 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1047 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1048 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1049 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1050 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1051 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1052 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1053 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1054 //SDMA0_CRD_CNTL 1055 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1056 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1057 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1058 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1059 //SDMA0_MMHUB_TRUSTLVL 1060 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1061 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1062 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1063 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1064 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1065 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1066 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1067 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1068 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1069 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1070 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1071 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1072 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1073 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1074 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1075 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1076 //SDMA0_GPU_IOV_VIOLATION_LOG 1077 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1078 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1079 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1080 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1081 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1082 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1083 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1084 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1085 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1089 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1090 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1091 //SDMA0_ULV_CNTL 1092 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1093 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1094 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1095 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1096 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1097 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1098 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1099 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1100 //SDMA0_EA_DBIT_ADDR_DATA 1101 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1102 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1103 //SDMA0_EA_DBIT_ADDR_INDEX 1104 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1105 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1106 //SDMA0_GFX_RB_CNTL 1107 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1108 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1109 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1110 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1111 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1112 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1113 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1114 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1115 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1116 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1117 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1118 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1119 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1120 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1121 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1122 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1123 //SDMA0_GFX_RB_BASE 1124 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1125 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1126 //SDMA0_GFX_RB_BASE_HI 1127 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1128 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1129 //SDMA0_GFX_RB_RPTR 1130 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1131 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1132 //SDMA0_GFX_RB_RPTR_HI 1133 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1134 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1135 //SDMA0_GFX_RB_WPTR 1136 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1137 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1138 //SDMA0_GFX_RB_WPTR_HI 1139 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1140 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1141 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1142 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1143 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1144 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1145 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1146 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1147 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1148 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1149 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1150 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1151 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1152 //SDMA0_GFX_RB_RPTR_ADDR_HI 1153 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1154 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1155 //SDMA0_GFX_RB_RPTR_ADDR_LO 1156 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1157 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1158 //SDMA0_GFX_IB_CNTL 1159 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1160 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1161 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1162 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1163 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1164 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1165 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1166 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1167 //SDMA0_GFX_IB_RPTR 1168 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1169 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1170 //SDMA0_GFX_IB_OFFSET 1171 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1172 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1173 //SDMA0_GFX_IB_BASE_LO 1174 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1175 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1176 //SDMA0_GFX_IB_BASE_HI 1177 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1178 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1179 //SDMA0_GFX_IB_SIZE 1180 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1181 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1182 //SDMA0_GFX_SKIP_CNTL 1183 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1184 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1185 //SDMA0_GFX_CONTEXT_STATUS 1186 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1187 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1188 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1189 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1190 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1191 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1192 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1193 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1194 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1195 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1196 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1197 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1198 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1199 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1200 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1201 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1202 //SDMA0_GFX_DOORBELL 1203 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1204 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1205 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1206 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1207 //SDMA0_GFX_CONTEXT_CNTL 1208 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1209 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1210 //SDMA0_GFX_STATUS 1211 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1212 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1213 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1214 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1215 //SDMA0_GFX_DOORBELL_LOG 1216 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1217 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1218 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1219 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1220 //SDMA0_GFX_WATERMARK 1221 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1222 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1223 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1224 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1225 //SDMA0_GFX_DOORBELL_OFFSET 1226 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1227 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1228 //SDMA0_GFX_CSA_ADDR_LO 1229 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1230 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1231 //SDMA0_GFX_CSA_ADDR_HI 1232 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1233 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1234 //SDMA0_GFX_IB_SUB_REMAIN 1235 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1236 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1237 //SDMA0_GFX_PREEMPT 1238 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1239 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1240 //SDMA0_GFX_DUMMY_REG 1241 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1242 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1243 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1244 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1245 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1246 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1247 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1248 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1249 //SDMA0_GFX_RB_AQL_CNTL 1250 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1251 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1252 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1253 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1254 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1255 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1256 //SDMA0_GFX_MINOR_PTR_UPDATE 1257 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1258 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1259 //SDMA0_GFX_MIDCMD_DATA0 1260 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1261 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1262 //SDMA0_GFX_MIDCMD_DATA1 1263 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1264 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1265 //SDMA0_GFX_MIDCMD_DATA2 1266 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1267 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1268 //SDMA0_GFX_MIDCMD_DATA3 1269 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1270 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1271 //SDMA0_GFX_MIDCMD_DATA4 1272 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1273 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1274 //SDMA0_GFX_MIDCMD_DATA5 1275 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1276 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1277 //SDMA0_GFX_MIDCMD_DATA6 1278 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1279 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1280 //SDMA0_GFX_MIDCMD_DATA7 1281 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1282 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1283 //SDMA0_GFX_MIDCMD_DATA8 1284 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1285 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1286 //SDMA0_GFX_MIDCMD_CNTL 1287 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1288 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1289 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1290 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1291 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1292 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1293 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1294 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1295 //SDMA0_PAGE_RB_CNTL 1296 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1297 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1298 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1299 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1300 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1301 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1302 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1303 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1304 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1305 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1306 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1307 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1308 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1309 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1310 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1311 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1312 //SDMA0_PAGE_RB_BASE 1313 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1314 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1315 //SDMA0_PAGE_RB_BASE_HI 1316 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1317 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1318 //SDMA0_PAGE_RB_RPTR 1319 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1320 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1321 //SDMA0_PAGE_RB_RPTR_HI 1322 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1323 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1324 //SDMA0_PAGE_RB_WPTR 1325 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1326 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1327 //SDMA0_PAGE_RB_WPTR_HI 1328 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1329 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1330 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1331 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1332 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1333 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1334 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1335 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1336 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1337 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1338 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1339 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1340 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1341 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1342 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1343 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1344 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1345 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1346 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1347 //SDMA0_PAGE_IB_CNTL 1348 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1349 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1350 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1351 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1352 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1353 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1354 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1355 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1356 //SDMA0_PAGE_IB_RPTR 1357 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1358 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1359 //SDMA0_PAGE_IB_OFFSET 1360 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1361 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1362 //SDMA0_PAGE_IB_BASE_LO 1363 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1364 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1365 //SDMA0_PAGE_IB_BASE_HI 1366 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1367 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1368 //SDMA0_PAGE_IB_SIZE 1369 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1370 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1371 //SDMA0_PAGE_SKIP_CNTL 1372 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1373 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1374 //SDMA0_PAGE_CONTEXT_STATUS 1375 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1376 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1377 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1378 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1379 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1380 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1381 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1382 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1383 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1384 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1385 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1386 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1387 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1388 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1389 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1390 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1391 //SDMA0_PAGE_DOORBELL 1392 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1393 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1394 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1395 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1396 //SDMA0_PAGE_STATUS 1397 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1398 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1399 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1400 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1401 //SDMA0_PAGE_DOORBELL_LOG 1402 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1403 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1404 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1405 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1406 //SDMA0_PAGE_WATERMARK 1407 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1408 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1409 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1410 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1411 //SDMA0_PAGE_DOORBELL_OFFSET 1412 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1413 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1414 //SDMA0_PAGE_CSA_ADDR_LO 1415 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1416 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1417 //SDMA0_PAGE_CSA_ADDR_HI 1418 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1419 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1420 //SDMA0_PAGE_IB_SUB_REMAIN 1421 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1422 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1423 //SDMA0_PAGE_PREEMPT 1424 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1425 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1426 //SDMA0_PAGE_DUMMY_REG 1427 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1428 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1429 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1430 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1431 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1432 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1433 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1434 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1435 //SDMA0_PAGE_RB_AQL_CNTL 1436 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1437 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1438 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1439 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1440 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1441 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1442 //SDMA0_PAGE_MINOR_PTR_UPDATE 1443 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1444 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1445 //SDMA0_PAGE_MIDCMD_DATA0 1446 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1447 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1448 //SDMA0_PAGE_MIDCMD_DATA1 1449 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1450 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1451 //SDMA0_PAGE_MIDCMD_DATA2 1452 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1453 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1454 //SDMA0_PAGE_MIDCMD_DATA3 1455 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1456 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1457 //SDMA0_PAGE_MIDCMD_DATA4 1458 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1459 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1460 //SDMA0_PAGE_MIDCMD_DATA5 1461 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1462 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1463 //SDMA0_PAGE_MIDCMD_DATA6 1464 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1465 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1466 //SDMA0_PAGE_MIDCMD_DATA7 1467 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1468 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1469 //SDMA0_PAGE_MIDCMD_DATA8 1470 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1471 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1472 //SDMA0_PAGE_MIDCMD_CNTL 1473 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1474 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1475 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1476 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1477 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1478 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1479 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1480 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1481 //SDMA0_RLC0_RB_CNTL 1482 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1483 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1484 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1485 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1486 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1487 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1488 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1489 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1490 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1491 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1492 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1493 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1494 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1495 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1496 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1497 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1498 //SDMA0_RLC0_RB_BASE 1499 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1500 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1501 //SDMA0_RLC0_RB_BASE_HI 1502 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1503 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1504 //SDMA0_RLC0_RB_RPTR 1505 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1506 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1507 //SDMA0_RLC0_RB_RPTR_HI 1508 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1509 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1510 //SDMA0_RLC0_RB_WPTR 1511 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1512 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1513 //SDMA0_RLC0_RB_WPTR_HI 1514 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1515 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1516 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1517 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1518 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1519 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1520 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1521 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1522 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1523 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1524 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1525 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1526 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1527 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1528 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1529 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1530 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1531 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1532 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1533 //SDMA0_RLC0_IB_CNTL 1534 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1535 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1536 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1537 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1538 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1539 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1540 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1541 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1542 //SDMA0_RLC0_IB_RPTR 1543 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1544 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1545 //SDMA0_RLC0_IB_OFFSET 1546 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1547 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1548 //SDMA0_RLC0_IB_BASE_LO 1549 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1550 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1551 //SDMA0_RLC0_IB_BASE_HI 1552 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1553 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1554 //SDMA0_RLC0_IB_SIZE 1555 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1556 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1557 //SDMA0_RLC0_SKIP_CNTL 1558 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1559 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1560 //SDMA0_RLC0_CONTEXT_STATUS 1561 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1562 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1563 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1564 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1565 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1566 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1567 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1568 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1569 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1570 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1571 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1572 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1573 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1574 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1575 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1576 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1577 //SDMA0_RLC0_DOORBELL 1578 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1579 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1580 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1581 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1582 //SDMA0_RLC0_STATUS 1583 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1584 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1585 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1586 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1587 //SDMA0_RLC0_DOORBELL_LOG 1588 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1589 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1590 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1591 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1592 //SDMA0_RLC0_WATERMARK 1593 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1594 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1595 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1596 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1597 //SDMA0_RLC0_DOORBELL_OFFSET 1598 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1599 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1600 //SDMA0_RLC0_CSA_ADDR_LO 1601 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1602 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1603 //SDMA0_RLC0_CSA_ADDR_HI 1604 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1605 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1606 //SDMA0_RLC0_IB_SUB_REMAIN 1607 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1608 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1609 //SDMA0_RLC0_PREEMPT 1610 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1611 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1612 //SDMA0_RLC0_DUMMY_REG 1613 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1614 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1615 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1616 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1617 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1618 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1619 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1620 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1621 //SDMA0_RLC0_RB_AQL_CNTL 1622 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1623 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1624 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1625 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1626 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1627 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1628 //SDMA0_RLC0_MINOR_PTR_UPDATE 1629 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1630 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1631 //SDMA0_RLC0_MIDCMD_DATA0 1632 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1633 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1634 //SDMA0_RLC0_MIDCMD_DATA1 1635 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1636 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1637 //SDMA0_RLC0_MIDCMD_DATA2 1638 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1639 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1640 //SDMA0_RLC0_MIDCMD_DATA3 1641 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1642 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1643 //SDMA0_RLC0_MIDCMD_DATA4 1644 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1645 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1646 //SDMA0_RLC0_MIDCMD_DATA5 1647 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1648 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1649 //SDMA0_RLC0_MIDCMD_DATA6 1650 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1651 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1652 //SDMA0_RLC0_MIDCMD_DATA7 1653 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1654 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1655 //SDMA0_RLC0_MIDCMD_DATA8 1656 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1657 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1658 //SDMA0_RLC0_MIDCMD_CNTL 1659 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1660 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1661 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1662 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1663 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1664 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1665 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1666 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1667 //SDMA0_RLC1_RB_CNTL 1668 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1669 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1670 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1671 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1672 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1673 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1674 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1675 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1676 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1677 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1678 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1679 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1680 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1681 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1682 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1683 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1684 //SDMA0_RLC1_RB_BASE 1685 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1686 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1687 //SDMA0_RLC1_RB_BASE_HI 1688 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1689 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1690 //SDMA0_RLC1_RB_RPTR 1691 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1692 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1693 //SDMA0_RLC1_RB_RPTR_HI 1694 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1695 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1696 //SDMA0_RLC1_RB_WPTR 1697 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1698 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1699 //SDMA0_RLC1_RB_WPTR_HI 1700 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1701 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1702 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1703 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1704 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1705 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1706 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1707 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1708 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1709 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1710 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1711 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1712 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1713 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1714 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1715 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1716 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1717 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1718 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1719 //SDMA0_RLC1_IB_CNTL 1720 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1721 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1722 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1723 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1724 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1725 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1726 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1727 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1728 //SDMA0_RLC1_IB_RPTR 1729 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1730 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1731 //SDMA0_RLC1_IB_OFFSET 1732 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1733 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1734 //SDMA0_RLC1_IB_BASE_LO 1735 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1736 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1737 //SDMA0_RLC1_IB_BASE_HI 1738 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1739 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1740 //SDMA0_RLC1_IB_SIZE 1741 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1742 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1743 //SDMA0_RLC1_SKIP_CNTL 1744 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1745 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1746 //SDMA0_RLC1_CONTEXT_STATUS 1747 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1748 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1749 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1750 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1751 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1752 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1753 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1754 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1755 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1756 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1757 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1758 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1759 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1760 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1761 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1762 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1763 //SDMA0_RLC1_DOORBELL 1764 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1765 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1766 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1767 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1768 //SDMA0_RLC1_STATUS 1769 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1770 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1771 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1772 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1773 //SDMA0_RLC1_DOORBELL_LOG 1774 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1775 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1776 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1777 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1778 //SDMA0_RLC1_WATERMARK 1779 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1780 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1781 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1782 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1783 //SDMA0_RLC1_DOORBELL_OFFSET 1784 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1785 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1786 //SDMA0_RLC1_CSA_ADDR_LO 1787 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1788 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1789 //SDMA0_RLC1_CSA_ADDR_HI 1790 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1791 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1792 //SDMA0_RLC1_IB_SUB_REMAIN 1793 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1794 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1795 //SDMA0_RLC1_PREEMPT 1796 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1797 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1798 //SDMA0_RLC1_DUMMY_REG 1799 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1800 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1801 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1802 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1803 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1804 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1805 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1806 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1807 //SDMA0_RLC1_RB_AQL_CNTL 1808 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1809 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1810 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1811 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1812 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1813 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1814 //SDMA0_RLC1_MINOR_PTR_UPDATE 1815 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1816 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1817 //SDMA0_RLC1_MIDCMD_DATA0 1818 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1819 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1820 //SDMA0_RLC1_MIDCMD_DATA1 1821 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1822 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1823 //SDMA0_RLC1_MIDCMD_DATA2 1824 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1825 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1826 //SDMA0_RLC1_MIDCMD_DATA3 1827 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1828 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1829 //SDMA0_RLC1_MIDCMD_DATA4 1830 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1831 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1832 //SDMA0_RLC1_MIDCMD_DATA5 1833 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1834 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1835 //SDMA0_RLC1_MIDCMD_DATA6 1836 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1837 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1838 //SDMA0_RLC1_MIDCMD_DATA7 1839 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1840 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1841 //SDMA0_RLC1_MIDCMD_DATA8 1842 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1843 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1844 //SDMA0_RLC1_MIDCMD_CNTL 1845 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1846 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1847 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1848 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1849 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1850 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1851 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1852 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1853 1854 #endif 1855