1 /* $NetBSD: sdma0_4_2_offset.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma0_4_2_0_OFFSET_HEADER 24 #define _sdma0_4_2_0_OFFSET_HEADER 25 26 27 28 // addressBlock: sdma0_sdma0dec 29 // base address: 0x4980 30 #define mmSDMA0_UCODE_ADDR 0x0000 31 #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 32 #define mmSDMA0_UCODE_DATA 0x0001 33 #define mmSDMA0_UCODE_DATA_BASE_IDX 0 34 #define mmSDMA0_VM_CNTL 0x0004 35 #define mmSDMA0_VM_CNTL_BASE_IDX 0 36 #define mmSDMA0_VM_CTX_LO 0x0005 37 #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 38 #define mmSDMA0_VM_CTX_HI 0x0006 39 #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 40 #define mmSDMA0_ACTIVE_FCN_ID 0x0007 41 #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 42 #define mmSDMA0_VM_CTX_CNTL 0x0008 43 #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 44 #define mmSDMA0_VIRT_RESET_REQ 0x0009 45 #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 46 #define mmSDMA0_VF_ENABLE 0x000a 47 #define mmSDMA0_VF_ENABLE_BASE_IDX 0 48 #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b 49 #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 50 #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c 51 #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 52 #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d 53 #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 54 #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e 55 #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 56 #define mmSDMA0_PUB_REG_TYPE0 0x000f 57 #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 58 #define mmSDMA0_PUB_REG_TYPE1 0x0010 59 #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 60 #define mmSDMA0_PUB_REG_TYPE2 0x0011 61 #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 62 #define mmSDMA0_PUB_REG_TYPE3 0x0012 63 #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 64 #define mmSDMA0_MMHUB_CNTL 0x0013 65 #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 66 #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 67 #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 68 #define mmSDMA0_POWER_CNTL 0x001a 69 #define mmSDMA0_POWER_CNTL_BASE_IDX 0 70 #define mmSDMA0_CLK_CTRL 0x001b 71 #define mmSDMA0_CLK_CTRL_BASE_IDX 0 72 #define mmSDMA0_CNTL 0x001c 73 #define mmSDMA0_CNTL_BASE_IDX 0 74 #define mmSDMA0_CHICKEN_BITS 0x001d 75 #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 76 #define mmSDMA0_GB_ADDR_CONFIG 0x001e 77 #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 78 #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f 79 #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 80 #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 81 #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 83 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 84 #define mmSDMA0_RB_RPTR_FETCH 0x0022 85 #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 86 #define mmSDMA0_IB_OFFSET_FETCH 0x0023 87 #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 88 #define mmSDMA0_PROGRAM 0x0024 89 #define mmSDMA0_PROGRAM_BASE_IDX 0 90 #define mmSDMA0_STATUS_REG 0x0025 91 #define mmSDMA0_STATUS_REG_BASE_IDX 0 92 #define mmSDMA0_STATUS1_REG 0x0026 93 #define mmSDMA0_STATUS1_REG_BASE_IDX 0 94 #define mmSDMA0_RD_BURST_CNTL 0x0027 95 #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 96 #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 97 #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 98 #define mmSDMA0_UCODE_CHECKSUM 0x0029 99 #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 100 #define mmSDMA0_F32_CNTL 0x002a 101 #define mmSDMA0_F32_CNTL_BASE_IDX 0 102 #define mmSDMA0_FREEZE 0x002b 103 #define mmSDMA0_FREEZE_BASE_IDX 0 104 #define mmSDMA0_PHASE0_QUANTUM 0x002c 105 #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 106 #define mmSDMA0_PHASE1_QUANTUM 0x002d 107 #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 108 #define mmSDMA_POWER_GATING 0x002e 109 #define mmSDMA_POWER_GATING_BASE_IDX 0 110 #define mmSDMA_PGFSM_CONFIG 0x002f 111 #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 112 #define mmSDMA_PGFSM_WRITE 0x0030 113 #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 114 #define mmSDMA_PGFSM_READ 0x0031 115 #define mmSDMA_PGFSM_READ_BASE_IDX 0 116 #define mmSDMA0_EDC_CONFIG 0x0032 117 #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 118 #define mmSDMA0_BA_THRESHOLD 0x0033 119 #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 120 #define mmSDMA0_ID 0x0034 121 #define mmSDMA0_ID_BASE_IDX 0 122 #define mmSDMA0_VERSION 0x0035 123 #define mmSDMA0_VERSION_BASE_IDX 0 124 #define mmSDMA0_EDC_COUNTER 0x0036 125 #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 126 #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 127 #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 128 #define mmSDMA0_STATUS2_REG 0x0038 129 #define mmSDMA0_STATUS2_REG_BASE_IDX 0 130 #define mmSDMA0_ATOMIC_CNTL 0x0039 131 #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 132 #define mmSDMA0_ATOMIC_PREOP_LO 0x003a 133 #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 134 #define mmSDMA0_ATOMIC_PREOP_HI 0x003b 135 #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 136 #define mmSDMA0_UTCL1_CNTL 0x003c 137 #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 138 #define mmSDMA0_UTCL1_WATERMK 0x003d 139 #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 140 #define mmSDMA0_UTCL1_RD_STATUS 0x003e 141 #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 142 #define mmSDMA0_UTCL1_WR_STATUS 0x003f 143 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 144 #define mmSDMA0_UTCL1_INV0 0x0040 145 #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 146 #define mmSDMA0_UTCL1_INV1 0x0041 147 #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 148 #define mmSDMA0_UTCL1_INV2 0x0042 149 #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 150 #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 151 #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 152 #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 153 #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 154 #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 155 #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 156 #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 157 #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 158 #define mmSDMA0_UTCL1_TIMEOUT 0x0047 159 #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 160 #define mmSDMA0_UTCL1_PAGE 0x0048 161 #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 162 #define mmSDMA0_POWER_CNTL_IDLE 0x0049 163 #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 164 #define mmSDMA0_RELAX_ORDERING_LUT 0x004a 165 #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 166 #define mmSDMA0_CHICKEN_BITS_2 0x004b 167 #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 168 #define mmSDMA0_STATUS3_REG 0x004c 169 #define mmSDMA0_STATUS3_REG_BASE_IDX 0 170 #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d 171 #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 172 #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e 173 #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 174 #define mmSDMA0_PHASE2_QUANTUM 0x004f 175 #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 176 #define mmSDMA0_ERROR_LOG 0x0050 177 #define mmSDMA0_ERROR_LOG_BASE_IDX 0 178 #define mmSDMA0_PUB_DUMMY_REG0 0x0051 179 #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 180 #define mmSDMA0_PUB_DUMMY_REG1 0x0052 181 #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 182 #define mmSDMA0_PUB_DUMMY_REG2 0x0053 183 #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 184 #define mmSDMA0_PUB_DUMMY_REG3 0x0054 185 #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 186 #define mmSDMA0_F32_COUNTER 0x0055 187 #define mmSDMA0_F32_COUNTER_BASE_IDX 0 188 #define mmSDMA0_PERFMON_CNTL 0x0057 189 #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 190 #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 191 #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 192 #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 193 #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 194 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 195 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 196 #define mmSDMA0_CRD_CNTL 0x005b 197 #define mmSDMA0_CRD_CNTL_BASE_IDX 0 198 #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d 199 #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 200 #define mmSDMA0_ULV_CNTL 0x005e 201 #define mmSDMA0_ULV_CNTL_BASE_IDX 0 202 #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 203 #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 204 #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 205 #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 206 #define mmSDMA0_GFX_RB_CNTL 0x0080 207 #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 208 #define mmSDMA0_GFX_RB_BASE 0x0081 209 #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 210 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 211 #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 212 #define mmSDMA0_GFX_RB_RPTR 0x0083 213 #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 214 #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 215 #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 216 #define mmSDMA0_GFX_RB_WPTR 0x0085 217 #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 218 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 219 #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 220 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 221 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 222 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 223 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 224 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 225 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 226 #define mmSDMA0_GFX_IB_CNTL 0x008a 227 #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 228 #define mmSDMA0_GFX_IB_RPTR 0x008b 229 #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 230 #define mmSDMA0_GFX_IB_OFFSET 0x008c 231 #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 232 #define mmSDMA0_GFX_IB_BASE_LO 0x008d 233 #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 234 #define mmSDMA0_GFX_IB_BASE_HI 0x008e 235 #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 236 #define mmSDMA0_GFX_IB_SIZE 0x008f 237 #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 238 #define mmSDMA0_GFX_SKIP_CNTL 0x0090 239 #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 240 #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 241 #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 242 #define mmSDMA0_GFX_DOORBELL 0x0092 243 #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 244 #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 245 #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 246 #define mmSDMA0_GFX_STATUS 0x00a8 247 #define mmSDMA0_GFX_STATUS_BASE_IDX 0 248 #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 249 #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 250 #define mmSDMA0_GFX_WATERMARK 0x00aa 251 #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 252 #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab 253 #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 254 #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac 255 #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 256 #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad 257 #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 258 #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af 259 #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 260 #define mmSDMA0_GFX_PREEMPT 0x00b0 261 #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 262 #define mmSDMA0_GFX_DUMMY_REG 0x00b1 263 #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 264 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 265 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 267 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 268 #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 269 #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 270 #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 271 #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 272 #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 273 #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 274 #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 275 #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 276 #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 277 #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 278 #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 279 #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 280 #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 281 #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 282 #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 283 #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 284 #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 285 #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 286 #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 287 #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 288 #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 289 #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 290 #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 291 #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 292 #define mmSDMA0_PAGE_RB_CNTL 0x00e0 293 #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 294 #define mmSDMA0_PAGE_RB_BASE 0x00e1 295 #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 296 #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 297 #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 298 #define mmSDMA0_PAGE_RB_RPTR 0x00e3 299 #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 300 #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 301 #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 302 #define mmSDMA0_PAGE_RB_WPTR 0x00e5 303 #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 304 #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 305 #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 306 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 307 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 308 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 309 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 310 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 311 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 312 #define mmSDMA0_PAGE_IB_CNTL 0x00ea 313 #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 314 #define mmSDMA0_PAGE_IB_RPTR 0x00eb 315 #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 316 #define mmSDMA0_PAGE_IB_OFFSET 0x00ec 317 #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 318 #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed 319 #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 320 #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee 321 #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 322 #define mmSDMA0_PAGE_IB_SIZE 0x00ef 323 #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 324 #define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 325 #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 326 #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 327 #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 328 #define mmSDMA0_PAGE_DOORBELL 0x00f2 329 #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 330 #define mmSDMA0_PAGE_STATUS 0x0108 331 #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 332 #define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 333 #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 334 #define mmSDMA0_PAGE_WATERMARK 0x010a 335 #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 336 #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b 337 #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 338 #define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c 339 #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 340 #define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d 341 #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 342 #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f 343 #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 344 #define mmSDMA0_PAGE_PREEMPT 0x0110 345 #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 346 #define mmSDMA0_PAGE_DUMMY_REG 0x0111 347 #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 348 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 349 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 350 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 351 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 352 #define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 353 #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 354 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 355 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 356 #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 357 #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 358 #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 359 #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 360 #define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 361 #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 362 #define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 363 #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 364 #define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 365 #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 366 #define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 367 #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 368 #define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 369 #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 370 #define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 371 #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 372 #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 373 #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 374 #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 375 #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 376 #define mmSDMA0_RLC0_RB_CNTL 0x0140 377 #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 378 #define mmSDMA0_RLC0_RB_BASE 0x0141 379 #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 380 #define mmSDMA0_RLC0_RB_BASE_HI 0x0142 381 #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 382 #define mmSDMA0_RLC0_RB_RPTR 0x0143 383 #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 384 #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 385 #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 386 #define mmSDMA0_RLC0_RB_WPTR 0x0145 387 #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 388 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 389 #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 390 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 391 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 392 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 393 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 394 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 395 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 396 #define mmSDMA0_RLC0_IB_CNTL 0x014a 397 #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 398 #define mmSDMA0_RLC0_IB_RPTR 0x014b 399 #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 400 #define mmSDMA0_RLC0_IB_OFFSET 0x014c 401 #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 402 #define mmSDMA0_RLC0_IB_BASE_LO 0x014d 403 #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 404 #define mmSDMA0_RLC0_IB_BASE_HI 0x014e 405 #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 406 #define mmSDMA0_RLC0_IB_SIZE 0x014f 407 #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 408 #define mmSDMA0_RLC0_SKIP_CNTL 0x0150 409 #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 410 #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 411 #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 412 #define mmSDMA0_RLC0_DOORBELL 0x0152 413 #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 414 #define mmSDMA0_RLC0_STATUS 0x0168 415 #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 416 #define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 417 #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 418 #define mmSDMA0_RLC0_WATERMARK 0x016a 419 #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 420 #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b 421 #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 422 #define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c 423 #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 424 #define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d 425 #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 426 #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f 427 #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 428 #define mmSDMA0_RLC0_PREEMPT 0x0170 429 #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 430 #define mmSDMA0_RLC0_DUMMY_REG 0x0171 431 #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 432 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 433 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 434 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 435 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 436 #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 437 #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 438 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 439 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 440 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 441 #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 442 #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 443 #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 444 #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 445 #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 446 #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 447 #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 448 #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 449 #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 450 #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 451 #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 452 #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 453 #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 454 #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 455 #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 456 #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 457 #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 458 #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 459 #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 460 #define mmSDMA0_RLC1_RB_CNTL 0x01a0 461 #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 462 #define mmSDMA0_RLC1_RB_BASE 0x01a1 463 #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 464 #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 465 #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 466 #define mmSDMA0_RLC1_RB_RPTR 0x01a3 467 #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 468 #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 469 #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 470 #define mmSDMA0_RLC1_RB_WPTR 0x01a5 471 #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 472 #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 473 #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 474 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 475 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 476 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 477 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 478 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 479 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 480 #define mmSDMA0_RLC1_IB_CNTL 0x01aa 481 #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 482 #define mmSDMA0_RLC1_IB_RPTR 0x01ab 483 #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 484 #define mmSDMA0_RLC1_IB_OFFSET 0x01ac 485 #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 486 #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad 487 #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 488 #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae 489 #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 490 #define mmSDMA0_RLC1_IB_SIZE 0x01af 491 #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 492 #define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 493 #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 494 #define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 495 #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 496 #define mmSDMA0_RLC1_DOORBELL 0x01b2 497 #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 498 #define mmSDMA0_RLC1_STATUS 0x01c8 499 #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 500 #define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 501 #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 502 #define mmSDMA0_RLC1_WATERMARK 0x01ca 503 #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 504 #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb 505 #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 506 #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc 507 #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 508 #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd 509 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 510 #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf 511 #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 512 #define mmSDMA0_RLC1_PREEMPT 0x01d0 513 #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 514 #define mmSDMA0_RLC1_DUMMY_REG 0x01d1 515 #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 516 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 517 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 518 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 519 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 520 #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 521 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 522 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 523 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 524 #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 525 #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 526 #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 527 #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 528 #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 529 #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 530 #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 531 #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 532 #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 533 #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 534 #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 535 #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 536 #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 537 #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 538 #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 539 #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 540 #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 541 #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 542 #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 543 #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 544 #define mmSDMA0_RLC2_RB_CNTL 0x0200 545 #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 546 #define mmSDMA0_RLC2_RB_BASE 0x0201 547 #define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 548 #define mmSDMA0_RLC2_RB_BASE_HI 0x0202 549 #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 550 #define mmSDMA0_RLC2_RB_RPTR 0x0203 551 #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 552 #define mmSDMA0_RLC2_RB_RPTR_HI 0x0204 553 #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 554 #define mmSDMA0_RLC2_RB_WPTR 0x0205 555 #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 556 #define mmSDMA0_RLC2_RB_WPTR_HI 0x0206 557 #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 558 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 559 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 560 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x0208 561 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 562 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x0209 563 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 564 #define mmSDMA0_RLC2_IB_CNTL 0x020a 565 #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 566 #define mmSDMA0_RLC2_IB_RPTR 0x020b 567 #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 568 #define mmSDMA0_RLC2_IB_OFFSET 0x020c 569 #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 570 #define mmSDMA0_RLC2_IB_BASE_LO 0x020d 571 #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 572 #define mmSDMA0_RLC2_IB_BASE_HI 0x020e 573 #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 574 #define mmSDMA0_RLC2_IB_SIZE 0x020f 575 #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 576 #define mmSDMA0_RLC2_SKIP_CNTL 0x0210 577 #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 578 #define mmSDMA0_RLC2_CONTEXT_STATUS 0x0211 579 #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 580 #define mmSDMA0_RLC2_DOORBELL 0x0212 581 #define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 582 #define mmSDMA0_RLC2_STATUS 0x0228 583 #define mmSDMA0_RLC2_STATUS_BASE_IDX 0 584 #define mmSDMA0_RLC2_DOORBELL_LOG 0x0229 585 #define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 586 #define mmSDMA0_RLC2_WATERMARK 0x022a 587 #define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 588 #define mmSDMA0_RLC2_DOORBELL_OFFSET 0x022b 589 #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 590 #define mmSDMA0_RLC2_CSA_ADDR_LO 0x022c 591 #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 592 #define mmSDMA0_RLC2_CSA_ADDR_HI 0x022d 593 #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 594 #define mmSDMA0_RLC2_IB_SUB_REMAIN 0x022f 595 #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 596 #define mmSDMA0_RLC2_PREEMPT 0x0230 597 #define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 598 #define mmSDMA0_RLC2_DUMMY_REG 0x0231 599 #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 600 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 601 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 602 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 603 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 604 #define mmSDMA0_RLC2_RB_AQL_CNTL 0x0234 605 #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 606 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0235 607 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 608 #define mmSDMA0_RLC2_MIDCMD_DATA0 0x0240 609 #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 610 #define mmSDMA0_RLC2_MIDCMD_DATA1 0x0241 611 #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 612 #define mmSDMA0_RLC2_MIDCMD_DATA2 0x0242 613 #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 614 #define mmSDMA0_RLC2_MIDCMD_DATA3 0x0243 615 #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 616 #define mmSDMA0_RLC2_MIDCMD_DATA4 0x0244 617 #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 618 #define mmSDMA0_RLC2_MIDCMD_DATA5 0x0245 619 #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 620 #define mmSDMA0_RLC2_MIDCMD_DATA6 0x0246 621 #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 622 #define mmSDMA0_RLC2_MIDCMD_DATA7 0x0247 623 #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 624 #define mmSDMA0_RLC2_MIDCMD_DATA8 0x0248 625 #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 626 #define mmSDMA0_RLC2_MIDCMD_CNTL 0x0249 627 #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 628 #define mmSDMA0_RLC3_RB_CNTL 0x0260 629 #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 630 #define mmSDMA0_RLC3_RB_BASE 0x0261 631 #define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 632 #define mmSDMA0_RLC3_RB_BASE_HI 0x0262 633 #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 634 #define mmSDMA0_RLC3_RB_RPTR 0x0263 635 #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 636 #define mmSDMA0_RLC3_RB_RPTR_HI 0x0264 637 #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 638 #define mmSDMA0_RLC3_RB_WPTR 0x0265 639 #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 640 #define mmSDMA0_RLC3_RB_WPTR_HI 0x0266 641 #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 642 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 643 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 644 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0268 645 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 646 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0269 647 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 648 #define mmSDMA0_RLC3_IB_CNTL 0x026a 649 #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 650 #define mmSDMA0_RLC3_IB_RPTR 0x026b 651 #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 652 #define mmSDMA0_RLC3_IB_OFFSET 0x026c 653 #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 654 #define mmSDMA0_RLC3_IB_BASE_LO 0x026d 655 #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 656 #define mmSDMA0_RLC3_IB_BASE_HI 0x026e 657 #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 658 #define mmSDMA0_RLC3_IB_SIZE 0x026f 659 #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 660 #define mmSDMA0_RLC3_SKIP_CNTL 0x0270 661 #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 662 #define mmSDMA0_RLC3_CONTEXT_STATUS 0x0271 663 #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 664 #define mmSDMA0_RLC3_DOORBELL 0x0272 665 #define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 666 #define mmSDMA0_RLC3_STATUS 0x0288 667 #define mmSDMA0_RLC3_STATUS_BASE_IDX 0 668 #define mmSDMA0_RLC3_DOORBELL_LOG 0x0289 669 #define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 670 #define mmSDMA0_RLC3_WATERMARK 0x028a 671 #define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 672 #define mmSDMA0_RLC3_DOORBELL_OFFSET 0x028b 673 #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 674 #define mmSDMA0_RLC3_CSA_ADDR_LO 0x028c 675 #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 676 #define mmSDMA0_RLC3_CSA_ADDR_HI 0x028d 677 #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 678 #define mmSDMA0_RLC3_IB_SUB_REMAIN 0x028f 679 #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 680 #define mmSDMA0_RLC3_PREEMPT 0x0290 681 #define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 682 #define mmSDMA0_RLC3_DUMMY_REG 0x0291 683 #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 684 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 685 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 686 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 687 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 688 #define mmSDMA0_RLC3_RB_AQL_CNTL 0x0294 689 #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 690 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x0295 691 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 692 #define mmSDMA0_RLC3_MIDCMD_DATA0 0x02a0 693 #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 694 #define mmSDMA0_RLC3_MIDCMD_DATA1 0x02a1 695 #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 696 #define mmSDMA0_RLC3_MIDCMD_DATA2 0x02a2 697 #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 698 #define mmSDMA0_RLC3_MIDCMD_DATA3 0x02a3 699 #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 700 #define mmSDMA0_RLC3_MIDCMD_DATA4 0x02a4 701 #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 702 #define mmSDMA0_RLC3_MIDCMD_DATA5 0x02a5 703 #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 704 #define mmSDMA0_RLC3_MIDCMD_DATA6 0x02a6 705 #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 706 #define mmSDMA0_RLC3_MIDCMD_DATA7 0x02a7 707 #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 708 #define mmSDMA0_RLC3_MIDCMD_DATA8 0x02a8 709 #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 710 #define mmSDMA0_RLC3_MIDCMD_CNTL 0x02a9 711 #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 712 #define mmSDMA0_RLC4_RB_CNTL 0x02c0 713 #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 714 #define mmSDMA0_RLC4_RB_BASE 0x02c1 715 #define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 716 #define mmSDMA0_RLC4_RB_BASE_HI 0x02c2 717 #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 718 #define mmSDMA0_RLC4_RB_RPTR 0x02c3 719 #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 720 #define mmSDMA0_RLC4_RB_RPTR_HI 0x02c4 721 #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 722 #define mmSDMA0_RLC4_RB_WPTR 0x02c5 723 #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 724 #define mmSDMA0_RLC4_RB_WPTR_HI 0x02c6 725 #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 726 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 727 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 728 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x02c8 729 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 730 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x02c9 731 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 732 #define mmSDMA0_RLC4_IB_CNTL 0x02ca 733 #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 734 #define mmSDMA0_RLC4_IB_RPTR 0x02cb 735 #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 736 #define mmSDMA0_RLC4_IB_OFFSET 0x02cc 737 #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 738 #define mmSDMA0_RLC4_IB_BASE_LO 0x02cd 739 #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 740 #define mmSDMA0_RLC4_IB_BASE_HI 0x02ce 741 #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 742 #define mmSDMA0_RLC4_IB_SIZE 0x02cf 743 #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 744 #define mmSDMA0_RLC4_SKIP_CNTL 0x02d0 745 #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 746 #define mmSDMA0_RLC4_CONTEXT_STATUS 0x02d1 747 #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 748 #define mmSDMA0_RLC4_DOORBELL 0x02d2 749 #define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 750 #define mmSDMA0_RLC4_STATUS 0x02e8 751 #define mmSDMA0_RLC4_STATUS_BASE_IDX 0 752 #define mmSDMA0_RLC4_DOORBELL_LOG 0x02e9 753 #define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 754 #define mmSDMA0_RLC4_WATERMARK 0x02ea 755 #define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 756 #define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02eb 757 #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 758 #define mmSDMA0_RLC4_CSA_ADDR_LO 0x02ec 759 #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 760 #define mmSDMA0_RLC4_CSA_ADDR_HI 0x02ed 761 #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 762 #define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02ef 763 #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 764 #define mmSDMA0_RLC4_PREEMPT 0x02f0 765 #define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 766 #define mmSDMA0_RLC4_DUMMY_REG 0x02f1 767 #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 768 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 769 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 770 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 771 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 772 #define mmSDMA0_RLC4_RB_AQL_CNTL 0x02f4 773 #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 774 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02f5 775 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 776 #define mmSDMA0_RLC4_MIDCMD_DATA0 0x0300 777 #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 778 #define mmSDMA0_RLC4_MIDCMD_DATA1 0x0301 779 #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 780 #define mmSDMA0_RLC4_MIDCMD_DATA2 0x0302 781 #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 782 #define mmSDMA0_RLC4_MIDCMD_DATA3 0x0303 783 #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 784 #define mmSDMA0_RLC4_MIDCMD_DATA4 0x0304 785 #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 786 #define mmSDMA0_RLC4_MIDCMD_DATA5 0x0305 787 #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 788 #define mmSDMA0_RLC4_MIDCMD_DATA6 0x0306 789 #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 790 #define mmSDMA0_RLC4_MIDCMD_DATA7 0x0307 791 #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 792 #define mmSDMA0_RLC4_MIDCMD_DATA8 0x0308 793 #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 794 #define mmSDMA0_RLC4_MIDCMD_CNTL 0x0309 795 #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 796 #define mmSDMA0_RLC5_RB_CNTL 0x0320 797 #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 798 #define mmSDMA0_RLC5_RB_BASE 0x0321 799 #define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 800 #define mmSDMA0_RLC5_RB_BASE_HI 0x0322 801 #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 802 #define mmSDMA0_RLC5_RB_RPTR 0x0323 803 #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 804 #define mmSDMA0_RLC5_RB_RPTR_HI 0x0324 805 #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 806 #define mmSDMA0_RLC5_RB_WPTR 0x0325 807 #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 808 #define mmSDMA0_RLC5_RB_WPTR_HI 0x0326 809 #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 810 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327 811 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 812 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x0328 813 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 814 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x0329 815 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 816 #define mmSDMA0_RLC5_IB_CNTL 0x032a 817 #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 818 #define mmSDMA0_RLC5_IB_RPTR 0x032b 819 #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 820 #define mmSDMA0_RLC5_IB_OFFSET 0x032c 821 #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 822 #define mmSDMA0_RLC5_IB_BASE_LO 0x032d 823 #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 824 #define mmSDMA0_RLC5_IB_BASE_HI 0x032e 825 #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 826 #define mmSDMA0_RLC5_IB_SIZE 0x032f 827 #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 828 #define mmSDMA0_RLC5_SKIP_CNTL 0x0330 829 #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 830 #define mmSDMA0_RLC5_CONTEXT_STATUS 0x0331 831 #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 832 #define mmSDMA0_RLC5_DOORBELL 0x0332 833 #define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 834 #define mmSDMA0_RLC5_STATUS 0x0348 835 #define mmSDMA0_RLC5_STATUS_BASE_IDX 0 836 #define mmSDMA0_RLC5_DOORBELL_LOG 0x0349 837 #define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 838 #define mmSDMA0_RLC5_WATERMARK 0x034a 839 #define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 840 #define mmSDMA0_RLC5_DOORBELL_OFFSET 0x034b 841 #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 842 #define mmSDMA0_RLC5_CSA_ADDR_LO 0x034c 843 #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 844 #define mmSDMA0_RLC5_CSA_ADDR_HI 0x034d 845 #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 846 #define mmSDMA0_RLC5_IB_SUB_REMAIN 0x034f 847 #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 848 #define mmSDMA0_RLC5_PREEMPT 0x0350 849 #define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 850 #define mmSDMA0_RLC5_DUMMY_REG 0x0351 851 #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 852 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 853 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 854 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 855 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 856 #define mmSDMA0_RLC5_RB_AQL_CNTL 0x0354 857 #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 858 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x0355 859 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 860 #define mmSDMA0_RLC5_MIDCMD_DATA0 0x0360 861 #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 862 #define mmSDMA0_RLC5_MIDCMD_DATA1 0x0361 863 #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 864 #define mmSDMA0_RLC5_MIDCMD_DATA2 0x0362 865 #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 866 #define mmSDMA0_RLC5_MIDCMD_DATA3 0x0363 867 #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 868 #define mmSDMA0_RLC5_MIDCMD_DATA4 0x0364 869 #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 870 #define mmSDMA0_RLC5_MIDCMD_DATA5 0x0365 871 #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 872 #define mmSDMA0_RLC5_MIDCMD_DATA6 0x0366 873 #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 874 #define mmSDMA0_RLC5_MIDCMD_DATA7 0x0367 875 #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 876 #define mmSDMA0_RLC5_MIDCMD_DATA8 0x0368 877 #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 878 #define mmSDMA0_RLC5_MIDCMD_CNTL 0x0369 879 #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 880 #define mmSDMA0_RLC6_RB_CNTL 0x0380 881 #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 882 #define mmSDMA0_RLC6_RB_BASE 0x0381 883 #define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 884 #define mmSDMA0_RLC6_RB_BASE_HI 0x0382 885 #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 886 #define mmSDMA0_RLC6_RB_RPTR 0x0383 887 #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 888 #define mmSDMA0_RLC6_RB_RPTR_HI 0x0384 889 #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 890 #define mmSDMA0_RLC6_RB_WPTR 0x0385 891 #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 892 #define mmSDMA0_RLC6_RB_WPTR_HI 0x0386 893 #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 894 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0387 895 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 896 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0388 897 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 898 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0389 899 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 900 #define mmSDMA0_RLC6_IB_CNTL 0x038a 901 #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 902 #define mmSDMA0_RLC6_IB_RPTR 0x038b 903 #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 904 #define mmSDMA0_RLC6_IB_OFFSET 0x038c 905 #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 906 #define mmSDMA0_RLC6_IB_BASE_LO 0x038d 907 #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 908 #define mmSDMA0_RLC6_IB_BASE_HI 0x038e 909 #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 910 #define mmSDMA0_RLC6_IB_SIZE 0x038f 911 #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 912 #define mmSDMA0_RLC6_SKIP_CNTL 0x0390 913 #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 914 #define mmSDMA0_RLC6_CONTEXT_STATUS 0x0391 915 #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 916 #define mmSDMA0_RLC6_DOORBELL 0x0392 917 #define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 918 #define mmSDMA0_RLC6_STATUS 0x03a8 919 #define mmSDMA0_RLC6_STATUS_BASE_IDX 0 920 #define mmSDMA0_RLC6_DOORBELL_LOG 0x03a9 921 #define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 922 #define mmSDMA0_RLC6_WATERMARK 0x03aa 923 #define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 924 #define mmSDMA0_RLC6_DOORBELL_OFFSET 0x03ab 925 #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 926 #define mmSDMA0_RLC6_CSA_ADDR_LO 0x03ac 927 #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 928 #define mmSDMA0_RLC6_CSA_ADDR_HI 0x03ad 929 #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 930 #define mmSDMA0_RLC6_IB_SUB_REMAIN 0x03af 931 #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 932 #define mmSDMA0_RLC6_PREEMPT 0x03b0 933 #define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 934 #define mmSDMA0_RLC6_DUMMY_REG 0x03b1 935 #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 936 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 937 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 938 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 939 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 940 #define mmSDMA0_RLC6_RB_AQL_CNTL 0x03b4 941 #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 942 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x03b5 943 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 944 #define mmSDMA0_RLC6_MIDCMD_DATA0 0x03c0 945 #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 946 #define mmSDMA0_RLC6_MIDCMD_DATA1 0x03c1 947 #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 948 #define mmSDMA0_RLC6_MIDCMD_DATA2 0x03c2 949 #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 950 #define mmSDMA0_RLC6_MIDCMD_DATA3 0x03c3 951 #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 952 #define mmSDMA0_RLC6_MIDCMD_DATA4 0x03c4 953 #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 954 #define mmSDMA0_RLC6_MIDCMD_DATA5 0x03c5 955 #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 956 #define mmSDMA0_RLC6_MIDCMD_DATA6 0x03c6 957 #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 958 #define mmSDMA0_RLC6_MIDCMD_DATA7 0x03c7 959 #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 960 #define mmSDMA0_RLC6_MIDCMD_DATA8 0x03c8 961 #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 962 #define mmSDMA0_RLC6_MIDCMD_CNTL 0x03c9 963 #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 964 #define mmSDMA0_RLC7_RB_CNTL 0x03e0 965 #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 966 #define mmSDMA0_RLC7_RB_BASE 0x03e1 967 #define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 968 #define mmSDMA0_RLC7_RB_BASE_HI 0x03e2 969 #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 970 #define mmSDMA0_RLC7_RB_RPTR 0x03e3 971 #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 972 #define mmSDMA0_RLC7_RB_RPTR_HI 0x03e4 973 #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 974 #define mmSDMA0_RLC7_RB_WPTR 0x03e5 975 #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 976 #define mmSDMA0_RLC7_RB_WPTR_HI 0x03e6 977 #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 978 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x03e7 979 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 980 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03e8 981 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 982 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03e9 983 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 984 #define mmSDMA0_RLC7_IB_CNTL 0x03ea 985 #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 986 #define mmSDMA0_RLC7_IB_RPTR 0x03eb 987 #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 988 #define mmSDMA0_RLC7_IB_OFFSET 0x03ec 989 #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 990 #define mmSDMA0_RLC7_IB_BASE_LO 0x03ed 991 #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 992 #define mmSDMA0_RLC7_IB_BASE_HI 0x03ee 993 #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 994 #define mmSDMA0_RLC7_IB_SIZE 0x03ef 995 #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 996 #define mmSDMA0_RLC7_SKIP_CNTL 0x03f0 997 #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 998 #define mmSDMA0_RLC7_CONTEXT_STATUS 0x03f1 999 #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 1000 #define mmSDMA0_RLC7_DOORBELL 0x03f2 1001 #define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 1002 #define mmSDMA0_RLC7_STATUS 0x0408 1003 #define mmSDMA0_RLC7_STATUS_BASE_IDX 0 1004 #define mmSDMA0_RLC7_DOORBELL_LOG 0x0409 1005 #define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 1006 #define mmSDMA0_RLC7_WATERMARK 0x040a 1007 #define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 1008 #define mmSDMA0_RLC7_DOORBELL_OFFSET 0x040b 1009 #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 1010 #define mmSDMA0_RLC7_CSA_ADDR_LO 0x040c 1011 #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 1012 #define mmSDMA0_RLC7_CSA_ADDR_HI 0x040d 1013 #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 1014 #define mmSDMA0_RLC7_IB_SUB_REMAIN 0x040f 1015 #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 1016 #define mmSDMA0_RLC7_PREEMPT 0x0410 1017 #define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 1018 #define mmSDMA0_RLC7_DUMMY_REG 0x0411 1019 #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 1020 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 1021 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1022 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 1023 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1024 #define mmSDMA0_RLC7_RB_AQL_CNTL 0x0414 1025 #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 1026 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x0415 1027 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 1028 #define mmSDMA0_RLC7_MIDCMD_DATA0 0x0420 1029 #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 1030 #define mmSDMA0_RLC7_MIDCMD_DATA1 0x0421 1031 #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 1032 #define mmSDMA0_RLC7_MIDCMD_DATA2 0x0422 1033 #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 1034 #define mmSDMA0_RLC7_MIDCMD_DATA3 0x0423 1035 #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 1036 #define mmSDMA0_RLC7_MIDCMD_DATA4 0x0424 1037 #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 1038 #define mmSDMA0_RLC7_MIDCMD_DATA5 0x0425 1039 #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 1040 #define mmSDMA0_RLC7_MIDCMD_DATA6 0x0426 1041 #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 1042 #define mmSDMA0_RLC7_MIDCMD_DATA7 0x0427 1043 #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 1044 #define mmSDMA0_RLC7_MIDCMD_DATA8 0x0428 1045 #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 1046 #define mmSDMA0_RLC7_MIDCMD_CNTL 0x0429 1047 #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 1048 1049 #endif 1050