1 /* $NetBSD: sdma0_4_2_2_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _sdma0_4_2_2_SH_MASK_HEADER 24 #define _sdma0_4_2_2_SH_MASK_HEADER 25 26 27 // addressBlock: sdma0_sdma0dec 28 //SDMA0_UCODE_ADDR 29 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 //SDMA0_UCODE_DATA 32 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA0_VM_CNTL 35 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 36 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 37 //SDMA0_VM_CTX_LO 38 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 39 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 40 //SDMA0_VM_CTX_HI 41 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 42 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 43 //SDMA0_ACTIVE_FCN_ID 44 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 45 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 46 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 47 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 48 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 49 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 50 //SDMA0_VM_CTX_CNTL 51 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 52 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 53 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 54 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 55 //SDMA0_VIRT_RESET_REQ 56 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 57 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 58 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 59 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 60 //SDMA0_VF_ENABLE 61 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 62 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 63 //SDMA0_CONTEXT_REG_TYPE0 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 102 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 103 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 104 //SDMA0_CONTEXT_REG_TYPE1 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 109 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 111 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 117 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 119 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 124 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 126 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 132 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 133 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 134 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 135 //SDMA0_CONTEXT_REG_TYPE2 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 144 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 146 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 155 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 156 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 157 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 158 //SDMA0_CONTEXT_REG_TYPE3 159 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 160 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 161 //SDMA0_PUB_REG_TYPE0 162 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 164 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 169 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 171 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 179 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 181 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 189 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 191 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 196 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 198 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 206 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 208 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 214 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 215 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216 //SDMA0_PUB_REG_TYPE1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 229 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 230 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 231 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 261 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 279 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 280 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 281 //SDMA0_PUB_REG_TYPE2 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 308 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 309 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 310 #define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c 311 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 313 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 339 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 340 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 341 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 342 #define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L 343 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 344 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 345 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 346 //SDMA0_PUB_REG_TYPE3 347 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 348 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 349 #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 350 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 351 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 352 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 353 #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 354 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L 355 //SDMA0_MMHUB_CNTL 356 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 357 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 358 //SDMA0_CONTEXT_GROUP_BOUNDARY 359 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 360 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 361 //SDMA0_POWER_CNTL 362 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 363 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 364 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 365 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 366 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 367 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 368 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 369 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 370 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 371 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 372 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 373 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 374 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 375 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 376 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 377 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 378 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 379 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 380 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 381 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 382 //SDMA0_CLK_CTRL 383 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 384 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 385 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 386 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 387 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 388 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 390 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 392 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 393 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 394 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 395 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 396 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 397 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 398 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 399 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 400 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 401 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 402 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 403 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 404 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 405 //SDMA0_CNTL 406 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 407 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 408 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 409 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 410 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 411 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 412 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 413 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 414 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 415 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 416 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 417 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 418 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 419 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 420 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 421 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 422 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 423 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 424 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 425 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 426 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 427 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 428 //SDMA0_CHICKEN_BITS 429 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 430 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 431 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 432 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 433 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 434 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 435 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 436 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 437 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 438 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 439 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 440 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 441 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 442 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 443 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 444 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 445 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 446 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 447 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 448 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 449 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 450 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 451 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 452 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 453 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 454 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 455 //SDMA0_GB_ADDR_CONFIG 456 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 457 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 458 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 459 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 460 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 461 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 462 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 463 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 464 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 465 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 466 //SDMA0_GB_ADDR_CONFIG_READ 467 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 468 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 469 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 470 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 471 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 472 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 473 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 474 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 475 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 476 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 477 //SDMA0_RB_RPTR_FETCH_HI 478 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 479 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 480 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 481 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 482 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 483 //SDMA0_RB_RPTR_FETCH 484 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 485 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 486 //SDMA0_IB_OFFSET_FETCH 487 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 488 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 489 //SDMA0_PROGRAM 490 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 491 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 492 //SDMA0_STATUS_REG 493 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 494 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 495 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 496 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 497 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 498 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 499 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 500 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 501 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 502 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 503 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 504 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 505 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 506 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 507 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 508 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 509 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 510 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 511 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 512 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 513 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 514 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 515 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 516 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 517 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 518 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 519 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 520 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 521 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 522 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 523 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 524 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 525 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 526 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 527 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 528 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 529 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 530 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 531 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 532 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 533 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 534 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 535 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 536 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 537 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 538 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 539 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 540 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 541 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 542 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 543 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 544 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 545 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 546 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 547 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 548 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 549 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 550 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 551 //SDMA0_STATUS1_REG 552 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 553 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 554 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 555 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 556 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 557 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 558 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 559 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 560 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 561 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 562 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 563 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 564 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 565 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 566 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 567 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 568 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 569 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 570 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 571 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 572 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 573 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 574 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 575 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 576 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 577 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 578 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 579 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 580 //SDMA0_RD_BURST_CNTL 581 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 582 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 583 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 584 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 585 //SDMA0_HBM_PAGE_CONFIG 586 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 587 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 588 //SDMA0_UCODE_CHECKSUM 589 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 590 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 591 //SDMA0_F32_CNTL 592 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 593 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 594 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 595 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 596 //SDMA0_FREEZE 597 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 598 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 599 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 600 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 601 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 602 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 603 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 604 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 605 //SDMA0_PHASE0_QUANTUM 606 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 607 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 608 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 609 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 610 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 611 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 612 //SDMA0_PHASE1_QUANTUM 613 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 614 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 615 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 616 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 617 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 618 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 619 //SDMA_POWER_GATING 620 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 621 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 622 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 623 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 624 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 625 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 626 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 627 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 628 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 629 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 630 //SDMA_PGFSM_CONFIG 631 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 632 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 633 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 634 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 635 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 636 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 637 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 638 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 639 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 640 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 641 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 642 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 643 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 644 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 645 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 646 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 647 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 648 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 649 //SDMA_PGFSM_WRITE 650 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 651 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 652 //SDMA_PGFSM_READ 653 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 654 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 655 //SDMA0_EDC_CONFIG 656 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 657 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 658 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 659 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 660 //SDMA0_BA_THRESHOLD 661 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 662 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 663 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 664 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 665 //SDMA0_ID 666 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 667 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 668 //SDMA0_VERSION 669 #define SDMA0_VERSION__MINVER__SHIFT 0x0 670 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 671 #define SDMA0_VERSION__REV__SHIFT 0x10 672 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 673 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 674 #define SDMA0_VERSION__REV_MASK 0x003F0000L 675 //SDMA0_EDC_COUNTER 676 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 677 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 678 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 679 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 680 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 681 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 682 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 683 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 684 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 685 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 686 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 687 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 688 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 689 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 690 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 691 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 692 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 693 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 694 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 695 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 696 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 697 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 698 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 699 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 700 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 701 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 702 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 703 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 704 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 705 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 706 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 707 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 708 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 709 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 710 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 711 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 712 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 713 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 714 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 715 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 716 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 717 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 718 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 719 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 720 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 721 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 722 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 723 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 724 //SDMA0_EDC_COUNTER_CLEAR 725 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 726 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 727 //SDMA0_STATUS2_REG 728 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 729 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 730 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 731 #define SDMA0_STATUS2_REG__ID_MASK 0x00000007L 732 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 733 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 734 //SDMA0_ATOMIC_CNTL 735 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 736 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 737 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 738 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 739 //SDMA0_ATOMIC_PREOP_LO 740 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 741 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 742 //SDMA0_ATOMIC_PREOP_HI 743 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 744 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 745 //SDMA0_UTCL1_CNTL 746 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 747 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 748 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 749 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 750 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 751 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 752 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 753 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 754 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 755 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 756 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 757 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 758 //SDMA0_UTCL1_WATERMK 759 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 760 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 761 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 762 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 763 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 764 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 765 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 766 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 767 //SDMA0_UTCL1_RD_STATUS 768 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 769 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 770 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 771 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 772 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 773 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 774 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 775 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 776 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 777 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 778 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 779 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 780 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 781 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 782 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 783 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 784 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 785 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 786 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 787 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 788 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 789 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 790 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 791 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 792 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 793 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 794 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 795 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 796 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 797 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 798 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 799 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 800 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 801 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 802 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 803 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 804 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 805 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 806 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 807 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 808 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 809 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 810 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 811 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 812 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 813 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 814 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 815 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 816 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 817 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 818 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 819 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 820 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 821 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 822 //SDMA0_UTCL1_WR_STATUS 823 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 824 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 825 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 826 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 827 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 828 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 829 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 830 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 831 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 832 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 833 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 834 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 835 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 836 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 837 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 838 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 839 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 840 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 841 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 842 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 843 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 844 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 845 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 846 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 847 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 848 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 849 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 850 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 851 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 852 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 853 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 854 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 855 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 856 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 857 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 858 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 859 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 860 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 861 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 862 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 863 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 864 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 865 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 866 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 867 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 868 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 869 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 870 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 871 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 872 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 873 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 874 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 875 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 876 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 877 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 878 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 879 //SDMA0_UTCL1_INV0 880 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 881 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 882 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 883 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 884 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 885 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 886 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 887 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 888 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 889 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 890 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 891 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 892 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 893 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 894 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 895 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 896 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 897 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 898 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 899 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 900 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 901 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 902 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 903 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 904 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 905 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 906 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 907 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 908 //SDMA0_UTCL1_INV1 909 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 910 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 911 //SDMA0_UTCL1_INV2 912 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 913 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 914 //SDMA0_UTCL1_RD_XNACK0 915 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 916 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 917 //SDMA0_UTCL1_RD_XNACK1 918 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 919 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 920 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 921 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 922 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 923 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 924 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 925 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 926 //SDMA0_UTCL1_WR_XNACK0 927 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 928 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 929 //SDMA0_UTCL1_WR_XNACK1 930 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 931 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 932 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 933 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 934 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 935 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 936 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 937 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 938 //SDMA0_UTCL1_TIMEOUT 939 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 940 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 941 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 942 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 943 //SDMA0_UTCL1_PAGE 944 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 945 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 946 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 947 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 948 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 949 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 950 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 951 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 952 //SDMA0_POWER_CNTL_IDLE 953 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 954 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 955 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 956 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 957 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 958 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 959 //SDMA0_RELAX_ORDERING_LUT 960 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 961 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 962 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 963 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 964 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 965 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 966 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 967 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 968 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 969 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 970 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 971 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 972 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 973 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 974 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 975 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 976 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 977 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 978 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 979 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 980 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 981 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 982 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 983 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 984 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 985 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 986 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 987 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 988 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 989 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 990 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 991 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 992 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 993 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 994 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 995 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 996 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 997 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 998 //SDMA0_CHICKEN_BITS_2 999 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 1000 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 1001 //SDMA0_STATUS3_REG 1002 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 1003 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 1004 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 1005 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 1006 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 1007 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1008 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1009 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1010 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1011 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1012 //SDMA0_PHYSICAL_ADDR_LO 1013 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1014 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1015 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1016 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1017 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1018 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1019 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1020 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1021 //SDMA0_PHYSICAL_ADDR_HI 1022 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1023 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1024 //SDMA0_PHASE2_QUANTUM 1025 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1026 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1027 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1028 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1029 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1030 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1031 //SDMA0_ERROR_LOG 1032 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1033 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1034 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1035 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1036 //SDMA0_PUB_DUMMY_REG0 1037 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1038 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1039 //SDMA0_PUB_DUMMY_REG1 1040 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1041 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1042 //SDMA0_PUB_DUMMY_REG2 1043 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1044 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1045 //SDMA0_PUB_DUMMY_REG3 1046 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1047 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1048 //SDMA0_F32_COUNTER 1049 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1050 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1051 //SDMA0_UNBREAKABLE 1052 #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1053 #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1054 //SDMA0_PERFMON_CNTL 1055 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1056 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1057 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1058 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1059 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1060 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1061 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1062 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1063 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1064 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1065 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1066 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1067 //SDMA0_PERFCOUNTER0_RESULT 1068 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1069 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1070 //SDMA0_PERFCOUNTER1_RESULT 1071 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1072 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1073 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1074 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1075 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1076 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1077 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1078 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1079 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1080 //SDMA0_CRD_CNTL 1081 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1082 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1083 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1084 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1085 //SDMA0_GPU_IOV_VIOLATION_LOG 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1089 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 1090 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 1091 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 1092 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1093 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1094 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 1095 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 1096 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 1097 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 1098 //SDMA0_ULV_CNTL 1099 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1100 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1101 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1102 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1103 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1104 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1105 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1106 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1107 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1108 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1109 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1110 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1111 //SDMA0_EA_DBIT_ADDR_DATA 1112 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1113 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1114 //SDMA0_EA_DBIT_ADDR_INDEX 1115 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1116 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1117 //SDMA0_GPU_IOV_VIOLATION_LOG2 1118 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 1119 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL 1120 //SDMA0_GFX_RB_CNTL 1121 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1122 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1123 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1124 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1125 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1126 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1127 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1128 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1129 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1130 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1131 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1132 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1133 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1134 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1135 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1136 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1137 //SDMA0_GFX_RB_BASE 1138 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1139 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1140 //SDMA0_GFX_RB_BASE_HI 1141 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1142 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1143 //SDMA0_GFX_RB_RPTR 1144 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1145 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1146 //SDMA0_GFX_RB_RPTR_HI 1147 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1148 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1149 //SDMA0_GFX_RB_WPTR 1150 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1151 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1152 //SDMA0_GFX_RB_WPTR_HI 1153 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1154 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1155 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1156 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1157 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1158 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1159 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1160 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1161 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1162 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1163 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1164 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1165 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1166 //SDMA0_GFX_RB_RPTR_ADDR_HI 1167 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1168 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1169 //SDMA0_GFX_RB_RPTR_ADDR_LO 1170 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1171 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1172 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1173 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1174 //SDMA0_GFX_IB_CNTL 1175 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1176 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1177 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1178 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1179 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1180 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1181 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1182 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1183 //SDMA0_GFX_IB_RPTR 1184 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1185 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1186 //SDMA0_GFX_IB_OFFSET 1187 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1188 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1189 //SDMA0_GFX_IB_BASE_LO 1190 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1191 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1192 //SDMA0_GFX_IB_BASE_HI 1193 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1194 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1195 //SDMA0_GFX_IB_SIZE 1196 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1197 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1198 //SDMA0_GFX_SKIP_CNTL 1199 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1200 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1201 //SDMA0_GFX_CONTEXT_STATUS 1202 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1203 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1204 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1205 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1206 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1207 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1208 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1209 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1210 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1211 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1212 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1213 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1214 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1215 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1216 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1217 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1218 //SDMA0_GFX_DOORBELL 1219 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1220 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1221 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1222 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1223 //SDMA0_GFX_CONTEXT_CNTL 1224 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1225 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1226 //SDMA0_GFX_STATUS 1227 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1228 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1229 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1230 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1231 //SDMA0_GFX_DOORBELL_LOG 1232 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1233 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1234 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1235 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1236 //SDMA0_GFX_WATERMARK 1237 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1238 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1239 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1240 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1241 //SDMA0_GFX_DOORBELL_OFFSET 1242 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1243 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1244 //SDMA0_GFX_CSA_ADDR_LO 1245 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1246 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1247 //SDMA0_GFX_CSA_ADDR_HI 1248 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1249 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1250 //SDMA0_GFX_IB_SUB_REMAIN 1251 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1252 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1253 //SDMA0_GFX_PREEMPT 1254 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1255 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1256 //SDMA0_GFX_DUMMY_REG 1257 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1258 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1259 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1260 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1261 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1262 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1263 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1264 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1265 //SDMA0_GFX_RB_AQL_CNTL 1266 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1267 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1268 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1269 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1270 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1271 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1272 //SDMA0_GFX_MINOR_PTR_UPDATE 1273 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1274 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1275 //SDMA0_GFX_MIDCMD_DATA0 1276 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1277 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1278 //SDMA0_GFX_MIDCMD_DATA1 1279 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1280 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1281 //SDMA0_GFX_MIDCMD_DATA2 1282 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1283 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1284 //SDMA0_GFX_MIDCMD_DATA3 1285 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1286 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1287 //SDMA0_GFX_MIDCMD_DATA4 1288 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1289 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1290 //SDMA0_GFX_MIDCMD_DATA5 1291 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1292 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1293 //SDMA0_GFX_MIDCMD_DATA6 1294 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1295 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1296 //SDMA0_GFX_MIDCMD_DATA7 1297 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1298 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1299 //SDMA0_GFX_MIDCMD_DATA8 1300 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1301 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1302 //SDMA0_GFX_MIDCMD_CNTL 1303 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1304 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1305 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1306 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1307 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1308 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1309 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1310 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1311 //SDMA0_PAGE_RB_CNTL 1312 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1313 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1314 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1315 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1316 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1317 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1318 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1319 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1320 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1321 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1322 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1323 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1324 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1325 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1326 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1327 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1328 //SDMA0_PAGE_RB_BASE 1329 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1330 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1331 //SDMA0_PAGE_RB_BASE_HI 1332 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1333 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1334 //SDMA0_PAGE_RB_RPTR 1335 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1336 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1337 //SDMA0_PAGE_RB_RPTR_HI 1338 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1339 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1340 //SDMA0_PAGE_RB_WPTR 1341 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1342 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1343 //SDMA0_PAGE_RB_WPTR_HI 1344 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1345 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1346 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1347 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1348 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1349 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1350 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1351 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1352 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1353 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1354 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1355 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1356 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1357 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1358 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1359 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1360 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1361 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1362 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1363 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1364 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1365 //SDMA0_PAGE_IB_CNTL 1366 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1367 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1368 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1369 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1370 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1371 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1372 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1373 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1374 //SDMA0_PAGE_IB_RPTR 1375 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1376 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1377 //SDMA0_PAGE_IB_OFFSET 1378 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1379 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1380 //SDMA0_PAGE_IB_BASE_LO 1381 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1382 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1383 //SDMA0_PAGE_IB_BASE_HI 1384 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1385 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1386 //SDMA0_PAGE_IB_SIZE 1387 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1388 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1389 //SDMA0_PAGE_SKIP_CNTL 1390 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1391 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1392 //SDMA0_PAGE_CONTEXT_STATUS 1393 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1394 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1395 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1396 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1397 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1398 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1399 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1400 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1401 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1402 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1403 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1404 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1405 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1406 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1407 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1408 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1409 //SDMA0_PAGE_DOORBELL 1410 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1411 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1412 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1413 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1414 //SDMA0_PAGE_STATUS 1415 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1416 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1417 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1418 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1419 //SDMA0_PAGE_DOORBELL_LOG 1420 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1421 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1422 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1423 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1424 //SDMA0_PAGE_WATERMARK 1425 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1426 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1427 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1428 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1429 //SDMA0_PAGE_DOORBELL_OFFSET 1430 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1431 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1432 //SDMA0_PAGE_CSA_ADDR_LO 1433 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1434 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1435 //SDMA0_PAGE_CSA_ADDR_HI 1436 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1437 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1438 //SDMA0_PAGE_IB_SUB_REMAIN 1439 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1440 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1441 //SDMA0_PAGE_PREEMPT 1442 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1443 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1444 //SDMA0_PAGE_DUMMY_REG 1445 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1446 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1447 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1448 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1449 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1450 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1451 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1452 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1453 //SDMA0_PAGE_RB_AQL_CNTL 1454 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1455 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1456 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1457 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1458 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1459 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1460 //SDMA0_PAGE_MINOR_PTR_UPDATE 1461 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1462 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1463 //SDMA0_PAGE_MIDCMD_DATA0 1464 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1465 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1466 //SDMA0_PAGE_MIDCMD_DATA1 1467 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1468 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1469 //SDMA0_PAGE_MIDCMD_DATA2 1470 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1471 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1472 //SDMA0_PAGE_MIDCMD_DATA3 1473 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1474 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1475 //SDMA0_PAGE_MIDCMD_DATA4 1476 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1477 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1478 //SDMA0_PAGE_MIDCMD_DATA5 1479 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1480 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1481 //SDMA0_PAGE_MIDCMD_DATA6 1482 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1483 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1484 //SDMA0_PAGE_MIDCMD_DATA7 1485 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1486 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1487 //SDMA0_PAGE_MIDCMD_DATA8 1488 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1489 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1490 //SDMA0_PAGE_MIDCMD_CNTL 1491 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1492 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1493 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1494 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1495 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1496 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1497 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1498 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1499 //SDMA0_RLC0_RB_CNTL 1500 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1501 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1502 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1503 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1504 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1505 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1506 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1507 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1508 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1509 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1510 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1511 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1512 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1513 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1514 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1515 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1516 //SDMA0_RLC0_RB_BASE 1517 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1518 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1519 //SDMA0_RLC0_RB_BASE_HI 1520 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1521 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1522 //SDMA0_RLC0_RB_RPTR 1523 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1524 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1525 //SDMA0_RLC0_RB_RPTR_HI 1526 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1527 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1528 //SDMA0_RLC0_RB_WPTR 1529 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1530 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1531 //SDMA0_RLC0_RB_WPTR_HI 1532 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1533 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1534 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1535 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1536 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1537 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1538 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1539 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1540 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1541 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1542 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1543 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1544 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1545 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1546 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1547 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1548 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1549 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1550 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1551 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1552 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1553 //SDMA0_RLC0_IB_CNTL 1554 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1555 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1556 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1557 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1558 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1559 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1560 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1561 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1562 //SDMA0_RLC0_IB_RPTR 1563 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1564 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1565 //SDMA0_RLC0_IB_OFFSET 1566 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1567 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1568 //SDMA0_RLC0_IB_BASE_LO 1569 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1570 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1571 //SDMA0_RLC0_IB_BASE_HI 1572 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1573 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1574 //SDMA0_RLC0_IB_SIZE 1575 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1576 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1577 //SDMA0_RLC0_SKIP_CNTL 1578 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1579 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1580 //SDMA0_RLC0_CONTEXT_STATUS 1581 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1582 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1583 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1584 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1585 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1586 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1587 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1588 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1589 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1590 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1591 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1592 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1593 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1594 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1595 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1596 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1597 //SDMA0_RLC0_DOORBELL 1598 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1599 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1600 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1601 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1602 //SDMA0_RLC0_STATUS 1603 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1604 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1605 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1606 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1607 //SDMA0_RLC0_DOORBELL_LOG 1608 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1609 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1610 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1611 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1612 //SDMA0_RLC0_WATERMARK 1613 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1614 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1615 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1616 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1617 //SDMA0_RLC0_DOORBELL_OFFSET 1618 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1619 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1620 //SDMA0_RLC0_CSA_ADDR_LO 1621 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1622 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1623 //SDMA0_RLC0_CSA_ADDR_HI 1624 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1625 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1626 //SDMA0_RLC0_IB_SUB_REMAIN 1627 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1628 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1629 //SDMA0_RLC0_PREEMPT 1630 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1631 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1632 //SDMA0_RLC0_DUMMY_REG 1633 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1634 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1635 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1636 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1637 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1638 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1639 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1640 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1641 //SDMA0_RLC0_RB_AQL_CNTL 1642 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1643 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1644 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1645 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1646 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1647 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1648 //SDMA0_RLC0_MINOR_PTR_UPDATE 1649 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1650 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1651 //SDMA0_RLC0_MIDCMD_DATA0 1652 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1653 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1654 //SDMA0_RLC0_MIDCMD_DATA1 1655 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1656 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1657 //SDMA0_RLC0_MIDCMD_DATA2 1658 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1659 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1660 //SDMA0_RLC0_MIDCMD_DATA3 1661 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1662 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1663 //SDMA0_RLC0_MIDCMD_DATA4 1664 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1665 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1666 //SDMA0_RLC0_MIDCMD_DATA5 1667 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1668 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1669 //SDMA0_RLC0_MIDCMD_DATA6 1670 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1671 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1672 //SDMA0_RLC0_MIDCMD_DATA7 1673 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1674 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1675 //SDMA0_RLC0_MIDCMD_DATA8 1676 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1677 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1678 //SDMA0_RLC0_MIDCMD_CNTL 1679 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1680 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1681 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1682 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1683 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1684 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1685 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1686 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1687 //SDMA0_RLC1_RB_CNTL 1688 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1689 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1690 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1691 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1692 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1693 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1694 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1695 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1696 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1697 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1698 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1699 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1700 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1701 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1702 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1703 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1704 //SDMA0_RLC1_RB_BASE 1705 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1706 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1707 //SDMA0_RLC1_RB_BASE_HI 1708 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1709 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1710 //SDMA0_RLC1_RB_RPTR 1711 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1712 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1713 //SDMA0_RLC1_RB_RPTR_HI 1714 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1715 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1716 //SDMA0_RLC1_RB_WPTR 1717 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1718 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1719 //SDMA0_RLC1_RB_WPTR_HI 1720 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1721 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1722 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1723 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1724 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1725 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1726 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1727 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1728 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1729 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1730 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1731 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1732 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1733 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1734 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1735 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1736 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1737 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1738 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1739 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1740 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1741 //SDMA0_RLC1_IB_CNTL 1742 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1743 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1744 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1745 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1746 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1747 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1748 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1749 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1750 //SDMA0_RLC1_IB_RPTR 1751 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1752 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1753 //SDMA0_RLC1_IB_OFFSET 1754 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1755 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1756 //SDMA0_RLC1_IB_BASE_LO 1757 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1758 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1759 //SDMA0_RLC1_IB_BASE_HI 1760 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1761 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1762 //SDMA0_RLC1_IB_SIZE 1763 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1764 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1765 //SDMA0_RLC1_SKIP_CNTL 1766 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1767 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1768 //SDMA0_RLC1_CONTEXT_STATUS 1769 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1770 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1771 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1772 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1773 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1774 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1775 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1776 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1777 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1778 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1779 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1780 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1781 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1782 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1783 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1784 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1785 //SDMA0_RLC1_DOORBELL 1786 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1787 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1788 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1789 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1790 //SDMA0_RLC1_STATUS 1791 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1792 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1793 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1794 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1795 //SDMA0_RLC1_DOORBELL_LOG 1796 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1797 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1798 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1799 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1800 //SDMA0_RLC1_WATERMARK 1801 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1802 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1803 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1804 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1805 //SDMA0_RLC1_DOORBELL_OFFSET 1806 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1807 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1808 //SDMA0_RLC1_CSA_ADDR_LO 1809 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1810 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1811 //SDMA0_RLC1_CSA_ADDR_HI 1812 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1813 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1814 //SDMA0_RLC1_IB_SUB_REMAIN 1815 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1816 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1817 //SDMA0_RLC1_PREEMPT 1818 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1819 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1820 //SDMA0_RLC1_DUMMY_REG 1821 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1822 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1823 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1824 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1825 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1826 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1827 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1828 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1829 //SDMA0_RLC1_RB_AQL_CNTL 1830 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1831 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1832 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1833 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1834 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1835 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1836 //SDMA0_RLC1_MINOR_PTR_UPDATE 1837 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1838 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1839 //SDMA0_RLC1_MIDCMD_DATA0 1840 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1841 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1842 //SDMA0_RLC1_MIDCMD_DATA1 1843 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1844 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1845 //SDMA0_RLC1_MIDCMD_DATA2 1846 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1847 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1848 //SDMA0_RLC1_MIDCMD_DATA3 1849 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1850 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1851 //SDMA0_RLC1_MIDCMD_DATA4 1852 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1853 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1854 //SDMA0_RLC1_MIDCMD_DATA5 1855 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1856 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1857 //SDMA0_RLC1_MIDCMD_DATA6 1858 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1859 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1860 //SDMA0_RLC1_MIDCMD_DATA7 1861 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1862 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1863 //SDMA0_RLC1_MIDCMD_DATA8 1864 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1865 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1866 //SDMA0_RLC1_MIDCMD_CNTL 1867 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1868 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1869 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1870 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1871 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1872 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1873 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1874 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1875 //SDMA0_RLC2_RB_CNTL 1876 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1877 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1878 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1879 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1880 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1881 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1882 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1883 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1884 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1885 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1886 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1887 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1888 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1889 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1890 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1891 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1892 //SDMA0_RLC2_RB_BASE 1893 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1894 #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1895 //SDMA0_RLC2_RB_BASE_HI 1896 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1897 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1898 //SDMA0_RLC2_RB_RPTR 1899 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1900 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1901 //SDMA0_RLC2_RB_RPTR_HI 1902 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1903 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1904 //SDMA0_RLC2_RB_WPTR 1905 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1906 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1907 //SDMA0_RLC2_RB_WPTR_HI 1908 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1909 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1910 //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1911 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1912 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1913 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1914 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1915 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1916 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1917 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1918 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1919 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1920 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1921 //SDMA0_RLC2_RB_RPTR_ADDR_HI 1922 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1923 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1924 //SDMA0_RLC2_RB_RPTR_ADDR_LO 1925 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1926 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1927 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1928 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1929 //SDMA0_RLC2_IB_CNTL 1930 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1931 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1932 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1933 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1934 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1935 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1936 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1937 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1938 //SDMA0_RLC2_IB_RPTR 1939 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1940 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1941 //SDMA0_RLC2_IB_OFFSET 1942 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1943 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1944 //SDMA0_RLC2_IB_BASE_LO 1945 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1946 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1947 //SDMA0_RLC2_IB_BASE_HI 1948 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1949 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1950 //SDMA0_RLC2_IB_SIZE 1951 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1952 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1953 //SDMA0_RLC2_SKIP_CNTL 1954 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1955 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1956 //SDMA0_RLC2_CONTEXT_STATUS 1957 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1958 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1959 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1960 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1961 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1962 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1963 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1964 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1965 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1966 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1967 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1968 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1969 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1970 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1971 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1972 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1973 //SDMA0_RLC2_DOORBELL 1974 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1975 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1976 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1977 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1978 //SDMA0_RLC2_STATUS 1979 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1980 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1981 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1982 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1983 //SDMA0_RLC2_DOORBELL_LOG 1984 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1985 #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1986 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1987 #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1988 //SDMA0_RLC2_WATERMARK 1989 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1990 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1991 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1992 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1993 //SDMA0_RLC2_DOORBELL_OFFSET 1994 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1995 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1996 //SDMA0_RLC2_CSA_ADDR_LO 1997 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1998 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1999 //SDMA0_RLC2_CSA_ADDR_HI 2000 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 2001 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2002 //SDMA0_RLC2_IB_SUB_REMAIN 2003 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2004 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2005 //SDMA0_RLC2_PREEMPT 2006 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 2007 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2008 //SDMA0_RLC2_DUMMY_REG 2009 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 2010 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2011 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2012 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2013 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2014 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2015 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2016 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2017 //SDMA0_RLC2_RB_AQL_CNTL 2018 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2019 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2020 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2021 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2022 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2023 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2024 //SDMA0_RLC2_MINOR_PTR_UPDATE 2025 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2026 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2027 //SDMA0_RLC2_MIDCMD_DATA0 2028 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2029 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2030 //SDMA0_RLC2_MIDCMD_DATA1 2031 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2032 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2033 //SDMA0_RLC2_MIDCMD_DATA2 2034 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2035 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2036 //SDMA0_RLC2_MIDCMD_DATA3 2037 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2038 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2039 //SDMA0_RLC2_MIDCMD_DATA4 2040 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2041 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2042 //SDMA0_RLC2_MIDCMD_DATA5 2043 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2044 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2045 //SDMA0_RLC2_MIDCMD_DATA6 2046 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2047 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2048 //SDMA0_RLC2_MIDCMD_DATA7 2049 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2050 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2051 //SDMA0_RLC2_MIDCMD_DATA8 2052 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2053 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2054 //SDMA0_RLC2_MIDCMD_CNTL 2055 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2056 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2057 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2058 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2059 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2060 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2061 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2062 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2063 //SDMA0_RLC3_RB_CNTL 2064 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2065 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2066 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2067 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2068 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2069 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2070 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2071 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2072 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2073 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2074 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2075 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2076 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2077 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2078 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2079 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2080 //SDMA0_RLC3_RB_BASE 2081 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2082 #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2083 //SDMA0_RLC3_RB_BASE_HI 2084 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2085 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2086 //SDMA0_RLC3_RB_RPTR 2087 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2088 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2089 //SDMA0_RLC3_RB_RPTR_HI 2090 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2091 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2092 //SDMA0_RLC3_RB_WPTR 2093 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2094 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2095 //SDMA0_RLC3_RB_WPTR_HI 2096 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2097 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2098 //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2099 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2100 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2101 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2102 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2103 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2104 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2105 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2106 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2107 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2108 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2109 //SDMA0_RLC3_RB_RPTR_ADDR_HI 2110 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2111 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2112 //SDMA0_RLC3_RB_RPTR_ADDR_LO 2113 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2114 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2115 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2116 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2117 //SDMA0_RLC3_IB_CNTL 2118 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2119 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2120 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2121 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2122 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2123 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2124 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2125 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2126 //SDMA0_RLC3_IB_RPTR 2127 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2128 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2129 //SDMA0_RLC3_IB_OFFSET 2130 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2131 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2132 //SDMA0_RLC3_IB_BASE_LO 2133 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2134 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2135 //SDMA0_RLC3_IB_BASE_HI 2136 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2137 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2138 //SDMA0_RLC3_IB_SIZE 2139 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2140 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2141 //SDMA0_RLC3_SKIP_CNTL 2142 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2143 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2144 //SDMA0_RLC3_CONTEXT_STATUS 2145 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2146 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2147 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2148 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2149 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2150 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2151 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2152 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2153 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2154 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2155 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2156 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2157 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2158 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2159 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2160 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2161 //SDMA0_RLC3_DOORBELL 2162 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2163 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2164 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2165 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2166 //SDMA0_RLC3_STATUS 2167 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2168 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2169 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2170 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2171 //SDMA0_RLC3_DOORBELL_LOG 2172 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2173 #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2174 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2175 #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2176 //SDMA0_RLC3_WATERMARK 2177 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2178 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2179 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2180 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2181 //SDMA0_RLC3_DOORBELL_OFFSET 2182 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2183 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2184 //SDMA0_RLC3_CSA_ADDR_LO 2185 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2186 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2187 //SDMA0_RLC3_CSA_ADDR_HI 2188 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2189 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2190 //SDMA0_RLC3_IB_SUB_REMAIN 2191 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2192 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2193 //SDMA0_RLC3_PREEMPT 2194 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2195 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2196 //SDMA0_RLC3_DUMMY_REG 2197 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2198 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2199 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2200 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2201 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2202 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2203 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2204 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2205 //SDMA0_RLC3_RB_AQL_CNTL 2206 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2207 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2208 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2209 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2210 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2211 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2212 //SDMA0_RLC3_MINOR_PTR_UPDATE 2213 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2214 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2215 //SDMA0_RLC3_MIDCMD_DATA0 2216 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2217 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2218 //SDMA0_RLC3_MIDCMD_DATA1 2219 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2220 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2221 //SDMA0_RLC3_MIDCMD_DATA2 2222 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2223 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2224 //SDMA0_RLC3_MIDCMD_DATA3 2225 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2226 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2227 //SDMA0_RLC3_MIDCMD_DATA4 2228 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2229 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2230 //SDMA0_RLC3_MIDCMD_DATA5 2231 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2232 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2233 //SDMA0_RLC3_MIDCMD_DATA6 2234 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2235 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2236 //SDMA0_RLC3_MIDCMD_DATA7 2237 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2238 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2239 //SDMA0_RLC3_MIDCMD_DATA8 2240 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2241 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2242 //SDMA0_RLC3_MIDCMD_CNTL 2243 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2244 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2245 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2246 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2247 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2248 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2249 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2250 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2251 //SDMA0_RLC4_RB_CNTL 2252 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2253 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2254 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2255 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2256 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2257 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2258 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2259 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2260 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2261 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2262 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2263 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2264 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2265 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2266 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2267 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2268 //SDMA0_RLC4_RB_BASE 2269 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2270 #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2271 //SDMA0_RLC4_RB_BASE_HI 2272 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2273 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2274 //SDMA0_RLC4_RB_RPTR 2275 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2276 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2277 //SDMA0_RLC4_RB_RPTR_HI 2278 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2279 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2280 //SDMA0_RLC4_RB_WPTR 2281 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2282 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2283 //SDMA0_RLC4_RB_WPTR_HI 2284 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2285 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2286 //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2287 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2288 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2289 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2290 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2291 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2292 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2293 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2294 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2295 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2296 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2297 //SDMA0_RLC4_RB_RPTR_ADDR_HI 2298 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2299 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2300 //SDMA0_RLC4_RB_RPTR_ADDR_LO 2301 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2302 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2303 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2304 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2305 //SDMA0_RLC4_IB_CNTL 2306 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2307 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2308 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2309 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2310 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2311 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2312 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2313 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2314 //SDMA0_RLC4_IB_RPTR 2315 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2316 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2317 //SDMA0_RLC4_IB_OFFSET 2318 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2319 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2320 //SDMA0_RLC4_IB_BASE_LO 2321 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2322 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2323 //SDMA0_RLC4_IB_BASE_HI 2324 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2325 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2326 //SDMA0_RLC4_IB_SIZE 2327 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2328 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2329 //SDMA0_RLC4_SKIP_CNTL 2330 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2331 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2332 //SDMA0_RLC4_CONTEXT_STATUS 2333 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2334 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2335 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2336 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2337 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2338 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2339 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2340 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2341 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2342 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2343 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2344 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2345 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2346 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2347 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2348 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2349 //SDMA0_RLC4_DOORBELL 2350 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2351 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2352 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2353 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2354 //SDMA0_RLC4_STATUS 2355 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2356 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2357 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2358 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2359 //SDMA0_RLC4_DOORBELL_LOG 2360 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2361 #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2362 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2363 #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2364 //SDMA0_RLC4_WATERMARK 2365 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2366 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2367 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2368 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2369 //SDMA0_RLC4_DOORBELL_OFFSET 2370 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2371 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2372 //SDMA0_RLC4_CSA_ADDR_LO 2373 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2374 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2375 //SDMA0_RLC4_CSA_ADDR_HI 2376 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2377 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2378 //SDMA0_RLC4_IB_SUB_REMAIN 2379 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2380 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2381 //SDMA0_RLC4_PREEMPT 2382 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2383 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2384 //SDMA0_RLC4_DUMMY_REG 2385 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2386 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2387 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2388 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2389 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2390 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2391 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2392 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2393 //SDMA0_RLC4_RB_AQL_CNTL 2394 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2395 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2396 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2397 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2398 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2399 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2400 //SDMA0_RLC4_MINOR_PTR_UPDATE 2401 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2402 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2403 //SDMA0_RLC4_MIDCMD_DATA0 2404 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2405 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2406 //SDMA0_RLC4_MIDCMD_DATA1 2407 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2408 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2409 //SDMA0_RLC4_MIDCMD_DATA2 2410 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2411 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2412 //SDMA0_RLC4_MIDCMD_DATA3 2413 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2414 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2415 //SDMA0_RLC4_MIDCMD_DATA4 2416 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2417 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2418 //SDMA0_RLC4_MIDCMD_DATA5 2419 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2420 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2421 //SDMA0_RLC4_MIDCMD_DATA6 2422 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2423 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2424 //SDMA0_RLC4_MIDCMD_DATA7 2425 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2426 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2427 //SDMA0_RLC4_MIDCMD_DATA8 2428 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2429 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2430 //SDMA0_RLC4_MIDCMD_CNTL 2431 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2432 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2433 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2434 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2435 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2436 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2437 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2438 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2439 //SDMA0_RLC5_RB_CNTL 2440 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2441 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2442 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2443 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2444 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2445 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2446 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2447 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2448 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2449 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2450 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2451 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2452 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2453 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2454 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2455 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2456 //SDMA0_RLC5_RB_BASE 2457 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2458 #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2459 //SDMA0_RLC5_RB_BASE_HI 2460 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2461 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2462 //SDMA0_RLC5_RB_RPTR 2463 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2464 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2465 //SDMA0_RLC5_RB_RPTR_HI 2466 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2467 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2468 //SDMA0_RLC5_RB_WPTR 2469 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2470 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2471 //SDMA0_RLC5_RB_WPTR_HI 2472 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2473 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2474 //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2475 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2476 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2477 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2478 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2479 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2480 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2481 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2482 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2483 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2484 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2485 //SDMA0_RLC5_RB_RPTR_ADDR_HI 2486 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2487 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2488 //SDMA0_RLC5_RB_RPTR_ADDR_LO 2489 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2490 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2491 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2492 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2493 //SDMA0_RLC5_IB_CNTL 2494 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2495 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2496 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2497 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2498 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2499 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2500 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2501 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2502 //SDMA0_RLC5_IB_RPTR 2503 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2504 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2505 //SDMA0_RLC5_IB_OFFSET 2506 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2507 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2508 //SDMA0_RLC5_IB_BASE_LO 2509 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2510 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2511 //SDMA0_RLC5_IB_BASE_HI 2512 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2513 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2514 //SDMA0_RLC5_IB_SIZE 2515 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2516 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2517 //SDMA0_RLC5_SKIP_CNTL 2518 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2519 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2520 //SDMA0_RLC5_CONTEXT_STATUS 2521 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2522 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2523 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2524 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2525 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2526 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2527 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2528 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2529 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2530 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2531 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2532 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2533 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2534 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2535 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2536 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2537 //SDMA0_RLC5_DOORBELL 2538 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2539 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2540 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2541 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2542 //SDMA0_RLC5_STATUS 2543 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2544 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2545 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2546 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2547 //SDMA0_RLC5_DOORBELL_LOG 2548 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2549 #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2550 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2551 #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2552 //SDMA0_RLC5_WATERMARK 2553 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2554 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2555 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2556 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2557 //SDMA0_RLC5_DOORBELL_OFFSET 2558 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2559 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2560 //SDMA0_RLC5_CSA_ADDR_LO 2561 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2562 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2563 //SDMA0_RLC5_CSA_ADDR_HI 2564 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2565 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2566 //SDMA0_RLC5_IB_SUB_REMAIN 2567 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2568 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2569 //SDMA0_RLC5_PREEMPT 2570 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2571 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2572 //SDMA0_RLC5_DUMMY_REG 2573 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2574 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2575 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2576 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2577 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2578 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2579 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2580 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2581 //SDMA0_RLC5_RB_AQL_CNTL 2582 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2583 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2584 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2585 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2586 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2587 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2588 //SDMA0_RLC5_MINOR_PTR_UPDATE 2589 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2590 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2591 //SDMA0_RLC5_MIDCMD_DATA0 2592 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2593 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2594 //SDMA0_RLC5_MIDCMD_DATA1 2595 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2596 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2597 //SDMA0_RLC5_MIDCMD_DATA2 2598 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2599 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2600 //SDMA0_RLC5_MIDCMD_DATA3 2601 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2602 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2603 //SDMA0_RLC5_MIDCMD_DATA4 2604 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2605 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2606 //SDMA0_RLC5_MIDCMD_DATA5 2607 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2608 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2609 //SDMA0_RLC5_MIDCMD_DATA6 2610 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2611 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2612 //SDMA0_RLC5_MIDCMD_DATA7 2613 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2614 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2615 //SDMA0_RLC5_MIDCMD_DATA8 2616 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2617 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2618 //SDMA0_RLC5_MIDCMD_CNTL 2619 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2620 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2621 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2622 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2623 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2624 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2625 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2626 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2627 //SDMA0_RLC6_RB_CNTL 2628 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2629 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2630 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2631 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2632 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2633 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2634 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2635 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2636 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2637 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2638 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2639 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2640 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2641 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2642 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2643 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2644 //SDMA0_RLC6_RB_BASE 2645 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2646 #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2647 //SDMA0_RLC6_RB_BASE_HI 2648 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2649 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2650 //SDMA0_RLC6_RB_RPTR 2651 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2652 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2653 //SDMA0_RLC6_RB_RPTR_HI 2654 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2655 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2656 //SDMA0_RLC6_RB_WPTR 2657 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2658 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2659 //SDMA0_RLC6_RB_WPTR_HI 2660 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2661 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2662 //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2663 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2664 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2665 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2666 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2667 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2668 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2669 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2670 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2671 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2672 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2673 //SDMA0_RLC6_RB_RPTR_ADDR_HI 2674 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2675 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2676 //SDMA0_RLC6_RB_RPTR_ADDR_LO 2677 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2678 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2679 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2680 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2681 //SDMA0_RLC6_IB_CNTL 2682 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2683 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2684 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2685 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2686 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2687 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2688 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2689 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2690 //SDMA0_RLC6_IB_RPTR 2691 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2692 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2693 //SDMA0_RLC6_IB_OFFSET 2694 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2695 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2696 //SDMA0_RLC6_IB_BASE_LO 2697 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2698 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2699 //SDMA0_RLC6_IB_BASE_HI 2700 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2701 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2702 //SDMA0_RLC6_IB_SIZE 2703 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2704 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2705 //SDMA0_RLC6_SKIP_CNTL 2706 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2707 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2708 //SDMA0_RLC6_CONTEXT_STATUS 2709 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2710 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2711 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2712 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2713 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2714 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2715 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2716 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2717 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2718 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2719 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2720 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2721 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2722 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2723 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2724 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2725 //SDMA0_RLC6_DOORBELL 2726 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2727 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2728 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2729 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2730 //SDMA0_RLC6_STATUS 2731 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2732 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2733 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2734 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2735 //SDMA0_RLC6_DOORBELL_LOG 2736 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2737 #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2738 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2739 #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2740 //SDMA0_RLC6_WATERMARK 2741 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2742 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2743 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2744 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2745 //SDMA0_RLC6_DOORBELL_OFFSET 2746 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2747 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2748 //SDMA0_RLC6_CSA_ADDR_LO 2749 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2750 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2751 //SDMA0_RLC6_CSA_ADDR_HI 2752 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2753 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2754 //SDMA0_RLC6_IB_SUB_REMAIN 2755 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2756 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2757 //SDMA0_RLC6_PREEMPT 2758 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2759 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2760 //SDMA0_RLC6_DUMMY_REG 2761 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2762 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2763 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2764 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2765 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2766 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2767 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2768 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2769 //SDMA0_RLC6_RB_AQL_CNTL 2770 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2771 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2772 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2773 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2774 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2775 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2776 //SDMA0_RLC6_MINOR_PTR_UPDATE 2777 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2778 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2779 //SDMA0_RLC6_MIDCMD_DATA0 2780 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2781 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2782 //SDMA0_RLC6_MIDCMD_DATA1 2783 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2784 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2785 //SDMA0_RLC6_MIDCMD_DATA2 2786 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2787 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2788 //SDMA0_RLC6_MIDCMD_DATA3 2789 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2790 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2791 //SDMA0_RLC6_MIDCMD_DATA4 2792 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2793 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2794 //SDMA0_RLC6_MIDCMD_DATA5 2795 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2796 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2797 //SDMA0_RLC6_MIDCMD_DATA6 2798 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2799 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2800 //SDMA0_RLC6_MIDCMD_DATA7 2801 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2802 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2803 //SDMA0_RLC6_MIDCMD_DATA8 2804 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2805 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2806 //SDMA0_RLC6_MIDCMD_CNTL 2807 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2808 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2809 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2810 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2811 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2812 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2813 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2814 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2815 //SDMA0_RLC7_RB_CNTL 2816 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2817 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2818 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2819 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2820 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2821 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2822 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2823 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2824 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2825 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2826 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2827 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2828 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2829 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2830 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2831 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2832 //SDMA0_RLC7_RB_BASE 2833 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2834 #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2835 //SDMA0_RLC7_RB_BASE_HI 2836 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2837 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2838 //SDMA0_RLC7_RB_RPTR 2839 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2840 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2841 //SDMA0_RLC7_RB_RPTR_HI 2842 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2843 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2844 //SDMA0_RLC7_RB_WPTR 2845 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2846 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2847 //SDMA0_RLC7_RB_WPTR_HI 2848 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2849 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2850 //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2851 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2852 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2853 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2854 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2855 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2856 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2857 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2858 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2859 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2860 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2861 //SDMA0_RLC7_RB_RPTR_ADDR_HI 2862 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2863 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2864 //SDMA0_RLC7_RB_RPTR_ADDR_LO 2865 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2866 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2867 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2868 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2869 //SDMA0_RLC7_IB_CNTL 2870 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2871 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2872 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2873 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2874 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2875 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2876 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2877 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2878 //SDMA0_RLC7_IB_RPTR 2879 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2880 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2881 //SDMA0_RLC7_IB_OFFSET 2882 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2883 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2884 //SDMA0_RLC7_IB_BASE_LO 2885 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2886 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2887 //SDMA0_RLC7_IB_BASE_HI 2888 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2889 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2890 //SDMA0_RLC7_IB_SIZE 2891 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2892 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2893 //SDMA0_RLC7_SKIP_CNTL 2894 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2895 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2896 //SDMA0_RLC7_CONTEXT_STATUS 2897 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2898 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2899 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2900 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2901 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2902 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2903 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2904 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2905 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2906 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2907 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2908 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2909 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2910 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2911 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2912 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2913 //SDMA0_RLC7_DOORBELL 2914 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2915 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2916 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2917 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2918 //SDMA0_RLC7_STATUS 2919 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2920 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2921 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2922 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2923 //SDMA0_RLC7_DOORBELL_LOG 2924 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2925 #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2926 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2927 #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2928 //SDMA0_RLC7_WATERMARK 2929 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2930 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2931 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2932 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2933 //SDMA0_RLC7_DOORBELL_OFFSET 2934 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2935 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2936 //SDMA0_RLC7_CSA_ADDR_LO 2937 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2938 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2939 //SDMA0_RLC7_CSA_ADDR_HI 2940 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2941 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2942 //SDMA0_RLC7_IB_SUB_REMAIN 2943 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2944 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2945 //SDMA0_RLC7_PREEMPT 2946 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2947 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2948 //SDMA0_RLC7_DUMMY_REG 2949 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2950 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2951 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2952 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2953 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2954 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2955 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2956 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2957 //SDMA0_RLC7_RB_AQL_CNTL 2958 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2959 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2960 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2961 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2962 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2963 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2964 //SDMA0_RLC7_MINOR_PTR_UPDATE 2965 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2966 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2967 //SDMA0_RLC7_MIDCMD_DATA0 2968 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2969 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2970 //SDMA0_RLC7_MIDCMD_DATA1 2971 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2972 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2973 //SDMA0_RLC7_MIDCMD_DATA2 2974 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2975 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2976 //SDMA0_RLC7_MIDCMD_DATA3 2977 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2978 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2979 //SDMA0_RLC7_MIDCMD_DATA4 2980 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2981 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2982 //SDMA0_RLC7_MIDCMD_DATA5 2983 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2984 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2985 //SDMA0_RLC7_MIDCMD_DATA6 2986 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2987 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2988 //SDMA0_RLC7_MIDCMD_DATA7 2989 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2990 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2991 //SDMA0_RLC7_MIDCMD_DATA8 2992 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2993 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2994 //SDMA0_RLC7_MIDCMD_CNTL 2995 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2996 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2997 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2998 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2999 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 3000 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 3001 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 3002 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 3003 3004 #endif 3005