1 /* $NetBSD: schide.c,v 1.8 2013/10/07 19:51:55 jakllsch Exp $ */
2 /* $OpenBSD: pciide.c,v 1.305 2009/11/01 01:50:15 dlg Exp $ */
3
4 /*
5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29 /*
30 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 * 3. All advertising materials mentioning features or use of this software
41 * must display the following acknowledgement:
42 * This product includes software developed by Christopher G. Demetriou
43 * for the NetBSD Project.
44 * 4. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <sys/cdefs.h>
60 __KERNEL_RCSID(0, "$NetBSD: schide.c,v 1.8 2013/10/07 19:51:55 jakllsch Exp $");
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64
65 #include <dev/pci/pcivar.h>
66 #include <dev/pci/pcidevs.h>
67 #include <dev/pci/pciidereg.h>
68 #include <dev/pci/pciidevar.h>
69 #include <dev/pci/pciide_sch_reg.h>
70
71 static void sch_chip_map(struct pciide_softc*, const struct pci_attach_args*);
72 static void sch_setup_channel(struct ata_channel*);
73 static int schide_match(device_t, cfdata_t, void *);
74 static void schide_attach(device_t, device_t, void *);
75
76 CFATTACH_DECL_NEW(schide, sizeof(struct pciide_softc),
77 schide_match, schide_attach, pciide_detach, NULL);
78
79 static const struct pciide_product_desc pciide_sch_products[] = {
80 { PCI_PRODUCT_INTEL_SCH_IDE,
81 0,
82 "Intel SCH IDE Controller",
83 sch_chip_map,
84 },
85 { 0,
86 0,
87 NULL,
88 NULL
89 }
90 };
91
92 static int
schide_match(device_t parent,cfdata_t match,void * aux)93 schide_match(device_t parent, cfdata_t match, void *aux)
94 {
95 struct pci_attach_args *pa = aux;
96
97 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
98 if (pciide_lookup_product(pa->pa_id, pciide_sch_products))
99 return (2);
100 }
101 return (0);
102 }
103
104 static void
schide_attach(device_t parent,device_t self,void * aux)105 schide_attach(device_t parent, device_t self, void *aux)
106 {
107 struct pci_attach_args *pa = aux;
108 struct pciide_softc *sc = device_private(self);
109
110 sc->sc_wdcdev.sc_atac.atac_dev = self;
111
112 pciide_common_attach(sc, pa,
113 pciide_lookup_product(pa->pa_id, pciide_sch_products));
114
115 }
116
117 static void
sch_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)118 sch_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
119 {
120 struct pciide_channel *cp;
121 pcireg_t interface;
122 int channel;
123
124 if (pciide_chipen(sc, pa) == 0)
125 return;
126
127 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
128 "bus-master DMA support present");
129 pciide_mapreg_dma(sc, pa);
130 aprint_verbose("\n");
131 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
132
133 if (sc->sc_dma_ok) {
134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
135 sc->sc_wdcdev.irqack = pciide_irqack;
136 }
137 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
138 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = sch_setup_channel;
141 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
142 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
143 sc->sc_wdcdev.wdc_maxdrives = 2;
144
145
146 ATADEBUG_PRINT(("sch_setup_chip: old d0tim=0x%x, d1tim=0x%x\n",
147 pci_conf_read(sc->sc_pc, sc->sc_tag, SCH_D0TIM),
148 pci_conf_read(sc->sc_pc, sc->sc_tag, SCH_D1TIM)),
149 DEBUG_PROBE);
150
151 interface = PCI_INTERFACE(pa->pa_class);
152
153 wdc_allocate_regs(&sc->sc_wdcdev);
154
155 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
156 channel++) {
157 cp = &sc->pciide_channels[channel];
158 if (pciide_chansetup(sc, channel, interface) == 0)
159 continue;
160 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
161 }
162
163 ATADEBUG_PRINT(("sch_setup_chip: d0tim=0x%x, d1tim=0x%x\n",
164 pci_conf_read(sc->sc_pc, sc->sc_tag, SCH_D0TIM),
165 pci_conf_read(sc->sc_pc, sc->sc_tag, SCH_D1TIM)),
166 DEBUG_PROBE);
167 }
168
169 static void
sch_setup_channel(struct ata_channel * chp)170 sch_setup_channel(struct ata_channel *chp)
171 {
172 struct ata_drive_datas *drvp;
173 u_int32_t tim, timaddr, idedma_ctl;
174 struct atac_softc *atac = chp->ch_atac;
175 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
176 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
177 int drive, s;
178
179 idedma_ctl = 0;
180
181 /* setup DMA if needed */
182 pciide_channel_dma_setup(cp);
183
184 /* Per drive settings */
185 for (drive = 0; drive < 2; drive++) {
186 drvp = &chp->ch_drive[drive];
187 /* If no drive, skip */
188 if (drvp->drive_type == ATA_DRIVET_NONE)
189 continue;
190
191 timaddr = (drive == 0) ? SCH_D0TIM : SCH_D1TIM;
192 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, timaddr);
193 tim &= ~SCH_TIM_MASK;
194
195 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
196 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0))
197 goto pio;
198
199 /* add timing values, setup DMA if needed */
200 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
201 (drvp->drive_flags & ATA_DRIVE_UDMA)) {
202 /* use Ultra/DMA */
203 tim |= (drvp->UDMA_mode << 16) | SCH_TIM_SYNCDMA;
204 } else {
205 /* use Multiword DMA */
206 s = splbio();
207 drvp->drive_flags &= ~ATA_DRIVE_UDMA;
208 splx(s);
209 tim &= ~SCH_TIM_SYNCDMA;
210 }
211 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
212
213 pio: /* use PIO mode */
214
215 tim |= (drvp->DMA_mode << 8) | (drvp->PIO_mode);
216 pci_conf_write(sc->sc_pc, sc->sc_tag, timaddr, tim);
217 }
218 if (idedma_ctl != 0) {
219 /* Add software bits in status register */
220 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
221 idedma_ctl);
222 }
223 }
224