1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation. 3 * Copyright 2013-2014 6WIND S.A. 4 */ 5 6 #ifndef _RTE_PCI_H_ 7 #define _RTE_PCI_H_ 8 9 /** 10 * @file 11 * 12 * RTE PCI Library 13 */ 14 15 #include <stdio.h> 16 #include <inttypes.h> 17 #include <sys/types.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /* 24 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of 25 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of 26 * configuration space. 27 */ 28 #define RTE_PCI_CFG_SPACE_SIZE 256 29 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 30 31 #define RTE_PCI_STD_HEADER_SIZEOF 64 32 33 /* Standard register offsets in the PCI configuration space */ 34 #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ 35 #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ 36 #define RTE_PCI_COMMAND 0x04 /* 16 bits */ 37 #define RTE_PCI_STATUS 0x06 /* 16 bits */ 38 #define RTE_PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 39 #define RTE_PCI_CAPABILITY_LIST 0x34 /* 32 bits */ 40 41 /* PCI Command Register (RTE_PCI_COMMAND) */ 42 #define RTE_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 43 #define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ 44 #define RTE_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 45 46 /* PCI Status Register (RTE_PCI_STATUS) */ 47 #define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 48 49 /* Base addresses (RTE_PCI_BASE_ADDRESS_*) */ 50 #define RTE_PCI_BASE_ADDRESS_SPACE_IO 0x01 51 52 /* Capability registers (RTE_PCI_CAPABILITY_LIST) */ 53 #define RTE_PCI_CAP_ID_PM 0x01 /* Power Management */ 54 #define RTE_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 55 #define RTE_PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 56 #define RTE_PCI_CAP_ID_EXP 0x10 /* PCI Express */ 57 #define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 58 #define RTE_PCI_CAP_SIZEOF 4 59 #define RTE_PCI_CAP_NEXT 1 60 61 /* Power Management Registers (RTE_PCI_CAP_ID_PM) */ 62 #define RTE_PCI_PM_CTRL 4 /* PM control and status register */ 63 #define RTE_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 64 #define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 65 #define RTE_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 66 67 /* PCI Express capability registers (RTE_PCI_CAP_ID_EXP) */ 68 #define RTE_PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 69 #define RTE_PCI_EXP_DEVCTL 0x08 /* Device Control */ 70 #define RTE_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 71 #define RTE_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 72 #define RTE_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 73 #define RTE_PCI_EXP_DEVSTA 0x0a /* Device Status */ 74 #define RTE_PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ 75 #define RTE_PCI_EXP_LNKCTL 0x10 /* Link Control */ 76 #define RTE_PCI_EXP_LNKSTA 0x12 /* Link Status */ 77 #define RTE_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 78 #define RTE_PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 79 #define RTE_PCI_EXP_SLTCTL 0x18 /* Slot Control */ 80 #define RTE_PCI_EXP_RTCTL 0x1c /* Root Control */ 81 #define RTE_PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */ 82 #define RTE_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ 83 #define RTE_PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */ 84 85 /* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */ 86 #define RTE_PCI_MSIX_FLAGS 2 /* Message Control */ 87 #define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */ 88 #define RTE_PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 89 #define RTE_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ 90 91 #define RTE_PCI_MSIX_TABLE 4 /* Table offset */ 92 #define RTE_PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ 93 #define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ 94 95 /* Extended Capabilities (PCI-X 2.0 and Express) */ 96 #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 97 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 98 99 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 100 #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 101 #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ 102 #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ 103 #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 104 #define RTE_PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID */ 105 106 /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ 107 #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ 108 #define RTE_PCI_ERR_COR_STATUS 0x10 /* Correctable Error Status */ 109 #define RTE_PCI_ERR_ROOT_STATUS 0x30 110 111 /* Access Control Service (RTE_PCI_EXT_CAP_ID_ACS) */ 112 #define RTE_PCI_ACS_CAP 0x04 /* ACS Capability Register */ 113 #define RTE_PCI_ACS_CTRL 0x06 /* ACS Control Register */ 114 #define RTE_PCI_ACS_SV 0x0001 /* Source Validation */ 115 #define RTE_PCI_ACS_RR 0x0004 /* P2P Request Redirect */ 116 #define RTE_PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ 117 #define RTE_PCI_ACS_UF 0x0010 /* Upstream Forwarding */ 118 #define RTE_PCI_ACS_EC 0x0020 /* P2P Egress Control */ 119 120 /* Single Root I/O Virtualization (RTE_PCI_EXT_CAP_ID_SRIOV) */ 121 #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 122 #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 123 #define RTE_PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 124 #define RTE_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 125 #define RTE_PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 126 #define RTE_PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 127 #define RTE_PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 128 #define RTE_PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 129 #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 130 #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 131 132 /* Page Request Interface (RTE_PCI_EXT_CAP_ID_PRI) */ 133 #define RTE_PCI_PRI_CTRL 0x04 /* PRI control register */ 134 #define RTE_PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ 135 #define RTE_PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 136 137 /* Process Address Space ID (RTE_PCI_EXT_CAP_ID_PASID) */ 138 #define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ 139 140 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ 141 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 142 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X") 143 144 /** Short formatting string, without domain, for PCI device: Ex: 00:01.0 */ 145 #define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 146 147 /** Nb. of values in PCI device identifier format string. */ 148 #define PCI_FMT_NVAL 4 149 150 /** Nb. of values in PCI resource format. */ 151 #define PCI_RESOURCE_FMT_NVAL 3 152 153 /** Maximum number of PCI resources. */ 154 #define PCI_MAX_RESOURCE 6 155 156 /** 157 * A structure describing an ID for a PCI driver. Each driver provides a 158 * table of these IDs for each device that it supports. 159 */ 160 struct rte_pci_id { 161 uint32_t class_id; /**< Class ID or RTE_CLASS_ANY_ID. */ 162 uint16_t vendor_id; /**< Vendor ID or RTE_PCI_ANY_ID. */ 163 uint16_t device_id; /**< Device ID or RTE_PCI_ANY_ID. */ 164 uint16_t subsystem_vendor_id; /**< Subsystem vendor ID or RTE_PCI_ANY_ID. */ 165 uint16_t subsystem_device_id; /**< Subsystem device ID or RTE_PCI_ANY_ID. */ 166 }; 167 168 /** 169 * A structure describing the location of a PCI device. 170 */ 171 struct rte_pci_addr { 172 uint32_t domain; /**< Device domain */ 173 uint8_t bus; /**< Device bus */ 174 uint8_t devid; /**< Device ID */ 175 uint8_t function; /**< Device function. */ 176 }; 177 178 /** Any PCI device identifier (vendor, device, ...) */ 179 #define RTE_PCI_ANY_ID (0xffff) 180 /** @deprecated Replaced with RTE_PCI_ANY_ID */ 181 #define PCI_ANY_ID RTE_DEPRECATED(PCI_ANY_ID) RTE_PCI_ANY_ID 182 #define RTE_CLASS_ANY_ID (0xffffff) 183 184 /** 185 * Utility function to write a pci device name, this device name can later be 186 * used to retrieve the corresponding rte_pci_addr using rte_pci_addr_parse(). 187 * 188 * @param addr 189 * The PCI Bus-Device-Function address 190 * @param output 191 * The output buffer string 192 * @param size 193 * The output buffer size 194 */ 195 void rte_pci_device_name(const struct rte_pci_addr *addr, 196 char *output, size_t size); 197 198 /** 199 * Utility function to compare two PCI device addresses. 200 * 201 * @param addr 202 * The PCI Bus-Device-Function address to compare 203 * @param addr2 204 * The PCI Bus-Device-Function address to compare 205 * @return 206 * 0 on equal PCI address. 207 * Positive on addr is greater than addr2. 208 * Negative on addr is less than addr2, or error. 209 */ 210 int rte_pci_addr_cmp(const struct rte_pci_addr *addr, 211 const struct rte_pci_addr *addr2); 212 213 214 /** 215 * Utility function to parse a string into a PCI location. 216 * 217 * @param str 218 * The string to parse 219 * @param addr 220 * The reference to the structure where the location 221 * is stored. 222 * @return 223 * 0 on success 224 * <0 otherwise 225 */ 226 int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr); 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif /* _RTE_PCI_H_ */ 233