1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef __INCLUDE_RTE_LRU_H__ 6 #define __INCLUDE_RTE_LRU_H__ 7 8 #include <rte_config.h> 9 #ifdef RTE_ARCH_X86_64 10 #include "rte_lru_x86.h" 11 #elif defined(RTE_ARCH_ARM64) 12 #include "rte_lru_arm64.h" 13 #else 14 #undef RTE_TABLE_HASH_LRU_STRATEGY 15 #define RTE_TABLE_HASH_LRU_STRATEGY 1 16 #endif 17 18 #if RTE_TABLE_HASH_LRU_STRATEGY == 0 19 20 #define lru_init(bucket) \ 21 do \ 22 bucket = bucket; \ 23 while (0) 24 25 #define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU) 26 27 #define lru_update(bucket, mru_val) \ 28 do { \ 29 bucket = bucket; \ 30 mru_val = mru_val; \ 31 } while (0) 32 33 #elif RTE_TABLE_HASH_LRU_STRATEGY == 1 34 35 #define lru_init(bucket) \ 36 do \ 37 bucket->lru_list = 0x0000000100020003LLU; \ 38 while (0) 39 40 #define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU) 41 42 #define lru_update(bucket, mru_val) \ 43 do { \ 44 uint64_t x, pos, x0, x1, x2, mask; \ 45 \ 46 x = bucket->lru_list; \ 47 \ 48 pos = 4; \ 49 if ((x >> 48) == ((uint64_t) mru_val)) \ 50 pos = 3; \ 51 \ 52 if (((x >> 32) & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 53 pos = 2; \ 54 \ 55 if (((x >> 16) & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 56 pos = 1; \ 57 \ 58 if ((x & 0xFFFFLLU) == ((uint64_t) mru_val)) \ 59 pos = 0; \ 60 \ 61 \ 62 pos <<= 4; \ 63 mask = (~0LLU) << pos; \ 64 x0 = x & (~mask); \ 65 x1 = (x >> 16) & mask; \ 66 x2 = (x << (48 - pos)) & (0xFFFFLLU << 48); \ 67 x = x0 | x1 | x2; \ 68 \ 69 if (pos != 64) \ 70 bucket->lru_list = x; \ 71 } while (0) 72 73 #elif (RTE_TABLE_HASH_LRU_STRATEGY == 2) || (RTE_TABLE_HASH_LRU_STRATEGY == 3) 74 75 /** 76 * These strategies are implemented in architecture specific header files. 77 */ 78 79 #else 80 81 #error "Incorrect value for RTE_TABLE_HASH_LRU_STRATEGY" 82 83 #endif 84 85 #endif 86