1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 NVIDIA Corporation & Affiliates 3 */ 4 5 #ifndef RTE_IB_H 6 #define RTE_IB_H 7 8 /** 9 * @file 10 * 11 * InfiniBand headers definitions 12 * 13 * The infiniBand headers are used by RoCE (RDMA over Converged Ethernet). 14 */ 15 16 #include <stdint.h> 17 18 #include <rte_byteorder.h> 19 20 /** 21 * InfiniBand Base Transport Header according to 22 * IB Specification Vol 1-Release-1.4. 23 */ 24 __extension__ 25 struct __rte_packed_begin rte_ib_bth { 26 uint8_t opcode; /**< Opcode. */ 27 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 28 uint8_t tver:4; /**< Transport Header Version. */ 29 uint8_t padcnt:2; /**< Pad Count. */ 30 uint8_t m:1; /**< MigReq. */ 31 uint8_t se:1; /**< Solicited Event. */ 32 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 33 uint8_t se:1; /**< Solicited Event. */ 34 uint8_t m:1; /**< MigReq. */ 35 uint8_t padcnt:2; /**< Pad Count. */ 36 uint8_t tver:4; /**< Transport Header Version. */ 37 #endif 38 rte_be16_t pkey; /**< Partition key. */ 39 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 40 uint8_t rsvd0:6; /**< Reserved. */ 41 uint8_t b:1; /**< BECN. */ 42 uint8_t f:1; /**< FECN. */ 43 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 44 uint8_t f:1; /**< FECN. */ 45 uint8_t b:1; /**< BECN. */ 46 uint8_t rsvd0:6; /**< Reserved. */ 47 #endif 48 uint8_t dst_qp[3]; /**< Destination QP */ 49 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 50 uint8_t rsvd1:7; /**< Reserved. */ 51 uint8_t a:1; /**< Acknowledge Request. */ 52 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 53 uint8_t a:1; /**< Acknowledge Request. */ 54 uint8_t rsvd1:7; /**< Reserved. */ 55 #endif 56 uint8_t psn[3]; /**< Packet Sequence Number */ 57 } __rte_packed_end; 58 59 /** RoCEv2 default port. */ 60 #define RTE_ROCEV2_DEFAULT_PORT 4791 61 62 #endif /* RTE_IB_H */ 63