1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2022 Marvell. 3 */ 4 5 #ifndef _ROC_ML_H_ 6 #define _ROC_ML_H_ 7 8 #include "roc_api.h" 9 10 #define ROC_ML_MEM_SZ (6 * 1024) 11 #define ROC_ML_TIMEOUT_MS 10000 12 13 /* ML_CFG */ 14 #define ROC_ML_CFG_JD_SIZE GENMASK_ULL(1, 0) 15 #define ROC_ML_CFG_MLIP_ENA BIT_ULL(2) 16 #define ROC_ML_CFG_BUSY BIT_ULL(3) 17 #define ROC_ML_CFG_WRAP_CLK_FORCE BIT_ULL(4) 18 #define ROC_ML_CFG_MLIP_CLK_FORCE BIT_ULL(5) 19 #define ROC_ML_CFG_ENA BIT_ULL(6) 20 21 /* ML_MLR_BASE */ 22 #define ROC_ML_MLR_BASE_BASE GENMASK_ULL(51, 0) 23 24 /* ML_STG_STATUS */ 25 #define ROC_ML_STG_STATUS_VALID BIT_ULL(0) 26 #define ROC_ML_STG_STATUS_ADDR_ERR BIT_ULL(1) 27 #define ROC_ML_STG_STATUS_DMA_ERR BIT_ULL(2) 28 #define ROC_ML_STG_STATUS_TIMEOUT BIT_ULL(3) 29 #define ROC_ML_STG_STATUS_NFAT_ERR BIT_ULL(4) 30 #define ROC_ML_STG_STATUS_JOB_ERR BIT_ULL(5) 31 #define ROC_ML_STG_STATUS_ELAPSED_TICKS GENMASK_ULL(47, 6) 32 33 /* ML_STG_CONTROL */ 34 #define ROC_ML_STG_CONTROL_FETCH_TO_RUN BIT_ULL(0) 35 #define ROC_ML_STG_CONTROL_RUN_TO_COMP BIT_ULL(1) 36 37 /* ML_AXI_BRIDGE */ 38 #define ROC_ML_AXI_BRIDGE_CTRL_AXI_RESP_CTRL BIT_ULL(0) 39 #define ROC_ML_AXI_BRIDGE_CTRL_BRIDGE_CTRL_MODE BIT_ULL(1) 40 #define ROC_ML_AXI_BRIDGE_CTRL_FORCE_AXI_ID GENMASK_ULL(11, 2) 41 #define ROC_ML_AXI_BRIDGE_CTRL_CSR_WR_BLK BIT_ULL(13) 42 #define ROC_ML_AXI_BRIDGE_CTRL_NCB_WR_BLK BIT_ULL(14) 43 #define ROC_ML_AXI_BRIDGE_CTRL_CSR_RD_BLK BIT_ULL(15) 44 #define ROC_ML_AXI_BRIDGE_CTRL_NCB_RD_BLK BIT_ULL(16) 45 #define ROC_ML_AXI_BRIDGE_CTRL_FENCE BIT_ULL(17) 46 #define ROC_ML_AXI_BRIDGE_CTRL_BUSY BIT_ULL(18) 47 #define ROC_ML_AXI_BRIDGE_CTRL_FORCE_WRESP_OK BIT_ULL(19) 48 #define ROC_ML_AXI_BRIDGE_CTRL_FORCE_RRESP_OK BIT_ULL(20) 49 #define ROC_ML_AXI_BRIDGE_CTRL_CSR_FORCE_CMPLT BIT_ULL(21) 50 #define ROC_ML_AXI_BRIDGE_CTRL_WR_CNT_GEAR GENMASK_ULL(25, 22) 51 #define ROC_ML_AXI_BRIDGE_CTRL_RD_GEAR GENMASK_ULL(28, 26) 52 #define ROC_ML_AXI_BRIDGE_CTRL_CSR_CUTTHROUGH_MODE BIT_ULL(29) 53 #define ROC_ML_AXI_BRIDGE_CTRL_GAA_WRITE_CREDITS GENMASK_ULL(33, 30) 54 #define ROC_ML_AXI_BRIDGE_CTRL_GAA_READ_CREDITS GENMASK_ULL(37, 34) 55 #define ROC_ML_AXI_BRIDGE_CTRL_GAA_LOAD_WRITE_CREDITS BIT_ULL(38) 56 #define ROC_ML_AXI_BRIDGE_CTRL_GAA_LOAD_READ_CREDITS BIT_ULL(39) 57 #define ROC_ML_AXI_BRIDGE_CTRL_FLUSH_WRITE_DATA BIT_ULL(40) 58 59 /* ML_JOB_MGR_CTRL */ 60 #define ROC_ML_JOB_MGR_CTRL_STALL_ON_ERR BIT_ULL(0) 61 #define ROC_ML_JOB_MGR_CTRL_PF_OVERRIDE BIT_ULL(1) 62 #define ROC_ML_JOB_MGR_CTRL_PF_FUNC_OVERRIDE GENMASK_ULL(19, 4) 63 #define ROC_ML_JOB_MGR_CTRL_BUSY BIT_ULL(20) 64 #define ROC_ML_JOB_MGR_CTRL_STALL_ON_IDLE BIT_ULL(21) 65 66 /* ML_JCMDQ_STATUS */ 67 #define ROC_ML_JCMDQ_STATUS_AVAIL_COUNT GENMASK_ULL(4, 0) 68 69 /* ML_ANBX_BACKP_DISABLE */ 70 #define ROC_ML_ANBX_BACKP_DISABLE_EXTMSTR_B_BACKP_DISABLE BIT_ULL(0) 71 #define ROC_ML_ANBX_BACKP_DISABLE_EXTMSTR_R_BACKP_DISABLE BIT_ULL(1) 72 73 /* ML_ANBX_NCBI_P_OVR */ 74 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MSH_DST_OVR_VLD BIT_ULL(0) 75 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MSH_DST_OVR GENMASK_ULL(11, 1) 76 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_NS_OVR_VLD BIT_ULL(12) 77 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_NS_OVR BIT_ULL(13) 78 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_PADDR_OVR_VLD BIT_ULL(14) 79 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_PADDR_OVR BIT_ULL(15) 80 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_RO_OVR_VLD BIT_ULL(16) 81 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_RO_OVR BIT_ULL(17) 82 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPADID_VAL_OVR_VLD BIT_ULL(18) 83 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPADID_VAL_OVR BIT_ULL(19) 84 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPAMDID_OVR_VLD BIT_ULL(20) 85 #define ML_ANBX_NCBI_P_OVR_ANB_NCBI_P_MPAMDID_OVR BIT_ULL(21) 86 87 /* ML_ANBX_NCBI_NP_OVR */ 88 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MSH_DST_OVR_VLD BIT_ULL(0) 89 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MSH_DST_OVR GENMASK_ULL(11, 1) 90 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_NS_OVR_VLD BIT_ULL(12) 91 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_NS_OVR BIT_ULL(13) 92 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_PADDR_OVR_VLD BIT_ULL(14) 93 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_PADDR_OVR BIT_ULL(15) 94 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_RO_OVR_VLD BIT_ULL(16) 95 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_RO_OVR BIT_ULL(17) 96 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPADID_VAL_OVR_VLD BIT_ULL(18) 97 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPADID_VAL_OVR BIT_ULL(19) 98 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPAMDID_OVR_VLD BIT_ULL(20) 99 #define ML_ANBX_NCBI_NP_OVR_ANB_NCBI_NP_MPAMDID_OVR BIT_ULL(21) 100 101 /* ML_SW_RST_CTRL */ 102 #define ROC_ML_SW_RST_CTRL_ACC_RST BIT_ULL(0) 103 #define ROC_ML_SW_RST_CTRL_CMPC_RST BIT_ULL(1) 104 105 struct roc_ml { 106 struct plt_pci_device *pci_dev; 107 plt_spinlock_t sp_spinlock; 108 plt_spinlock_t fp_spinlock; 109 uint8_t reserved[ROC_ML_MEM_SZ] __plt_cache_aligned; 110 } __plt_cache_aligned; 111 112 /* Register read and write functions */ 113 uint64_t __roc_api roc_ml_reg_read64(struct roc_ml *roc_ml, uint64_t offset); 114 void __roc_api roc_ml_reg_write64(struct roc_ml *roc_ml, uint64_t val, uint64_t offset); 115 uint32_t __roc_api roc_ml_reg_read32(struct roc_ml *roc_ml, uint64_t offset); 116 void __roc_api roc_ml_reg_write32(struct roc_ml *roc_ml, uint32_t val, uint64_t offset); 117 void __roc_api roc_ml_reg_save(struct roc_ml *roc_ml, uint64_t offset); 118 119 /* Address translation functions */ 120 uint64_t __roc_api roc_ml_addr_pa_to_offset(struct roc_ml *roc_ml, uint64_t phys_addr); 121 uint64_t __roc_api roc_ml_addr_offset_to_pa(struct roc_ml *roc_ml, uint64_t offset); 122 void *__roc_api roc_ml_addr_ap2mlip(struct roc_ml *roc_ml, void *addr); 123 void *__roc_api roc_ml_addr_mlip2ap(struct roc_ml *roc_ml, void *addr); 124 125 /* Scratch and JCMDQ functions */ 126 void __roc_api roc_ml_scratch_write_job(struct roc_ml *roc_ml, void *jd); 127 bool __roc_api roc_ml_scratch_is_valid_bit_set(struct roc_ml *roc_ml); 128 bool __roc_api roc_ml_scratch_is_done_bit_set(struct roc_ml *roc_ml); 129 bool __roc_api roc_ml_scratch_enqueue(struct roc_ml *roc_ml, void *work_ptr); 130 bool __roc_api roc_ml_scratch_dequeue(struct roc_ml *roc_ml, void *work_ptr); 131 void __roc_api roc_ml_scratch_queue_reset(struct roc_ml *roc_ml); 132 bool __roc_api roc_ml_jcmdq_enqueue_lf(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd); 133 bool __roc_api roc_ml_jcmdq_enqueue_sl(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd); 134 135 /* Device management functions */ 136 void __roc_api roc_ml_clk_force_on(struct roc_ml *roc_ml); 137 void __roc_api roc_ml_clk_force_off(struct roc_ml *roc_ml); 138 void __roc_api roc_ml_dma_stall_on(struct roc_ml *roc_ml); 139 void __roc_api roc_ml_dma_stall_off(struct roc_ml *roc_ml); 140 bool __roc_api roc_ml_mlip_is_enabled(struct roc_ml *roc_ml); 141 int __roc_api roc_ml_mlip_reset(struct roc_ml *roc_ml, bool force); 142 143 /* Device / block functions */ 144 int __roc_api roc_ml_dev_init(struct roc_ml *roc_ml); 145 int __roc_api roc_ml_dev_fini(struct roc_ml *roc_ml); 146 int __roc_api roc_ml_blk_init(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml); 147 int __roc_api roc_ml_blk_fini(struct roc_bphy *roc_bphy, struct roc_ml *roc_ml); 148 149 /* Utility functions */ 150 uint16_t __roc_api roc_ml_sso_pf_func_get(void); 151 152 #endif /*_ROC_ML_H_*/ 153