1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2023 Marvell. 3 */ 4 5 #ifndef ROC_MCS_H 6 #define ROC_MCS_H 7 8 #define MCS_AES_GCM_256_KEYLEN 32 9 10 #define ROC_MCS_MAX_AR_WINSZ BIT_ULL(31) 11 #define ROC_MCS_MAX_MTU (BIT_ULL(16) - 1) 12 13 struct roc_mcs_alloc_rsrc_req { 14 uint8_t rsrc_type; 15 uint8_t rsrc_cnt; /* Resources count */ 16 uint8_t dir; /* Macsec ingress or egress side */ 17 uint8_t all; /* Allocate all resource type one each */ 18 }; 19 20 struct roc_mcs_alloc_rsrc_rsp { 21 uint8_t flow_ids[128]; /* Index of reserved entries */ 22 uint8_t secy_ids[128]; 23 uint8_t sc_ids[128]; 24 uint8_t sa_ids[256]; 25 uint8_t rsrc_type; 26 uint8_t rsrc_cnt; /* No of entries reserved */ 27 uint8_t dir; 28 uint8_t all; 29 }; 30 31 struct roc_mcs_free_rsrc_req { 32 uint8_t rsrc_id; /* Index of the entry to be freed */ 33 uint8_t rsrc_type; 34 uint8_t dir; 35 uint8_t all; /* Free all the cam resources */ 36 }; 37 38 struct roc_mcs_flowid_entry_write_req { 39 uint64_t data[4]; 40 uint64_t mask[4]; 41 uint64_t sci; /* 105N for tx_secy_mem_map */ 42 uint8_t flow_id; 43 uint8_t secy_id; /* secyid for which flowid is mapped */ 44 uint8_t sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 45 uint8_t ena; /* Enable tcam entry */ 46 uint8_t ctr_pkt; 47 uint8_t dir; 48 }; 49 50 struct roc_mcs_secy_plcy_write_req { 51 uint64_t plcy; 52 uint8_t secy_id; 53 uint8_t dir; 54 }; 55 56 /* RX SC_CAM mapping */ 57 struct roc_mcs_rx_sc_cam_write_req { 58 uint64_t sci; /* SCI */ 59 uint64_t secy_id; /* secy index mapped to SC */ 60 uint8_t sc_id; /* SC CAM entry index */ 61 }; 62 63 struct roc_mcs_sa_plcy_write_req { 64 uint64_t plcy[2][9]; 65 uint8_t sa_index[2]; 66 uint8_t sa_cnt; 67 uint8_t dir; 68 }; 69 70 struct roc_mcs_tx_sc_sa_map { 71 uint8_t sa_index0; 72 uint8_t sa_index1; 73 uint8_t rekey_ena; 74 uint8_t sa_index0_vld; 75 uint8_t sa_index1_vld; 76 uint8_t tx_sa_active; 77 uint64_t sectag_sci; 78 uint8_t sc_id; /* used as index for SA_MEM_MAP */ 79 }; 80 81 struct roc_mcs_rx_sc_sa_map { 82 uint8_t sa_index; 83 uint8_t sa_in_use; 84 uint8_t sc_id; 85 uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 86 }; 87 88 struct roc_mcs_flowid_ena_dis_entry { 89 uint8_t flow_id; 90 uint8_t ena; 91 uint8_t dir; 92 }; 93 94 struct roc_mcs_pn_table_write_req { 95 uint64_t next_pn; 96 uint8_t pn_id; 97 uint8_t dir; 98 }; 99 100 struct roc_mcs_cam_entry_read_req { 101 uint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */ 102 uint8_t rsrc_id; 103 uint8_t dir; 104 }; 105 106 struct roc_mcs_cam_entry_read_rsp { 107 uint64_t reg_val[10]; 108 uint8_t rsrc_type; 109 uint8_t rsrc_id; 110 uint8_t dir; 111 }; 112 113 struct roc_mcs_hw_info { 114 uint8_t num_mcs_blks; /* Number of MCS blocks */ 115 uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ 116 uint8_t secy_entries; /* RX/TX SECY entries per mcs block */ 117 uint8_t sc_entries; /* RX/TX SC CAM entries per mcs block */ 118 uint16_t sa_entries; /* PN table entries = SA entries */ 119 uint64_t rsvd[16]; 120 }; 121 122 #define ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 123 #define ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 124 #define ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 125 #define ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 126 #define ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 127 #define ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 128 #define ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 129 #define ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 130 #define ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 131 #define ROC_MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 132 #define ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 133 #define ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 134 #define ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 135 #define ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 136 #define ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 137 #define ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 138 139 struct roc_mcs_intr_cfg { 140 uint64_t intr_mask; /* Interrupt enable mask */ 141 }; 142 143 struct roc_mcs_intr_info { 144 uint64_t intr_mask; 145 int sa_id; 146 uint8_t lmac_id; 147 uint64_t rsvd; 148 }; 149 150 struct roc_mcs_set_lmac_mode { 151 uint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ 152 uint8_t lmac_id; 153 uint64_t rsvd; 154 }; 155 156 struct roc_mcs_set_active_lmac { 157 uint32_t lmac_bmap; /* bitmap of active lmac per mcs block */ 158 uint16_t channel_base; /* MCS channel base */ 159 uint64_t rsvd; 160 }; 161 162 struct roc_mcs_set_pn_threshold { 163 uint64_t threshold; 164 uint8_t xpn; /* '1' for setting xpn threshold */ 165 uint8_t dir; 166 uint64_t rsvd; 167 }; 168 169 enum roc_mcs_ctrl_pkt_rule_type { 170 ROC_MCS_CTRL_PKT_RULE_TYPE_ETH, 171 ROC_MCS_CTRL_PKT_RULE_TYPE_DA, 172 ROC_MCS_CTRL_PKT_RULE_TYPE_RANGE, 173 ROC_MCS_CTRL_PKT_RULE_TYPE_COMBO, 174 ROC_MCS_CTRL_PKT_RULE_TYPE_MAC, 175 }; 176 177 struct roc_mcs_alloc_ctrl_pkt_rule_req { 178 uint8_t rule_type; 179 uint8_t dir; /* Macsec ingress or egress side */ 180 uint64_t rsvd; 181 }; 182 183 struct roc_mcs_alloc_ctrl_pkt_rule_rsp { 184 uint8_t rule_idx; 185 uint8_t rule_type; 186 uint8_t dir; 187 uint64_t rsvd; 188 }; 189 190 struct roc_mcs_free_ctrl_pkt_rule_req { 191 uint8_t rule_idx; 192 uint8_t rule_type; 193 uint8_t dir; 194 uint8_t all; /* Free all the rule resources */ 195 uint64_t rsvd; 196 }; 197 198 struct roc_mcs_ctrl_pkt_rule_write_req { 199 uint64_t data0; 200 uint64_t data1; 201 uint64_t data2; 202 uint8_t rule_idx; 203 uint8_t rule_type; 204 uint8_t dir; 205 uint64_t rsvd; 206 }; 207 208 struct roc_mcs_port_cfg_set_req { 209 /* Index of custom tag (= cstm_indx[x] in roc_mcs_custom_tag_cfg_get_rsp struct) to use 210 * when TX SECY_PLCY_MEMX[SECTAG_INSERT_MODE] = 0 (relative offset mode) 211 */ 212 uint8_t cstm_tag_rel_mode_sel; 213 /* In ingress path, custom_hdr_enb = 1 when the port is expected to receive pkts 214 * that have 8B custom header before DMAC 215 */ 216 uint8_t custom_hdr_enb; 217 /* Valid fifo skid values are 14,28,56 for 25G,50G,100G respectively 218 * FIFOs need to be configured based on the port_mode, valid only for 105N 219 */ 220 uint8_t fifo_skid; 221 uint8_t port_mode; /* 2'b00 - 25G or less, 2'b01 - 50G, 2'b10 - 100G */ 222 uint8_t port_id; 223 uint64_t rsvd; 224 }; 225 226 struct roc_mcs_port_cfg_get_req { 227 uint8_t port_id; 228 uint64_t rsvd; 229 }; 230 231 struct roc_mcs_port_cfg_get_rsp { 232 uint8_t cstm_tag_rel_mode_sel; 233 uint8_t custom_hdr_enb; 234 uint8_t fifo_skid; 235 uint8_t port_mode; 236 uint8_t port_id; 237 uint64_t rsvd; 238 }; 239 240 struct roc_mcs_custom_tag_cfg_get_req { 241 uint8_t dir; 242 uint64_t rsvd; 243 }; 244 245 struct roc_mcs_custom_tag_cfg_get_rsp { 246 uint16_t cstm_etype[8]; /* EthType/TPID */ 247 uint8_t cstm_indx[8]; /* Custom tag index used to identify the VLAN etype */ 248 uint8_t cstm_etype_en; /* bitmap of enabled custom tags */ 249 uint8_t dir; 250 uint64_t rsvd; 251 }; 252 253 struct roc_mcs_port_reset_req { 254 uint8_t port_id; 255 uint64_t rsvd; 256 }; 257 258 struct roc_mcs_stats_req { 259 uint8_t id; 260 uint8_t dir; 261 }; 262 263 struct roc_mcs_flowid_stats { 264 uint64_t tcam_hit_cnt; 265 }; 266 267 struct roc_mcs_secy_stats { 268 uint64_t ctl_pkt_bcast_cnt; 269 uint64_t ctl_pkt_mcast_cnt; 270 uint64_t ctl_pkt_ucast_cnt; 271 uint64_t ctl_octet_cnt; 272 uint64_t unctl_pkt_bcast_cnt; 273 uint64_t unctl_pkt_mcast_cnt; 274 uint64_t unctl_pkt_ucast_cnt; 275 uint64_t unctl_octet_cnt; 276 /* Valid only for RX */ 277 uint64_t octet_decrypted_cnt; 278 uint64_t octet_validated_cnt; 279 uint64_t pkt_port_disabled_cnt; 280 uint64_t pkt_badtag_cnt; 281 uint64_t pkt_nosa_cnt; 282 uint64_t pkt_nosaerror_cnt; 283 uint64_t pkt_tagged_ctl_cnt; 284 uint64_t pkt_untaged_cnt; 285 uint64_t pkt_ctl_cnt; /* CN10K-B */ 286 uint64_t pkt_notag_cnt; /* CNF10K-B */ 287 /* Valid only for TX */ 288 uint64_t octet_encrypted_cnt; 289 uint64_t octet_protected_cnt; 290 uint64_t pkt_noactivesa_cnt; 291 uint64_t pkt_toolong_cnt; 292 uint64_t pkt_untagged_cnt; 293 }; 294 295 struct roc_mcs_sc_stats { 296 /* RX */ 297 uint64_t hit_cnt; 298 uint64_t pkt_invalid_cnt; 299 uint64_t pkt_late_cnt; 300 uint64_t pkt_notvalid_cnt; 301 uint64_t pkt_unchecked_cnt; 302 uint64_t pkt_delay_cnt; /* CNF10K-B */ 303 uint64_t pkt_ok_cnt; /* CNF10K-B */ 304 uint64_t octet_decrypt_cnt; /* CN10K-B */ 305 uint64_t octet_validate_cnt; /* CN10K-B */ 306 /* TX */ 307 uint64_t pkt_encrypt_cnt; 308 uint64_t pkt_protected_cnt; 309 uint64_t octet_encrypt_cnt; /* CN10K-B */ 310 uint64_t octet_protected_cnt; /* CN10K-B */ 311 }; 312 313 struct roc_mcs_port_stats { 314 uint64_t tcam_miss_cnt; 315 uint64_t parser_err_cnt; 316 uint64_t preempt_err_cnt; /* CNF10K-B */ 317 uint64_t sectag_insert_err_cnt; 318 }; 319 320 struct roc_mcs_clear_stats { 321 uint8_t type; /* FLOWID, SECY, SC, SA, PORT */ 322 /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 323 uint8_t id; 324 uint8_t dir; 325 uint8_t all; /* All resources stats mapped to PF are cleared */ 326 }; 327 328 enum roc_mcs_event_subtype { 329 ROC_MCS_SUBEVENT_UNKNOWN, 330 331 /* subevents of ROC_MCS_EVENT_SECTAG_VAL_ERR sectag validation events 332 * ROC_MCS_EVENT_RX_SECTAG_V_EQ1 333 * Validation check: SecTag.TCI.V = 1 334 * ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1 335 * Validation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1 336 * ROC_MCS_EVENT_RX_SECTAG_SL_GTE48 337 * Validation check: SecTag.SL >= 'd48 338 * ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1 339 * Validation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1 340 * ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1 341 * Validation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1 342 */ 343 ROC_MCS_EVENT_RX_SECTAG_V_EQ1, 344 ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1, 345 ROC_MCS_EVENT_RX_SECTAG_SL_GTE48, 346 ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1, 347 ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1, 348 349 /* subevents of ROC_MCS_EVENT_FIFO_OVERFLOW error event 350 * ROC_MCS_EVENT_DATA_FIFO_OVERFLOW: 351 * Notifies data FIFO overflow fatal error in BBE unit. 352 * ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW 353 * Notifies policy FIFO overflow fatal error in BBE unit. 354 * ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW, 355 * Notifies output FIFO overflow fatal error in PAB unit. 356 */ 357 ROC_MCS_EVENT_DATA_FIFO_OVERFLOW, 358 ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW, 359 ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW, 360 }; 361 362 enum roc_mcs_event_type { 363 ROC_MCS_EVENT_UNKNOWN, 364 365 /* Notifies BBE_INT_DFIFO/PLFIFO_OVERFLOW or PAB_INT_OVERFLOW 366 * interrupts, it's a fatal error that causes packet corruption. 367 */ 368 ROC_MCS_EVENT_FIFO_OVERFLOW, 369 370 /* Notifies CPM_RX_SECTAG_X validation error interrupt */ 371 ROC_MCS_EVENT_SECTAG_VAL_ERR, 372 /* Notifies CPM_RX_PACKET_XPN_EQ0 (SecTag.PN == 0 in ingress) interrupt */ 373 ROC_MCS_EVENT_RX_SA_PN_HARD_EXP, 374 /* Notifies CPM_RX_PN_THRESH_REACHED interrupt */ 375 ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP, 376 /* Notifies CPM_TX_PACKET_XPN_EQ0 (PN wrapped in egress) interrupt */ 377 ROC_MCS_EVENT_TX_SA_PN_HARD_EXP, 378 /* Notifies CPM_TX_PN_THRESH_REACHED interrupt */ 379 ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP, 380 /* Notifies CPM_TX_SA_NOT_VALID interrupt */ 381 ROC_MCS_EVENT_SA_NOT_VALID, 382 /* Notifies recovery of software driven port reset */ 383 ROC_MCS_EVENT_PORT_RESET_RECOVERY, 384 }; 385 386 union roc_mcs_event_data { 387 /* Valid for below events 388 * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP 389 * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP 390 */ 391 struct { 392 uint8_t secy_idx; 393 uint8_t sc_idx; 394 uint8_t sa_idx; 395 }; 396 /* Valid for below event 397 * - ROC_MCS_EVENT_FIFO_OVERFLOW 398 * 399 * Upon fatal error notification on a MCS port, ROC driver resets below attributes of active 400 * flow entities(sc & sa) and than resets the port. 401 * - Reset NEXT_PN of active SAs to 1. 402 * - Reset TX active SA for each SC, TX_SA_ACTIVE = 0, SA_INDEX0_VLD = 1. 403 * - Clear SA_IN_USE for active ANs in RX_SA_MAP_MEM. 404 * - Clear all stats mapping to this port. 405 * - Reactivate SA_IN_USE for active ANs in RX_SA_MAP_MEM. 406 * 407 * ROC driver notifies the following flow entity(sc & sa) details in application callback, 408 * application is expected to exchange the Tx/Rx NEXT_PN, TX_SA_ACTIVE, active RX SC AN 409 * details with peer device so that peer device can resets it's MACsec flow states and than 410 * resume packet transfers. 411 */ 412 struct { 413 uint16_t *tx_sa_array; /* Tx SAs whose PN memories were reset (NEXT_PN=1) */ 414 uint16_t *rx_sa_array; /* Rx SAs whose PN memories were reset (NEXT_PN=1) */ 415 uint16_t *tx_sc_array; /* Tx SCs whose active SAs were reset (TX_SA_ACTIVE=0) */ 416 uint16_t *rx_sc_array; /* Rx SCs whose state was reset */ 417 uint8_t *sc_an_array; /* AN of Rx SCs(in rx_sc_array) which were reactivated */ 418 uint8_t num_tx_sa; /* num entries in tx_sa_array */ 419 uint8_t num_rx_sa; /* num entries in rx_sa_array */ 420 uint8_t num_tx_sc; /* num entries in tx_sc_array */ 421 uint8_t num_rx_sc; /* num entries in rx_sc_array */ 422 uint8_t lmac_id; /* lmac_id/port which was recovered from fatal error */ 423 }; 424 }; 425 426 struct roc_mcs_event_desc { 427 enum roc_mcs_event_type type; 428 enum roc_mcs_event_subtype subtype; 429 union roc_mcs_event_data metadata; 430 }; 431 432 struct roc_mcs_fips_req { 433 uint8_t dir; 434 }; 435 436 struct roc_mcs_fips_mode { 437 uint64_t mode; 438 uint8_t dir; 439 }; 440 441 struct roc_mcs_fips_ctl { 442 uint64_t ctl; 443 uint8_t dir; 444 }; 445 446 struct roc_mcs_fips_iv { 447 uint32_t iv_bits95_64; 448 uint64_t iv_bits63_0; 449 uint8_t dir; 450 }; 451 452 struct roc_mcs_fips_ctr { 453 uint32_t fips_ctr; 454 uint8_t dir; 455 }; 456 457 struct roc_mcs_fips_key { 458 uint64_t sak_bits255_192; 459 uint64_t sak_bits191_128; 460 uint64_t sak_bits127_64; 461 uint64_t sak_bits63_0; 462 uint64_t hashkey_bits127_64; 463 uint64_t hashkey_bits63_0; 464 uint8_t sak_len; 465 uint8_t dir; 466 }; 467 468 struct roc_mcs_fips_block { 469 uint64_t blk_bits127_64; 470 uint64_t blk_bits63_0; 471 uint8_t dir; 472 }; 473 474 struct roc_mcs_fips_result_rsp { 475 uint64_t blk_bits127_64; 476 uint64_t blk_bits63_0; 477 uint64_t icv_bits127_64; 478 uint64_t icv_bits63_0; 479 uint8_t result_pass; 480 }; 481 482 /** User application callback to be registered for any notifications from driver. */ 483 typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg, 484 uint8_t port_id); 485 486 struct roc_mcs { 487 TAILQ_ENTRY(roc_mcs) next; 488 struct plt_pci_device *pci_dev; 489 struct mbox *mbox; 490 uint8_t idx; 491 uint8_t refcount; 492 bool intr_cfg_once; 493 uint8_t *sa_port_map; 494 495 #define ROC_MCS_MEM_SZ (1 * 1024) 496 uint8_t reserved[ROC_MCS_MEM_SZ] __plt_cache_aligned; 497 } __plt_cache_aligned; 498 499 TAILQ_HEAD(roc_mcs_head, roc_mcs); 500 501 /* Initialization */ 502 __roc_api struct roc_mcs *roc_mcs_dev_init(uint8_t mcs_idx); 503 __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); 504 /* Get roc mcs dev structure */ 505 __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); 506 /* HW info get */ 507 __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); 508 /* Active lmac bmap set */ 509 __roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac); 510 /* Port bypass mode set */ 511 __roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port); 512 /* (X)PN threshold set */ 513 __roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn); 514 /* Reset port */ 515 __roc_api int roc_mcs_port_reset(struct roc_mcs *mcs, struct roc_mcs_port_reset_req *port); 516 /* Get port config */ 517 __roc_api int roc_mcs_port_cfg_set(struct roc_mcs *mcs, struct roc_mcs_port_cfg_set_req *req); 518 /* Set port config */ 519 __roc_api int roc_mcs_port_cfg_get(struct roc_mcs *mcs, struct roc_mcs_port_cfg_get_req *req, 520 struct roc_mcs_port_cfg_get_rsp *rsp); 521 /* Get custom tag config */ 522 __roc_api int roc_mcs_custom_tag_cfg_get(struct roc_mcs *mcs, 523 struct roc_mcs_custom_tag_cfg_get_req *req, 524 struct roc_mcs_custom_tag_cfg_get_rsp *rsp); 525 526 /* Resource allocation and free */ 527 __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, 528 struct roc_mcs_alloc_rsrc_rsp *rsp); 529 __roc_api int roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req); 530 /* SA policy read and write */ 531 __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, 532 struct roc_mcs_sa_plcy_write_req *sa_plcy); 533 __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, 534 struct roc_mcs_sa_plcy_write_req *sa_plcy); 535 536 /* PN Table read and write */ 537 __roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs, 538 struct roc_mcs_pn_table_write_req *pn_table); 539 __roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs, 540 struct roc_mcs_pn_table_write_req *pn_table); 541 542 /* RX SC read, write and enable */ 543 __roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, 544 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); 545 __roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs, 546 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); 547 __roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs, 548 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); 549 /* SECY policy read and write */ 550 __roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs, 551 struct roc_mcs_secy_plcy_write_req *secy_plcy); 552 __roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs, 553 struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); 554 /* RX SC-SA MAP read and write */ 555 __roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, 556 struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); 557 __roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs, 558 struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); 559 /* TX SC-SA MAP read and write */ 560 __roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, 561 struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); 562 __roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs, 563 struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); 564 /* SA to Port map update */ 565 __roc_api void roc_mcs_sa_port_map_update(struct roc_mcs *mcs, int sa_id, uint8_t port_id); 566 567 /* Flow entry read, write and enable */ 568 __roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs, 569 struct roc_mcs_flowid_entry_write_req *flowid_req); 570 __roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs, 571 struct roc_mcs_flowid_entry_write_req *flowid_rsp); 572 __roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, 573 struct roc_mcs_flowid_ena_dis_entry *entry); 574 575 /* Control packet rule alloc, free and write */ 576 __roc_api int roc_mcs_ctrl_pkt_rule_alloc(struct roc_mcs *mcs, 577 struct roc_mcs_alloc_ctrl_pkt_rule_req *req, 578 struct roc_mcs_alloc_ctrl_pkt_rule_rsp *rsp); 579 __roc_api int roc_mcs_ctrl_pkt_rule_free(struct roc_mcs *mcs, 580 struct roc_mcs_free_ctrl_pkt_rule_req *req); 581 __roc_api int roc_mcs_ctrl_pkt_rule_write(struct roc_mcs *mcs, 582 struct roc_mcs_ctrl_pkt_rule_write_req *req); 583 584 /* Flow id stats get */ 585 __roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, 586 struct roc_mcs_flowid_stats *stats); 587 /* Secy stats get */ 588 __roc_api int roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, 589 struct roc_mcs_secy_stats *stats); 590 /* SC stats get */ 591 __roc_api int roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, 592 struct roc_mcs_sc_stats *stats); 593 /* Port stats get */ 594 __roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req, 595 struct roc_mcs_port_stats *stats); 596 /* Clear stats */ 597 __roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req); 598 599 /* Register user callback routines */ 600 __roc_api int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event, 601 roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata); 602 /* Unregister user callback routines */ 603 __roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event); 604 605 /* Configure interrupts */ 606 __roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config); 607 608 /* Port recovery from fatal errors */ 609 __roc_api int roc_mcs_port_recovery(struct roc_mcs *mcs, union roc_mcs_event_data *mdata, 610 uint8_t port_id); 611 612 /* FIPS reset */ 613 __roc_api int roc_mcs_fips_reset(struct roc_mcs *mcs, struct roc_mcs_fips_req *req); 614 /* FIPS mode set */ 615 __roc_api int roc_mcs_fips_mode_set(struct roc_mcs *mcs, struct roc_mcs_fips_mode *req); 616 /* FIPS ctl set */ 617 __roc_api int roc_mcs_fips_ctl_set(struct roc_mcs *mcs, struct roc_mcs_fips_ctl *req); 618 /* FIPS iv set */ 619 __roc_api int roc_mcs_fips_iv_set(struct roc_mcs *mcs, struct roc_mcs_fips_iv *req); 620 /* FIPS ctr set */ 621 __roc_api int roc_mcs_fips_ctr_set(struct roc_mcs *mcs, struct roc_mcs_fips_ctr *req); 622 /* FIPS key set */ 623 __roc_api int roc_mcs_fips_key_set(struct roc_mcs *mcs, struct roc_mcs_fips_key *req); 624 /* FIPS block set */ 625 __roc_api int roc_mcs_fips_block_set(struct roc_mcs *mcs, struct roc_mcs_fips_block *req); 626 /* FIPS start */ 627 __roc_api int roc_mcs_fips_start(struct roc_mcs *mcs, struct roc_mcs_fips_req *req); 628 /* FIPS result */ 629 __roc_api int roc_mcs_fips_result_get(struct roc_mcs *mcs, struct roc_mcs_fips_req *req, 630 struct roc_mcs_fips_result_rsp *rsp); 631 #endif /* ROC_MCS_H */ 632