1 /* $NetBSD: radeon_ci_smc.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: radeon_ci_smc.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
29
30 #include <linux/firmware.h>
31
32 #include "radeon.h"
33 #include "cikd.h"
34 #include "ppsmc.h"
35 #include "radeon_ucode.h"
36 #include "ci_dpm.h"
37
ci_set_smc_sram_address(struct radeon_device * rdev,u32 smc_address,u32 limit)38 static int ci_set_smc_sram_address(struct radeon_device *rdev,
39 u32 smc_address, u32 limit)
40 {
41 if (smc_address & 3)
42 return -EINVAL;
43 if ((smc_address + 3) > limit)
44 return -EINVAL;
45
46 WREG32(SMC_IND_INDEX_0, smc_address);
47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
48
49 return 0;
50 }
51
ci_copy_bytes_to_smc(struct radeon_device * rdev,u32 smc_start_address,const u8 * src,u32 byte_count,u32 limit)52 int ci_copy_bytes_to_smc(struct radeon_device *rdev,
53 u32 smc_start_address,
54 const u8 *src, u32 byte_count, u32 limit)
55 {
56 unsigned long flags;
57 u32 data, original_data;
58 u32 addr;
59 u32 extra_shift;
60 int ret = 0;
61
62 if (smc_start_address & 3)
63 return -EINVAL;
64 if ((smc_start_address + byte_count) > limit)
65 return -EINVAL;
66
67 addr = smc_start_address;
68
69 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
70 while (byte_count >= 4) {
71 /* SMC address space is BE */
72 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
73
74 ret = ci_set_smc_sram_address(rdev, addr, limit);
75 if (ret)
76 goto done;
77
78 WREG32(SMC_IND_DATA_0, data);
79
80 src += 4;
81 byte_count -= 4;
82 addr += 4;
83 }
84
85 /* RMW for the final bytes */
86 if (byte_count > 0) {
87 data = 0;
88
89 ret = ci_set_smc_sram_address(rdev, addr, limit);
90 if (ret)
91 goto done;
92
93 original_data = RREG32(SMC_IND_DATA_0);
94
95 extra_shift = 8 * (4 - byte_count);
96
97 while (byte_count > 0) {
98 data = (data << 8) + *src++;
99 byte_count--;
100 }
101
102 data <<= extra_shift;
103
104 data |= (original_data & ~((~0UL) << extra_shift));
105
106 ret = ci_set_smc_sram_address(rdev, addr, limit);
107 if (ret)
108 goto done;
109
110 WREG32(SMC_IND_DATA_0, data);
111 }
112
113 done:
114 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
115
116 return ret;
117 }
118
ci_start_smc(struct radeon_device * rdev)119 void ci_start_smc(struct radeon_device *rdev)
120 {
121 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
122
123 tmp &= ~RST_REG;
124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
125 }
126
ci_reset_smc(struct radeon_device * rdev)127 void ci_reset_smc(struct radeon_device *rdev)
128 {
129 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
130
131 tmp |= RST_REG;
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
133 }
134
ci_program_jump_on_start(struct radeon_device * rdev)135 int ci_program_jump_on_start(struct radeon_device *rdev)
136 {
137 static const u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };
138
139 return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
140 }
141
ci_stop_smc_clock(struct radeon_device * rdev)142 void ci_stop_smc_clock(struct radeon_device *rdev)
143 {
144 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
145
146 tmp |= CK_DISABLE;
147
148 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
149 }
150
ci_start_smc_clock(struct radeon_device * rdev)151 void ci_start_smc_clock(struct radeon_device *rdev)
152 {
153 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
154
155 tmp &= ~CK_DISABLE;
156
157 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
158 }
159
ci_is_smc_running(struct radeon_device * rdev)160 bool ci_is_smc_running(struct radeon_device *rdev)
161 {
162 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
163 u32 pc_c = RREG32_SMC(SMC_PC_C);
164
165 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c))
166 return true;
167
168 return false;
169 }
170
171 #if 0
172 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)
173 {
174 u32 tmp;
175 int i;
176
177 if (!ci_is_smc_running(rdev))
178 return PPSMC_Result_OK;
179
180 for (i = 0; i < rdev->usec_timeout; i++) {
181 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
182 if ((tmp & CKEN) == 0)
183 break;
184 udelay(1);
185 }
186
187 return PPSMC_Result_OK;
188 }
189 #endif
190
ci_load_smc_ucode(struct radeon_device * rdev,u32 limit)191 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
192 {
193 unsigned long flags;
194 u32 ucode_start_address;
195 u32 ucode_size;
196 const u8 *src;
197 u32 data;
198
199 if (!rdev->smc_fw)
200 return -EINVAL;
201
202 if (rdev->new_fw) {
203 const struct smc_firmware_header_v1_0 *hdr =
204 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data;
205
206 radeon_ucode_print_smc_hdr(&hdr->header);
207
208 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
209 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
210 src = (const u8 *)
211 (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
212 } else {
213 switch (rdev->family) {
214 case CHIP_BONAIRE:
215 ucode_start_address = BONAIRE_SMC_UCODE_START;
216 ucode_size = BONAIRE_SMC_UCODE_SIZE;
217 break;
218 case CHIP_HAWAII:
219 ucode_start_address = HAWAII_SMC_UCODE_START;
220 ucode_size = HAWAII_SMC_UCODE_SIZE;
221 break;
222 default:
223 DRM_ERROR("unknown asic in smc ucode loader\n");
224 BUG();
225 }
226
227 src = (const u8 *)rdev->smc_fw->data;
228 }
229
230 if (ucode_size & 3)
231 return -EINVAL;
232
233 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
234 WREG32(SMC_IND_INDEX_0, ucode_start_address);
235 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
236 while (ucode_size >= 4) {
237 /* SMC address space is BE */
238 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
239
240 WREG32(SMC_IND_DATA_0, data);
241
242 src += 4;
243 ucode_size -= 4;
244 }
245 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
246 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
247
248 return 0;
249 }
250
ci_read_smc_sram_dword(struct radeon_device * rdev,u32 smc_address,u32 * value,u32 limit)251 int ci_read_smc_sram_dword(struct radeon_device *rdev,
252 u32 smc_address, u32 *value, u32 limit)
253 {
254 unsigned long flags;
255 int ret;
256
257 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
258 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
259 if (ret == 0)
260 *value = RREG32(SMC_IND_DATA_0);
261 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
262
263 return ret;
264 }
265
ci_write_smc_sram_dword(struct radeon_device * rdev,u32 smc_address,u32 value,u32 limit)266 int ci_write_smc_sram_dword(struct radeon_device *rdev,
267 u32 smc_address, u32 value, u32 limit)
268 {
269 unsigned long flags;
270 int ret;
271
272 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
273 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
274 if (ret == 0)
275 WREG32(SMC_IND_DATA_0, value);
276 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
277
278 return ret;
279 }
280