1 typedef struct I2Cdev I2Cdev; 2 typedef struct PCMconftab PCMconftab; 3 typedef struct PCMmap PCMmap; 4 typedef struct PCMslot PCMslot; 5 6 #define INTRREG ((IntrReg*)PHYSINTR) 7 typedef struct IntrReg IntrReg; 8 struct IntrReg { 9 ulong icip; /* IRQ pending */ 10 ulong icmr; /* mask */ 11 ulong iclr; /* level */ 12 ulong icfp; /* FIQ pending */ 13 ulong icpr; /* pending */ 14 ulong iccr; /* control */ 15 }; 16 17 /* 18 * types of interrupts 19 */ 20 enum 21 { 22 GPIOrising, 23 GPIOfalling, 24 GPIOboth, 25 IRQ, 26 }; 27 28 enum { 29 /* first-level interrupts (table 4-36) */ 30 IRQrtc= 31, 31 IRQhz= 30, 32 IRQtimer3= 29, 33 IRQtimer2= 28, 34 IRQtimer1= 27, 35 IRQtimer0= 26, 36 IRQdma= 25, 37 IRQssp= 24, 38 IRQmmc= 23, 39 IRQffuart= 22, 40 IRQbtuart= 21, 41 IRQstuart= 20, 42 IRQicp= 19, 43 IRQi2c= 18, 44 IRQlcd= 17, 45 IRQnssp= 16, 46 IRQac97= 14, 47 IRQi2s= 13, 48 IRQpmu= 12, 49 IRQusb= 11, 50 IRQgpio= 10, 51 IRQgpio1= 9, 52 IRQgpio0= 8, 53 IRQhwuart= 7, 54 }; 55 56 #define GPIOREG ((GpioReg*)PHYSGPIO) 57 typedef struct GpioReg GpioReg; 58 struct GpioReg { 59 ulong gplr[3]; 60 ulong gpdr[3]; 61 ulong gpsr[3]; 62 ulong gpcr[3]; 63 ulong grer[3]; 64 ulong gfer[3]; 65 ulong gedr[3]; 66 ulong gafr[6]; 67 }; 68 69 enum { 70 /* GPIO alternative functions if gafr bits set (see table 4-1, pp. 4-3 to 4-6) */ 71 GPIO_GP_RST_1_i= 1, /* active low GP_reset */ 72 GPIO_FFRXD_1_i= 34, /* FFUART receive */ 73 GPIO_FFTXD_2_o= 39, /* FFUART transmit */ 74 75 MaxGPIObit= 84, 76 MaxGPIOIRQ= 1, 77 }; 78 #define GPB(n) (1<<((n)&31)) 79 #define GPR(n) ((n)>>5) 80 #define GPAF(n,v) ((v)<<(((n)&15)*2)) 81 82 void gpioreserve(int); 83 void gpioconfig(int, ulong); 84 ulong gpioget(int); 85 void gpioset(int, int); 86 void gpiorelease(int); 87 88 enum { 89 /* software configuration bits for gpioconfig */ 90 Gpio_gpio= 0<<0, 91 Gpio_Alt1= 1<<0, 92 Gpio_Alt2= 2<<0, 93 Gpio_Alt3= 3<<0, 94 Gpio_in= 1<<2, 95 Gpio_out= 1<<3, 96 }; 97 98 /* 99 * software structures used by ../port/devi2c.c and iic.c 100 */ 101 struct I2Cdev { 102 int addr; 103 int salen; /* length in bytes of subaddress, if used; 0 otherwise */ 104 int tenbit; /* 10-bit addresses */ 105 }; 106 107 long i2crecv(I2Cdev*, void*, long, ulong); 108 long i2csend(I2Cdev*, void*, long, ulong); 109 void i2csetup(int); 110 111 #define COREREG ((Coreregs*)PHYSCORE) 112 typedef struct Coreregs Coreregs; 113 struct Coreregs { 114 ulong cccr; /* core clock config */ 115 ulong cken; /* clock enable */ 116 ulong oscc; /* oscillator configuration */ 117 }; 118 119 #define RTCREG ((RTCreg*)PHYSRTC) 120 typedef struct RTCreg RTCreg; 121 struct RTCreg { 122 ulong rcnr; /* count */ 123 ulong rtar; /* alarm */ 124 ulong rtsr; /* status */ 125 ulong rttr; /* trim */ 126 }; 127 128 #define OSTMRREG ((OstmrReg*)PHYSOSTMR) 129 typedef struct OstmrReg OstmrReg; 130 struct OstmrReg { 131 ulong osmr[4]; /* match */ 132 ulong oscr; /* counter */ 133 ulong ossr; /* status */ 134 ulong ower; /* watchdog */ 135 ulong oier; /* interrupt enable */ 136 }; 137 138 #define PMGRREG ((PmgrReg*)PHYSPOWER) 139 typedef struct PmgrReg PmgrReg; 140 struct PmgrReg { 141 ulong pmcr; /* ctl register */ 142 ulong pssr; /* sleep status */ 143 ulong pspr; /* scratch pad */ 144 ulong pwer; /* wakeup enable */ 145 ulong prer; /* rising-edge detect enable */ 146 ulong pfer; /* falling-edge detect enable */ 147 ulong pedr; /* GPIO edge detect status */ 148 ulong pcfr; /* general configuration */ 149 ulong pgsr[3]; /* GPIO sleep state */ 150 ulong rsvd; 151 ulong rcsr; /* reset controller status register */ 152 }; 153 154 enum { 155 /* pp. 3-25 to 3-31 */ 156 PWER_rtc = 1<<31, /* wakeup by RTC alarm */ 157 PWER_we0 = 1<<0, /* wake-up on GP0 edge detect */ 158 159 PSSR_sss = 1<<0, /* software sleep status */ 160 PSSR_bfs = 1<<1, /* battery fault status */ 161 PSSR_vfs = 1<<2, /* VDD fault status */ 162 PSSR_ph = 1<<4, /* peripheral control hold */ 163 PSSR_rdh = 1<<5, /* read disable hold */ 164 165 PMFW_fwake= 1<<1, /* fast wakeup enable (no power stabilisation delay) */ 166 167 RSCR_gpr= 1<<3, /* gpio reset has occurred */ 168 RSCR_smr= 1<<2, /* sleep mode has occurred */ 169 RSCR_wdr= 1<<1, /* watchdog reset has occurred */ 170 RSCR_hwr= 1<<0, /* hardware reset has occurred */ 171 }; 172 173 #define MEMCFGREG ((MemcfgReg*)PHYSMEMCFG) 174 typedef struct MemcfgReg MemcfgReg; 175 struct MemcfgReg { 176 ulong mdcnfg; /* SDRAM config */ 177 ulong mdrefr; /* dram refresh */ 178 ulong msc0; /* static memory or devices */ 179 ulong msc1; 180 ulong msc2; /* static memory or devices */ 181 ulong mecr; /* expansion bus (pcmcia, CF) */ 182 ulong sxcnfg; /* synchronous static memory control */ 183 ulong sxmrs; /* MRS value to write to SMROM */ 184 ulong mcmem0; /* card interface socket 0 memory timing */ 185 ulong mcmem1; /* card interface socket 1 memory timing */ 186 ulong mcatt0; /* socket 0 attribute memory timing */ 187 ulong mcatt1; /* socket 1 attribute memory timing */ 188 ulong mcio0; /* socket 0 i/o timing */ 189 ulong mcio1; /* socket 1 i/o timing */ 190 ulong mdmrs; /* MRS value to write to SDRAM */ 191 ulong boot_def; /* read-only boot-time register */ 192 ulong mdmrslp; /* low-power SDRAM mode register set config */ 193 ulong sa1111cr; /* SA1111 compatibility */ 194 }; 195 196 #define LCDREG ((LcdReg*)PHYSLCD) 197 typedef struct LcdReg LcdReg; 198 struct LcdReg { 199 ulong lccr0; /* control 0 */ 200 ulong lccr1; /* control 1 */ 201 ulong lccr2; /* control 2 */ 202 ulong lccr3; /* control 3 */ 203 struct { 204 ulong fdadr; /* dma frame descriptor address register */ 205 ulong fsadr; /* dma frame source address register */ 206 ulong fidr; /* dma frame ID register */ 207 ulong ldcmd; /* dma command */ 208 } frame[2]; 209 ulong fbr[2]; /* frame branch register */ 210 ulong lcsr; /* status */ 211 ulong liidr; /* interrupt ID register */ 212 ulong trgbr; /* TMED RGB seed register */ 213 ulong tcr; /* TMED control register */ 214 }; 215 216 #define USBREG ((UsbReg*)PHYSUSB) 217 typedef struct UsbReg UsbReg; 218 struct UsbReg { 219 ulong udccr; /* control */ 220 ulong udccs[16]; /* endpoint control/status */ 221 ulong ufnrh; /* frame number high */ 222 ulong ufnrl; /* frame number low */ 223 ulong udbcr2; 224 ulong udbcr4; 225 ulong udbcr7; 226 ulong udbcr9; 227 ulong udbcr12; 228 ulong udbcr14; 229 ulong uddr[16]; /* endpoint data */ 230 ulong uicr0; 231 ulong uicr1; 232 ulong usir0; 233 ulong usir1; 234 }; 235 236 enum { 237 /* DMA configuration parameters */ 238 239 /* DMA Direction */ 240 DmaOut= 0, 241 DmaIn= 1, 242 243 /* dma devices */ 244 DmaDREQ0= 0, 245 DmaDREQ1, 246 DmaI2S_i, 247 DmaI2S_o, 248 DmaBTUART_i, 249 DmaBTUART_o, 250 DmaFFUART_i, 251 DmaFFUART_o, 252 DmaAC97mic, 253 DmaAC97modem_i, 254 DmaAC97modem_o, 255 DmaAC97audio_i, 256 DmaAC97audio_o, 257 DmaSSP_i, 258 DmaSSP_o, 259 DmaNSSP_i, 260 DmaNSSP_o, 261 DmaICP_i, 262 DmaICP_o, 263 DmaSTUART_i, 264 DmaSTUART_o, 265 DmaMMC_i, 266 DmaMMC_o, 267 DmaRsvd0, 268 DmaRsvd1, 269 DmaUSB1, 270 DmaUSB2, 271 DmaUSB3, 272 DmaUSB4, 273 DmaHWUART_i, 274 DmaUSB6, 275 DmaUSB7, 276 DmaUSB8, 277 DmaUSB9, 278 DmaHWUART_o, 279 DmaUSB11, 280 DmaUSB12, 281 DmaUSB13, 282 DmaUSB14, 283 DmaRsvd2, 284 }; 285 286 /* 287 * Interface to platform-specific PCMCIA signals, in arch*.c 288 */ 289 enum { 290 /* argument to pcmpin() */ 291 PCMready, 292 PCMeject, 293 PCMstschng, 294 }; 295 296 /* 297 * physical device addresses are mapped to the same virtual ones, 298 * allowing the same addresses to be used with or without mmu. 299 */ 300 301 #define PCMCIAcard(n) (PHYSPCMCIA0+((n)*PCMCIASIZE)) 302 #define PCMCIAIO(n) (PCMCIAcard(n)+0x0) /* I/O space */ 303 #define PCMCIAAttr(n) (PCMCIAcard(n)+0x8000000) /* Attribute space*/ 304 #define PCMCIAMem(n) (PCMCIAcard(n)+0xC000000) /* Memory space */ 305 306 /* 307 * PCMCIA structures known by both port/cis.c and the pcmcia driver 308 */ 309 310 /* 311 * Map between ISA memory space and PCMCIA card memory space. 312 */ 313 struct PCMmap { 314 ulong ca; /* card address */ 315 ulong cea; /* card end address */ 316 ulong isa; /* local virtual address */ 317 int len; /* length of the ISA area */ 318 int attr; /* attribute memory */ 319 }; 320 321 /* 322 * a PCMCIA configuration entry 323 */ 324 struct PCMconftab 325 { 326 int index; 327 ushort irqs; /* legal irqs */ 328 uchar irqtype; 329 uchar bit16; /* true for 16 bit access */ 330 uchar nlines; 331 struct { 332 ulong start; 333 ulong len; 334 } io[16]; 335 int nio; 336 uchar vcc; 337 uchar vpp1; 338 uchar vpp2; 339 uchar memwait; 340 ulong maxwait; 341 ulong readywait; 342 ulong otherwait; 343 }; 344 345 /* 346 * PCMCIA card slot 347 */ 348 struct PCMslot 349 { 350 RWlock; 351 352 Ref ref; 353 354 long memlen; /* memory length */ 355 uchar slotno; /* slot number */ 356 void *regs; /* i/o registers */ 357 void *mem; /* memory */ 358 void *attr; /* attribute memory */ 359 360 /* status */ 361 uchar occupied; /* card in the slot */ 362 uchar configed; /* card configured */ 363 uchar busy; 364 uchar powered; 365 uchar battery; 366 uchar wrprot; 367 uchar enabled; 368 uchar special; 369 uchar dsize; 370 371 /* cis info */ 372 int cisread; /* set when the cis has been read */ 373 char verstr[512]; /* version string */ 374 uchar cpresent; /* config registers present */ 375 ulong caddr; /* relative address of config registers */ 376 int nctab; /* number of config table entries */ 377 PCMconftab ctab[8]; 378 PCMconftab *def; /* default conftab */ 379 380 /* maps are fixed */ 381 PCMmap memmap; 382 PCMmap attrmap; 383 }; 384