1 /* $NetBSD: pxa2x0_rtc.c,v 1.8 2024/02/24 12:04:16 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2007 NONAKA Kimihiro <nonaka@netbsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 */
23
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_rtc.c,v 1.8 2024/02/24 12:04:16 andvar Exp $");
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/device.h>
30 #include <sys/kernel.h>
31
32 #include <dev/clock_subr.h>
33
34 #include <sys/bus.h>
35
36 #include <arm/xscale/pxa2x0cpu.h>
37 #include <arm/xscale/pxa2x0reg.h>
38 #include <arm/xscale/pxa2x0var.h>
39
40 #ifdef PXARTC_DEBUG
41 #define DPRINTF(s) printf s
42 #else
43 #define DPRINTF(s)
44 #endif
45
46 struct pxartc_softc {
47 device_t sc_dev;
48 bus_space_tag_t sc_iot;
49 bus_space_handle_t sc_ioh;
50
51 struct todr_chip_handle sc_todr;
52
53 int sc_flags;
54 #define FLAG_WRISTWATCH (1 << 0)
55 };
56
57 static int pxartc_match(device_t, cfdata_t, void *);
58 static void pxartc_attach(device_t, device_t, void *);
59
60 CFATTACH_DECL_NEW(pxartc, sizeof(struct pxartc_softc),
61 pxartc_match, pxartc_attach, NULL, NULL);
62
63 /* todr(9) interface */
64 static int pxartc_todr_gettime(todr_chip_handle_t, struct timeval *);
65 static int pxartc_todr_settime(todr_chip_handle_t, struct timeval *);
66 static int pxartc_wristwatch_gettime(todr_chip_handle_t, struct clock_ymdhms *);
67 static int pxartc_wristwatch_settime(todr_chip_handle_t, struct clock_ymdhms *);
68
69 static int
pxartc_match(device_t parent,cfdata_t cf,void * aux)70 pxartc_match(device_t parent, cfdata_t cf, void *aux)
71 {
72 struct pxaip_attach_args *pxa = aux;
73
74 if (strcmp(pxa->pxa_name, cf->cf_name) != 0)
75 return 0;
76
77 if (pxa->pxa_size == 0) {
78 pxa->pxa_size =
79 CPU_IS_PXA270 ? PXA270_RTC_SIZE : PXA250_RTC_SIZE;
80 }
81 return 1;
82 }
83
84 static void
pxartc_attach(device_t parent,device_t self,void * aux)85 pxartc_attach(device_t parent, device_t self, void *aux)
86 {
87 struct pxartc_softc *sc = device_private(self);
88 struct pxaip_attach_args *pxa = aux;
89
90 sc->sc_dev = self;
91 sc->sc_iot = pxa->pxa_iot;
92
93 aprint_normal(": Real-time Clock\n");
94
95 if (bus_space_map(sc->sc_iot, pxa->pxa_addr, pxa->pxa_size, 0,
96 &sc->sc_ioh)) {
97 aprint_error("%s: couldn't map registers\n",
98 device_xname(sc->sc_dev));
99 return;
100 }
101
102 memset(&sc->sc_todr, 0, sizeof(sc->sc_todr));
103 sc->sc_todr.cookie = sc;
104 if (pxa->pxa_size == PXA270_RTC_SIZE) {
105 aprint_normal("%s: using wristwatch register\n",
106 device_xname(sc->sc_dev));
107 sc->sc_flags |= FLAG_WRISTWATCH;
108 sc->sc_todr.todr_gettime_ymdhms = pxartc_wristwatch_gettime;
109 sc->sc_todr.todr_settime_ymdhms = pxartc_wristwatch_settime;
110 } else {
111 sc->sc_todr.todr_gettime = pxartc_todr_gettime;
112 sc->sc_todr.todr_settime = pxartc_todr_settime;
113 }
114
115 todr_attach(&sc->sc_todr);
116 }
117
118 static int
pxartc_todr_gettime(todr_chip_handle_t ch,struct timeval * tv)119 pxartc_todr_gettime(todr_chip_handle_t ch, struct timeval *tv)
120 {
121 struct pxartc_softc *sc = ch->cookie;
122
123 tv->tv_sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR);
124 tv->tv_usec = 0;
125 #ifdef PXARTC_DEBUG
126 struct clock_ymdhms dt;
127 DPRINTF(("%s: RCNR = %08llx\n", device_xname(sc->sc_dev),
128 tv->tv_sec));
129 clock_secs_to_ymdhms(tv->tv_sec, &dt);
130 DPRINTF(("%s: %02lld/%02d/%02d %02d:%02d:%02d\n",
131 device_xname(sc->sc_dev),
132 dt.dt_year, dt.dt_mon, dt.dt_day,
133 dt.dt_hour, dt.dt_min, dt.dt_sec));
134 #endif
135 return 0;
136 }
137
138 static int
pxartc_todr_settime(todr_chip_handle_t ch,struct timeval * tv)139 pxartc_todr_settime(todr_chip_handle_t ch, struct timeval *tv)
140 {
141 struct pxartc_softc *sc = ch->cookie;
142
143 #ifdef PXARTC_DEBUG
144 struct clock_ymdhms dt;
145 DPRINTF(("%s: RCNR = %08llx\n", device_xname(sc->sc_dev),
146 tv->tv_sec));
147 clock_secs_to_ymdhms(tv->tv_sec, &dt);
148 DPRINTF(("%s: %02lld/%02d/%02d %02d:%02d:%02d\n",
149 device_xname(sc->sc_dev),
150 dt.dt_year, dt.dt_mon, dt.dt_day,
151 dt.dt_hour, dt.dt_min, dt.dt_sec));
152 #endif
153 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR, tv->tv_sec);
154 #ifdef PXARTC_DEBUG
155 {
156 uint32_t cntr;
157 delay(1);
158 cntr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR);
159 DPRINTF(("%s: new RCNR = %08x\n", device_xname(sc->sc_dev),
160 cntr));
161 clock_secs_to_ymdhms(cntr, &dt);
162 DPRINTF(("%s: %02lld/%02d/%02d %02d:%02d:%02d\n",
163 device_xname(sc->sc_dev),
164 dt.dt_year, dt.dt_mon, dt.dt_day,
165 dt.dt_hour, dt.dt_min, dt.dt_sec));
166 }
167 #endif
168 return 0;
169 }
170
171 static int
pxartc_wristwatch_gettime(todr_chip_handle_t ch,struct clock_ymdhms * dt)172 pxartc_wristwatch_gettime(todr_chip_handle_t ch, struct clock_ymdhms *dt)
173 {
174 struct pxartc_softc *sc = ch->cookie;
175 uint32_t dayr, yearr;
176 int s;
177
178 DPRINTF(("%s: pxartc_wristwatch_gettime()\n",
179 device_xname(sc->sc_dev)));
180
181 s = splhigh();
182 dayr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR);
183 yearr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR);
184 splx(s);
185
186 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", device_xname(sc->sc_dev),
187 dayr, yearr));
188
189 dt->dt_sec = (dayr >> RDCR_SECOND_SHIFT) & RDCR_SECOND_MASK;
190 dt->dt_min = (dayr >> RDCR_MINUTE_SHIFT) & RDCR_MINUTE_MASK;
191 dt->dt_hour = (dayr >> RDCR_HOUR_SHIFT) & RDCR_HOUR_MASK;
192 dt->dt_day = (yearr >> RYCR_DOM_SHIFT) & RYCR_DOM_MASK;
193 dt->dt_mon = (yearr >> RYCR_MONTH_SHIFT) & RYCR_MONTH_MASK;
194 dt->dt_year = (yearr >> RYCR_YEAR_SHIFT) & RYCR_YEAR_MASK;
195
196 DPRINTF(("%s: %02lld/%02d/%02d %02d:%02d:%02d\n",
197 device_xname(sc->sc_dev),
198 dt->dt_year, dt->dt_mon, dt->dt_day,
199 dt->dt_hour, dt->dt_min, dt->dt_sec));
200
201 return 0;
202 }
203
204 static int
pxartc_wristwatch_settime(todr_chip_handle_t ch,struct clock_ymdhms * dt)205 pxartc_wristwatch_settime(todr_chip_handle_t ch, struct clock_ymdhms *dt)
206 {
207 struct pxartc_softc *sc = ch->cookie;
208 uint32_t dayr, yearr;
209 uint32_t wom; /* week of month: 1=first week of month */
210 int s;
211
212 DPRINTF(("%s: pxartc_wristwatch_settime()\n",
213 device_xname(sc->sc_dev)));
214
215 DPRINTF(("%s: %02lld/%02d/%02d %02d:%02d:%02d\n",
216 device_xname(sc->sc_dev),
217 dt->dt_year, dt->dt_mon, dt->dt_day,
218 dt->dt_hour, dt->dt_min, dt->dt_sec));
219
220 dayr = (dt->dt_sec & RDCR_SECOND_MASK) << RDCR_SECOND_SHIFT;
221 dayr |= (dt->dt_min & RDCR_MINUTE_MASK) << RDCR_MINUTE_SHIFT;
222 dayr |= (dt->dt_hour & RDCR_HOUR_MASK) << RDCR_HOUR_SHIFT;
223 dayr |= ((dt->dt_wday + 1) & RDCR_DOW_MASK) << RDCR_DOW_SHIFT;
224 wom = ((dt->dt_day - 1 + 6 - dt->dt_wday) / 7) + 1;
225 dayr |= (wom & RDCR_WOM_MASK) << RDCR_WOM_SHIFT;
226 yearr = (dt->dt_day & RYCR_DOM_MASK) << RYCR_DOM_SHIFT;
227 yearr |= (dt->dt_mon & RYCR_MONTH_MASK) << RYCR_MONTH_SHIFT;
228 yearr |= (dt->dt_year & RYCR_YEAR_MASK) << RYCR_YEAR_SHIFT;
229
230 DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", device_xname(sc->sc_dev),
231 dayr, yearr));
232
233 /*
234 * We must write RYCR register before write RDCR register.
235 *
236 * See PXA270 Processor Family Developer's Manual p.946
237 * 21.4.2.3.1 Writing RDCR and RYCR Counter Registers with Valid Data.
238 */
239 s = splhigh();
240 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR, yearr);
241 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR, dayr);
242 splx(s);
243
244 #ifdef PXARTC_DEBUG
245 {
246 struct clock_ymdhms dummy;
247 pxartc_wristwatch_gettime(ch, &dummy);
248 }
249 #endif
250
251 return 0;
252 }
253