1/* $NetBSD: prom_swpal.S,v 1.2 1997/04/06 08:41:01 cgd Exp $ */ 2 3/* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30#include "../../include/asm.h" 31#include "../../include/prom.h" 32#include "../../include/rpb.h" 33 34/* Offsets from base of HWRPB. */ 35#define RPB_SELFREF 0x00 36#define RPB_SLOTSIZE 0x98 37#define RPB_PERCPU_OFF 0xA0 38 39/* Offsets in a boot PCB. */ 40#define PCB_KSP 0x00 41#define PCB_PTBR 0x10 42#define PCB_ASN 0x1c 43#define PCB_FEN 0x28 44 45/* Pal values. */ 46#define PAL_RESERVED 0 /* Reserved to Digital. */ 47#define PAL_VMS 1 /* VMS */ 48#define PAL_OSF 2 /* OSF */ 49 50/* 51 * PAL code switch routine. 52 */ 53#define D_RA (7*8) 54#define D_S0 (8*8) 55#define D_S1 (9*8) 56#define D_S2 (10*8) 57#define D_S3 (11*8) 58#define D_S4 (12*8) 59#define D_S5 (13*8) 60#define PALSW_FRAME_SIZE (14*8) 61#define PALSW_REGS IM_RA|IM_S0|IM_S1|IM_S2|IM_S3|IM_S4|IM_S5 62 63 .comm ptbr_save,8 64 65 .text 66 .align 4 67 68NESTED(switch_palcode, 0, PALSW_FRAME_SIZE, ra, PALSW_REGS, 0) 69 LDGP(pv) 70/* ldgp gp, 0(pv)*/ 71 72 lda sp, -PALSW_FRAME_SIZE(sp) 73 stq ra, D_RA(sp) 74 stq s0, D_S0(sp) 75 stq s1, D_S1(sp) 76 stq s2, D_S2(sp) 77 stq s3, D_S3(sp) 78 stq s4, D_S4(sp) 79 stq s5, D_S5(sp) 80 81 stq pv, 0(sp) 82 stq gp, 8(sp) 83 84 ldiq s0, HWRPB_ADDR /* s0 HWRPB_ADDR */ 85 ldq s1, RPB_SLOTSIZE(s0) 86 call_pal PAL_VMS_mfpr_whami 87 mulq s1, v0, s1 /* s1 per_cpu offset from base */ 88 ldq s2, RPB_PERCPU_OFF(s0) 89 addq s0, s2, s2 90 addq s2, s1, s2 /* s2 PCB (virtual) */ 91 92 call_pal PAL_VMS_mfpr_ptbr 93 stq v0, PCB_PTBR(s2) 94 stq v0, ptbr_save /* save PTBR for the kernel */ 95 stl zero, PCB_ASN(s2) 96 stq zero, PCB_FEN(s2) 97 stq sp, PCB_KSP(s2) 98 99 ldq t0, RPB_SELFREF(s0) /* HWRBP base (physical) */ 100 ldq t1, RPB_PERCPU_OFF(s0) 101 addq t0, t1, t0 102 addq t0, s1, t0 /* PCB base (phys) */ 103 stq t0, 16(sp) 104 105 call_pal PAL_VMS_mfpr_vptb 106 mov v0, a3 107 ldiq a0, PAL_OSF 108 lda a1, contin 109 ldq a2, 16(sp) 110 111 call_pal PAL_swppal /* a0, a1, a2, a3 */ 112 113contin: ldq pv, 0(sp) 114 ldq gp, 8(sp) 115 116 ldq ra, D_RA(sp) 117 ldq s0, D_S0(sp) 118 ldq s1, D_S1(sp) 119 ldq s2, D_S2(sp) 120 ldq s3, D_S3(sp) 121 ldq s4, D_S4(sp) 122 ldq s5, D_S5(sp) 123 lda sp, PALSW_FRAME_SIZE(sp) 124 RET 125END(switch_palcode) 126 127#undef D_RA 128#undef D_S0 129#undef D_S1 130#undef D_S2 131#undef D_S3 132#undef D_S4 133#undef D_S5 134#undef PALSW_FRAME_SIZE 135#undef PALSW_REGS 136