xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/polaris10_smumgr.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: polaris10_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2015 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #ifndef _POLARIS10_SMUMANAGER_H
27 #define _POLARIS10_SMUMANAGER_H
28 
29 
30 #include <pp_endian.h>
31 #include "smu74.h"
32 #include "smu74_discrete.h"
33 #include "smu7_smumgr.h"
34 
35 #define SMC_RAM_END 0x40000
36 
37 struct polaris10_pt_defaults {
38 	uint8_t   SviLoadLineEn;
39 	uint8_t   SviLoadLineVddC;
40 	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
41 	uint8_t   TDC_MAWt;
42 	uint8_t   TdcWaterfallCtl;
43 	uint8_t   DTEAmbientTempBase;
44 
45 	uint32_t  DisplayCac;
46 	uint32_t  BAPM_TEMP_GRADIENT;
47 	uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
48 	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
49 };
50 
51 struct polaris10_range_table {
52 	uint32_t trans_lower_frequency; /* in 10khz */
53 	uint32_t trans_upper_frequency;
54 };
55 
56 struct polaris10_smumgr {
57 	struct smu7_smumgr smu7_data;
58 	uint8_t protected_mode;
59 	SMU74_Discrete_DpmTable              smc_state_table;
60 	struct SMU74_Discrete_Ulv            ulv_setting;
61 	struct SMU74_Discrete_PmFuses  power_tune_table;
62 	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
63 	const struct polaris10_pt_defaults       *power_tune_defaults;
64 	uint32_t               bif_sclk_table[SMU74_MAX_LEVELS_LINK];
65 };
66 
67 
68 #endif
69