1 /* $NetBSD: p_sni_rm200pci.c,v 1.16 2020/06/13 20:01:27 ad Exp $ */
2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
3
4 /*
5 * Copyright (c) 1988 University of Utah.
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department, The Mach Operating System project at
12 * Carnegie-Mellon University and Ralph Campbell.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
39 */
40
41 #define __INTR_PRIVATE
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: p_sni_rm200pci.c,v 1.16 2020/06/13 20:01:27 ad Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/device.h>
48 #include <sys/intr.h>
49 #include <sys/bus.h>
50
51 #include <uvm/uvm_extern.h>
52
53 #include <machine/autoconf.h>
54 #include <machine/pio.h>
55 #include <machine/platform.h>
56 #include <machine/wired_map.h>
57
58 #include <mips/pte.h>
59
60 void p_sni_rm200pci_init(void);
61 void p_sni_rm200pci_cons_init(void);
62
63 #include "com.h"
64 #if NCOM > 0
65 #include <sys/termios.h>
66 #include <dev/ic/comreg.h>
67 #include <dev/ic/comvar.h>
68 #endif
69
70 struct platform platform_sni_rm200pci = {
71 "RM200PCI",
72 NULL, /* unknown */
73 "",
74 "RM200",
75 "Siemens Nixdorf",
76 150, /* MHz ?? */
77 NULL, /* XXX */
78 platform_generic_match,
79 p_sni_rm200pci_init,
80 p_sni_rm200pci_cons_init,
81 platform_nop, /* reset */
82 arc_set_intr, /* ??? */
83 };
84
85 /*
86 * This is a mask of bits to clear in the SR when we go to a
87 * given interrupt priority level.
88 */
89 /* XXX lack of hardware info for sni_rm200pci */
90 static const struct ipl_sr_map sni_rm200pci_ipl_sr_map = {
91 .sr_bits = {
92 [IPL_NONE] = 0,
93 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
94 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
95 [IPL_VM] = MIPS_INT_MASK, /* XXX */
96 [IPL_SCHED] = MIPS_INT_MASK,
97 [IPL_DDB] = MIPS_INT_MASK,
98 [IPL_HIGH] = MIPS_INT_MASK,
99 },
100 };
101
102 /*
103 * critial i/o space, interrupt, and other chipset related initialization.
104 */
105 void
p_sni_rm200pci_init(void)106 p_sni_rm200pci_init(void)
107 {
108
109 /*
110 * Initialize wired TLB for I/O space which is used on early stage
111 */
112
113 /*
114 * Initialize interrupt priority
115 */
116 ipl_sr_map = sni_rm200pci_ipl_sr_map;
117
118 /*
119 * Initialize I/O address offset
120 */
121 arc_init_wired_map();
122 #if 0
123 arc_bus_space_init(&arc_bus_io, "rm200isaio",
124 RM200_P_ISA_IO, RM200_V_ISA_IO, 0, RM200_S_ISA_IO);
125 arc_bus_space_init(&arc_bus_mem, "rm200isamem",
126 RM200_P_ISA_MEM, RM200_V_ISA_MEM, 0, RM200_S_ISA_MEM);
127 #endif
128 }
129
130 void
p_sni_rm200pci_cons_init(void)131 p_sni_rm200pci_cons_init(void)
132 {
133
134 if (!com_console) {
135 /* XXX For now... */
136 }
137 if (com_console_address == 0) {
138 #if 0 /* XXX */
139 com_console_address = xxx;
140 #else
141 panic("console address unknown");
142 #endif
143 }
144 comcnattach(&arc_bus_io /* XXX? */, com_console_address,
145 com_console_speed, com_freq, COM_TYPE_NORMAL, com_console_mode);
146 }
147