1 /* $NetBSD: p_dti_arcstation.c,v 1.20 2020/11/18 02:14:13 thorpej Exp $ */
2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
3
4 /*
5 * Copyright (c) 1988 University of Utah.
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department, The Mach Operating System project at
12 * Carnegie-Mellon University and Ralph Campbell.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
39 */
40
41 #include <sys/cdefs.h>
42 __KERNEL_RCSID(0, "$NetBSD: p_dti_arcstation.c,v 1.20 2020/11/18 02:14:13 thorpej Exp $");
43
44 #define __INTR_PRIVATE
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/device.h>
48 #include <sys/intr.h>
49
50 #include <uvm/uvm_extern.h>
51
52 #include <machine/autoconf.h>
53 #include <sys/bus.h>
54 #include <machine/pio.h>
55 #include <machine/platform.h>
56 #include <machine/wired_map.h>
57
58 #include <dev/isa/isareg.h>
59 #include <dev/isa/isavar.h>
60 #include <dev/ic/i8042reg.h>
61
62 #include <arc/dti/desktech.h>
63
64 void arc_sysreset(bus_addr_t, bus_size_t);
65
66 #include "pc.h"
67 #if NPC_ISA > 0 || NOPMS_ISA > 0
68 #include <arc/dev/pcconsvar.h>
69 #include <arc/isa/pccons_isavar.h>
70 #endif
71
72 #include "btl.h"
73 #if NBTL > 0
74 #include <arc/dti/btlvar.h>
75 #endif
76
77 const char *p_dti_arcstation_mainbusdevs[] = {
78 "arcsisabr",
79 NULL,
80 };
81
82 void p_dti_arcstation_init(void);
83 void p_dti_arcstation_cons_init(void);
84 void p_dti_arcstation_reset(void);
85
86 struct platform platform_desktech_arcstation_i = {
87 "DESKTECH-ARCStation I",
88 NULL, /* unknown, probably "DESKTECH"? */
89 "",
90 "DeskStation rPC44",
91 "DESKTECH",
92 150, /* MHz ?? */
93 p_dti_arcstation_mainbusdevs,
94 platform_generic_match,
95 p_dti_arcstation_init,
96 c_isa_cons_init,
97 p_dti_arcstation_reset,
98 arc_set_intr,
99 };
100
101 /*
102 * This is a mask of bits to clear in the SR when we go to a
103 * given interrupt priority level.
104 */
105 /* XXX see comments in p_dti_arcstation_init() */
106 static const struct ipl_sr_map dti_arcstation_ipl_sr_map = {
107 .sr_bits = {
108 [IPL_NONE] = 0,
109 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
110 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
111 [IPL_VM] = MIPS_INT_MASK, /* XXX */
112 [IPL_SCHED] = MIPS_INT_MASK,
113 [IPL_DDB] = MIPS_INT_MASK,
114 [IPL_HIGH] = MIPS_INT_MASK,
115 },
116 };
117
118 #if NPC_ISA > 0 || NOPMS_ISA > 0
119 /*
120 * platform-dependent pccons configuration
121 */
122
123 void pccons_dti_arcstation_init(void);
124
125 struct pccons_config pccons_dti_arcstation_conf = {
126 0x3b4, 0xb0000, /* mono: iobase, memaddr */
127 0x3d4, 0xa0000, /* cga: iobase, memaddr */
128 0x64, 0x60, /* kbdc: cmdport, dataport */
129 pccons_dti_arcstation_init,
130 };
131
132 void
pccons_dti_arcstation_init(void)133 pccons_dti_arcstation_init(void)
134 {
135
136 kbc_put8042cmd(CMDBYTE); /* Want XT codes.. */
137 }
138
139 #endif /* NPC_ISA > 0 || NOPMS_ISA > 0 */
140
141 #if NBTL > 0
142 /*
143 * platform-dependent btl configuration
144 */
145
146 void btl_dti_arcstation_bouncemem(u_int *, u_int *);
147 uint32_t btl_dti_arcstation_kvtophys(uint32_t);
148 uint32_t btl_dti_arcstation_phystokv(uint32_t);
149
150 struct btl_config btl_dti_arcstation_conf = {
151 btl_dti_arcstation_bouncemem,
152 btl_dti_arcstation_kvtophys,
153 btl_dti_arcstation_phystokv,
154 };
155
156 void
btl_dti_arcstation_bouncemem(u_int * basep,u_int * sizep)157 btl_dti_arcstation_bouncemem(u_int *basep, u_int *sizep)
158 {
159 /*
160 * XXX static buffer as a kludge.
161 * DMA isn't cache coherent on the rpc44, so we always use
162 * uncached buffers for DMA.
163 */
164 static char rpc44_buffer[TYNE_S_BOUNCE];
165
166 *sizep = TYNE_S_BOUNCE; /* Good enough? XXX */
167 #if 0
168 *basep = (u_int) kmem_alloc(*sizep, KM_SLEEP);
169 #else
170 *basep = (u_int) rpc44_buffer | 0xa0000000;
171 #endif
172 }
173
174 uint32_t
btl_dti_arcstation_kvtophys(uint32_t v)175 btl_dti_arcstation_kvtophys(uint32_t v)
176 {
177
178 return v;
179 }
180
181 uint32_t
btl_dti_arcstation_phystokv(uint32_t p)182 btl_dti_arcstation_phystokv(uint32_t p)
183 {
184
185 return p;
186 }
187 #endif /* NBTL > 0 */
188
189 /*
190 * critial i/o space, interrupt, and other chipset related initialization.
191 */
192 void
p_dti_arcstation_init(void)193 p_dti_arcstation_init(void)
194 {
195
196 /*
197 * Initialize interrupt priority
198 */
199 /*
200 * XXX
201 * - rewrite spl handling to allow ISA clock > bio|tty|net
202 * or
203 * - use MIP3_INTERNAL_TIMER_INTERRUPT for clock
204 */
205 ipl_sr_map = dti_arcstation_ipl_sr_map;
206
207 /*
208 * Initialize I/O address offset
209 */
210 arc_bus_space_init(&arc_bus_io, "rpc44isaio",
211 RPC44_P_ISA_IO, RPC44_V_ISA_IO, 0, RPC44_S_ISA_IO);
212 arc_bus_space_init(&arc_bus_mem, "rpc44isamem",
213 RPC44_P_ISA_MEM, RPC44_V_ISA_MEM, 0, RPC44_S_ISA_MEM);
214
215 /*
216 * Initialize wired TLB for I/O space which is used on early stage
217 */
218 arc_init_wired_map();
219 /* no need to initialize wired TLB */
220
221 /*
222 * common configuration for DTI platforms
223 */
224 c_isa_init();
225
226 #if NPC_ISA > 0 || NOPMS_ISA > 0
227 /* platform-dependent pccons configuration */
228 pccons_isa_conf = &pccons_dti_arcstation_conf;
229 #endif
230
231 #if NBTL > 0
232 /* platform-dependent btl configuration */
233 btl_conf = &btl_dti_arcstation_conf;
234 #endif
235 }
236
237 void
p_dti_arcstation_reset(void)238 p_dti_arcstation_reset(void)
239 {
240
241 arc_sysreset(RPC44_V_ISA_IO + IO_KBD, KBCMDP);
242 }
243