1 /* $NetBSD: oss_3_0_sh_mask.h,v 1.3 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * OSS_3_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef OSS_3_0_SH_MASK_H 27 #define OSS_3_0_SH_MASK_H 28 29 #define IH_VMID_0_LUT__PASID_MASK 0xffff 30 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_1_LUT__PASID_MASK 0xffff 32 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_2_LUT__PASID_MASK 0xffff 34 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 35 #define IH_VMID_3_LUT__PASID_MASK 0xffff 36 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 37 #define IH_VMID_4_LUT__PASID_MASK 0xffff 38 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 39 #define IH_VMID_5_LUT__PASID_MASK 0xffff 40 #define IH_VMID_5_LUT__PASID__SHIFT 0x0 41 #define IH_VMID_6_LUT__PASID_MASK 0xffff 42 #define IH_VMID_6_LUT__PASID__SHIFT 0x0 43 #define IH_VMID_7_LUT__PASID_MASK 0xffff 44 #define IH_VMID_7_LUT__PASID__SHIFT 0x0 45 #define IH_VMID_8_LUT__PASID_MASK 0xffff 46 #define IH_VMID_8_LUT__PASID__SHIFT 0x0 47 #define IH_VMID_9_LUT__PASID_MASK 0xffff 48 #define IH_VMID_9_LUT__PASID__SHIFT 0x0 49 #define IH_VMID_10_LUT__PASID_MASK 0xffff 50 #define IH_VMID_10_LUT__PASID__SHIFT 0x0 51 #define IH_VMID_11_LUT__PASID_MASK 0xffff 52 #define IH_VMID_11_LUT__PASID__SHIFT 0x0 53 #define IH_VMID_12_LUT__PASID_MASK 0xffff 54 #define IH_VMID_12_LUT__PASID__SHIFT 0x0 55 #define IH_VMID_13_LUT__PASID_MASK 0xffff 56 #define IH_VMID_13_LUT__PASID__SHIFT 0x0 57 #define IH_VMID_14_LUT__PASID_MASK 0xffff 58 #define IH_VMID_14_LUT__PASID__SHIFT 0x0 59 #define IH_VMID_15_LUT__PASID_MASK 0xffff 60 #define IH_VMID_15_LUT__PASID__SHIFT 0x0 61 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1 62 #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 63 #define IH_RB_CNTL__RB_SIZE_MASK 0x3e 64 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 65 #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 66 #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 67 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 68 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 69 #define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000 70 #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 71 #define IH_RB_CNTL__MC_SWAP_MASK 0xc0000 72 #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 73 #define IH_RB_CNTL__RPTR_REARM_MASK 0x200000 74 #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 75 #define IH_RB_CNTL__MC_VMID_MASK 0xf000000 76 #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 77 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 78 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 79 #define IH_RB_BASE__ADDR_MASK 0xffffffff 80 #define IH_RB_BASE__ADDR__SHIFT 0x0 81 #define IH_RB_RPTR__OFFSET_MASK 0x3fffc 82 #define IH_RB_RPTR__OFFSET__SHIFT 0x2 83 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 84 #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 85 #define IH_RB_WPTR__OFFSET_MASK 0x3fffc 86 #define IH_RB_WPTR__OFFSET__SHIFT 0x2 87 #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 88 #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 89 #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 90 #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 91 #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff 92 #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 93 #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc 94 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 95 #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f 96 #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 97 #define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 98 #define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 99 #define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 100 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa 101 #define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 102 #define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf 103 #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 104 #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 105 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 106 #define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 107 #define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 108 #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 109 #define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 110 #define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 111 #define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 112 #define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 113 #define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 114 #define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 115 #define IH_STATUS__IDLE_MASK 0x1 116 #define IH_STATUS__IDLE__SHIFT 0x0 117 #define IH_STATUS__INPUT_IDLE_MASK 0x2 118 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 119 #define IH_STATUS__RB_IDLE_MASK 0x4 120 #define IH_STATUS__RB_IDLE__SHIFT 0x2 121 #define IH_STATUS__RB_FULL_MASK 0x8 122 #define IH_STATUS__RB_FULL__SHIFT 0x3 123 #define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 124 #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 125 #define IH_STATUS__RB_OVERFLOW_MASK 0x20 126 #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 127 #define IH_STATUS__MC_WR_IDLE_MASK 0x40 128 #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 129 #define IH_STATUS__MC_WR_STALL_MASK 0x80 130 #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 131 #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 132 #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 133 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 134 #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 135 #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 136 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 137 #define IH_STATUS__SWITCH_READY_MASK 0x800 138 #define IH_STATUS__SWITCH_READY__SHIFT 0xb 139 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 140 #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 141 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 142 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 143 #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc 144 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 145 #define IH_PERFMON_CNTL__ENABLE1_MASK 0x400 146 #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa 147 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x800 148 #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb 149 #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 150 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 151 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 152 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 153 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 154 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 155 #define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1 156 #define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0 157 #define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2 158 #define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1 159 #define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4 160 #define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2 161 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff 162 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 163 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff 164 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 165 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff 166 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 167 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 168 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 169 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2 170 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 171 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 172 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 173 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 174 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 175 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 176 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 177 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 178 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 179 #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff 180 #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 181 #define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff 182 #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 183 #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000 184 #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 185 #define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000 186 #define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e 187 #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf 188 #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 189 #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 190 #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 191 #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 192 #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 193 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff 194 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 195 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000 196 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 197 #define IH_VF_ENABLE__VALUE_MASK 0x1 198 #define IH_VF_ENABLE__VALUE__SHIFT 0x0 199 #define IH_VIRT_RESET_REQ__VF_MASK 0xffff 200 #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 201 #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000 202 #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 203 #define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff 204 #define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0 205 #define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000 206 #define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 207 #define IH_VERSION__VALUE_MASK 0xfff 208 #define IH_VERSION__VALUE__SHIFT 0x0 209 #define IH_LEVEL_INTR_MASK__MASK_MASK 0x1 210 #define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0 211 #define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1 212 #define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0 213 #define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2 214 #define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1 215 #define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8 216 #define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3 217 #define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10 218 #define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4 219 #define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20 220 #define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5 221 #define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40 222 #define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6 223 #define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80 224 #define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7 225 #define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100 226 #define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8 227 #define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200 228 #define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9 229 #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400 230 #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa 231 #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800 232 #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb 233 #define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000 234 #define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc 235 #define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000 236 #define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd 237 #define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000 238 #define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe 239 #define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000 240 #define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf 241 #define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000 242 #define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10 243 #define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000 244 #define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11 245 #define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000 246 #define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12 247 #define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000 248 #define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13 249 #define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000 250 #define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14 251 #define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000 252 #define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15 253 #define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000 254 #define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16 255 #define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000 256 #define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18 257 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1 258 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0 259 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2 260 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1 261 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8 262 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3 263 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10 264 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4 265 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20 266 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5 267 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40 268 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6 269 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80 270 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7 271 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100 272 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8 273 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200 274 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9 275 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400 276 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa 277 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800 278 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb 279 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000 280 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc 281 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000 282 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd 283 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000 284 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe 285 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000 286 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf 287 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000 288 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10 289 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000 290 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11 291 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000 292 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12 293 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000 294 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13 295 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000 296 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14 297 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000 298 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15 299 #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 300 #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 301 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc 302 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 303 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 304 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 305 #define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 306 #define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 307 #define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 308 #define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 309 #define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 310 #define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 311 #define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 312 #define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 313 #define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 314 #define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 315 #define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 316 #define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 317 #define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 318 #define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 319 #define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 320 #define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 321 #define SEM_VF_ENABLE__VALUE_MASK 0x1 322 #define SEM_VF_ENABLE__VALUE__SHIFT 0x0 323 #define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00 324 #define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8 325 #define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000 326 #define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10 327 #define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf 328 #define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 329 #define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 330 #define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 331 #define SEM_VIRT_RESET_REQ__VF_MASK 0xffff 332 #define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 333 #define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 334 #define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 335 #define SEM_STATUS__SEM_IDLE_MASK 0x1 336 #define SEM_STATUS__SEM_IDLE__SHIFT 0x0 337 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 338 #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 339 #define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 340 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 341 #define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 342 #define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 343 #define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 344 #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 345 #define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 346 #define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 347 #define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 348 #define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 349 #define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 350 #define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 351 #define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 352 #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 353 #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 354 #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 355 #define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 356 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 357 #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 358 #define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 359 #define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 360 #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 361 #define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 362 #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 363 #define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 364 #define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 365 #define SEM_STATUS__SWITCH_READY_MASK 0x80000000 366 #define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 367 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 368 #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 369 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 370 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 371 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 372 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 373 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 374 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 375 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 376 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 377 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 378 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 379 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 380 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 381 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 382 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 383 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 384 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 385 #define SEM_MAILBOX__SIDEPORT_MASK 0xff 386 #define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 387 #define SEM_MAILBOX__HOSTPORT_MASK 0xff00 388 #define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 389 #define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 390 #define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 391 #define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 392 #define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 393 #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff 394 #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 395 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 396 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 397 #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 398 #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 399 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 400 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 401 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 402 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 403 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 404 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 405 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 406 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 407 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 408 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 409 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 410 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 411 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f 412 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 413 #define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 414 #define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 415 #define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 416 #define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 417 #define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 418 #define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 419 #define SRBM_GFX_CNTL__PIPEID_MASK 0x3 420 #define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 421 #define SRBM_GFX_CNTL__MEID_MASK 0xc 422 #define SRBM_GFX_CNTL__MEID__SHIFT 0x2 423 #define SRBM_GFX_CNTL__VMID_MASK 0xf0 424 #define SRBM_GFX_CNTL__VMID__SHIFT 0x4 425 #define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 426 #define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 427 #define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff 428 #define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 429 #define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 430 #define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 431 #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 432 #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 433 #define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 434 #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 435 #define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 436 #define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 437 #define SRBM_STATUS2__VP8_BUSY_MASK 0x10 438 #define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 439 #define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 440 #define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 441 #define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 442 #define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 443 #define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 444 #define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 445 #define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 446 #define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 447 #define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 448 #define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 449 #define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 450 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa 451 #define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 452 #define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb 453 #define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 454 #define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc 455 #define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 456 #define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd 457 #define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 458 #define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe 459 #define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 460 #define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf 461 #define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 462 #define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 463 #define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 464 #define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 465 #define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 466 #define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 467 #define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 468 #define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 469 #define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 470 #define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 471 #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 472 #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 473 #define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 474 #define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 475 #define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 476 #define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 477 #define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 478 #define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 479 #define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 480 #define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 481 #define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 482 #define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 483 #define SRBM_STATUS__VMC_BUSY_MASK 0x100 484 #define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 485 #define SRBM_STATUS__MCB_BUSY_MASK 0x200 486 #define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 487 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 488 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa 489 #define SRBM_STATUS__MCC_BUSY_MASK 0x800 490 #define SRBM_STATUS__MCC_BUSY__SHIFT 0xb 491 #define SRBM_STATUS__MCD_BUSY_MASK 0x1000 492 #define SRBM_STATUS__MCD_BUSY__SHIFT 0xc 493 #define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 494 #define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd 495 #define SRBM_STATUS__SEM_BUSY_MASK 0x4000 496 #define SRBM_STATUS__SEM_BUSY__SHIFT 0xe 497 #define SRBM_STATUS__ACP_BUSY_MASK 0x10000 498 #define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 499 #define SRBM_STATUS__IH_BUSY_MASK 0x20000 500 #define SRBM_STATUS__IH_BUSY__SHIFT 0x11 501 #define SRBM_STATUS__UVD_BUSY_MASK 0x80000 502 #define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 503 #define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 504 #define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 505 #define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 506 #define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 507 #define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 508 #define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 509 #define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 510 #define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d 511 #define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 512 #define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 513 #define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 514 #define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 515 #define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 516 #define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 517 #define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 518 #define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 519 #define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 520 #define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 521 #define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 522 #define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 523 #define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 524 #define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 525 #define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 526 #define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 527 #define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 528 #define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 529 #define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 530 #define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 531 #define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 532 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa 533 #define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 534 #define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb 535 #define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 536 #define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc 537 #define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 538 #define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd 539 #define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 540 #define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe 541 #define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 542 #define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf 543 #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 544 #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 545 #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 546 #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 547 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 548 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 549 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 550 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 551 #define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 552 #define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 553 #define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 554 #define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 555 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 556 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 557 #define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 558 #define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 559 #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 560 #define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 561 #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 562 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa 563 #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 564 #define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb 565 #define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 566 #define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc 567 #define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 568 #define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd 569 #define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 570 #define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe 571 #define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 572 #define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf 573 #define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 574 #define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 575 #define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 576 #define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 577 #define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 578 #define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 579 #define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 580 #define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 581 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 582 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 583 #define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 584 #define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 585 #define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 586 #define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 587 #define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 588 #define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 589 #define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 590 #define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 591 #define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 592 #define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 593 #define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 594 #define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a 595 #define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 596 #define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b 597 #define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 598 #define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c 599 #define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 600 #define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d 601 #define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 602 #define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e 603 #define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 604 #define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f 605 #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f 606 #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 607 #define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff 608 #define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 609 #define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff 610 #define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 611 #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff 612 #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0 613 #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000 614 #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f 615 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1 616 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0 617 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2 618 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1 619 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4 620 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2 621 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8 622 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3 623 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10 624 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4 625 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20 626 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5 627 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40 628 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6 629 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80 630 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7 631 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100 632 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8 633 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200 634 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9 635 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400 636 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa 637 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800 638 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb 639 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000 640 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc 641 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000 642 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd 643 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000 644 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe 645 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000 646 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf 647 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000 648 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10 649 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000 650 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11 651 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000 652 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12 653 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000 654 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13 655 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000 656 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14 657 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000 658 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15 659 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000 660 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16 661 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000 662 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17 663 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000 664 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18 665 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000 666 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19 667 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000 668 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a 669 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000 670 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b 671 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000 672 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c 673 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000 674 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d 675 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000 676 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e 677 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000 678 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f 679 #define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1 680 #define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0 681 #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2 682 #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1 683 #define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4 684 #define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2 685 #define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8 686 #define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3 687 #define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10 688 #define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4 689 #define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20 690 #define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5 691 #define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40 692 #define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6 693 #define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80 694 #define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7 695 #define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100 696 #define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8 697 #define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200 698 #define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9 699 #define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400 700 #define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa 701 #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800 702 #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb 703 #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000 704 #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc 705 #define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000 706 #define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd 707 #define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000 708 #define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe 709 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000 710 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf 711 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000 712 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10 713 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000 714 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11 715 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000 716 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12 717 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000 718 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13 719 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000 720 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14 721 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000 722 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15 723 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000 724 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16 725 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000 726 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17 727 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000 728 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18 729 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000 730 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19 731 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000 732 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a 733 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000 734 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b 735 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000 736 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c 737 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000 738 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d 739 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000 740 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e 741 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000 742 #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f 743 #define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 744 #define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 745 #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 746 #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 747 #define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 748 #define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 749 #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 750 #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 751 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 752 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 753 #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 754 #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 755 #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 756 #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 757 #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 758 #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 759 #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 760 #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 761 #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 762 #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 763 #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 764 #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 765 #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 766 #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 767 #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 768 #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 769 #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 770 #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 771 #define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 772 #define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 773 #define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 774 #define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 775 #define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 776 #define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 777 #define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 778 #define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 779 #define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 780 #define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 781 #define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 782 #define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 783 #define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 784 #define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 785 #define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 786 #define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 787 #define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 788 #define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 789 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 790 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 791 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 792 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 793 #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 794 #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 795 #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 796 #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 797 #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 798 #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 799 #define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 800 #define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 801 #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 802 #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 803 #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 804 #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 805 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 806 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa 807 #define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 808 #define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb 809 #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 810 #define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 811 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 812 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 813 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 814 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 815 #define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 816 #define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 817 #define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 818 #define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 819 #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 820 #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 821 #define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 822 #define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 823 #define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 824 #define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 825 #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 826 #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 827 #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 828 #define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 829 #define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 830 #define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa 831 #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 832 #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb 833 #define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 834 #define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc 835 #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 836 #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd 837 #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 838 #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe 839 #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 840 #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf 841 #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 842 #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 843 #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 844 #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 845 #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 846 #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 847 #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 848 #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 849 #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 850 #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 851 #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 852 #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 853 #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 854 #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 855 #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 856 #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 857 #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 858 #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 859 #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 860 #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 861 #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 862 #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a 863 #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 864 #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b 865 #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 866 #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c 867 #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 868 #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d 869 #define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 870 #define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e 871 #define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 872 #define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f 873 #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 874 #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 875 #define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 876 #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 877 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 878 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 879 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 880 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 881 #define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 882 #define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 883 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 884 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 885 #define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 886 #define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 887 #define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 888 #define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 889 #define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 890 #define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 891 #define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 892 #define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 893 #define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 894 #define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a 895 #define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 896 #define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b 897 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 898 #define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c 899 #define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 900 #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d 901 #define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 902 #define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 903 #define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 904 #define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 905 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 906 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 907 #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 908 #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 909 #define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 910 #define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 911 #define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 912 #define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 913 #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 914 #define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 915 #define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 916 #define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 917 #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 918 #define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 919 #define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 920 #define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 921 #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 922 #define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 923 #define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 924 #define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 925 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 926 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 927 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 928 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 929 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 930 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 931 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 932 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 933 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 934 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 935 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 936 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 937 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 938 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 939 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 940 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 941 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 942 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 943 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 944 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa 945 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 946 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb 947 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 948 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc 949 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 950 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd 951 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 952 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe 953 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 954 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf 955 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 956 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 957 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 958 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 959 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 960 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 961 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 962 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 963 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 964 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 965 #define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 966 #define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 967 #define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 968 #define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 969 #define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 970 #define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a 971 #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 972 #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b 973 #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 974 #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c 975 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc 976 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 977 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 978 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 979 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 980 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 981 #define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 982 #define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f 983 #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff 984 #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 985 #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 986 #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 987 #define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff 988 #define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 989 #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff 990 #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 991 #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 992 #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 993 #define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff 994 #define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 995 #define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 996 #define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 997 #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 998 #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 999 #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 1000 #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 1001 #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 1002 #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 1003 #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 1004 #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 1005 #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff 1006 #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 1007 #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff 1008 #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 1009 #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff 1010 #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 1011 #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff 1012 #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 1013 #define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 1014 #define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 1015 #define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 1016 #define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 1017 #define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 1018 #define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 1019 #define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1020 #define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1021 #define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1022 #define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1023 #define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1024 #define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1025 #define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1026 #define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1027 #define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1028 #define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1029 #define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1030 #define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1031 #define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1032 #define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1033 #define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1034 #define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1035 #define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 1036 #define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 1037 #define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 1038 #define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 1039 #define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 1040 #define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 1041 #define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 1042 #define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 1043 #define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 1044 #define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 1045 #define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 1046 #define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 1047 #define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1048 #define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1049 #define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1050 #define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1051 #define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1052 #define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1053 #define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1054 #define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1055 #define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1056 #define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1057 #define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1058 #define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1059 #define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1060 #define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1061 #define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1062 #define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1063 #define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 1064 #define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 1065 #define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 1066 #define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 1067 #define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 1068 #define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 1069 #define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 1070 #define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 1071 #define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 1072 #define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 1073 #define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 1074 #define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 1075 #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1076 #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1077 #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1078 #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1079 #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1080 #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1081 #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1082 #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1083 #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1084 #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1085 #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1086 #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1087 #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1088 #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1089 #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1090 #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1091 #define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1092 #define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1093 #define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1094 #define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1095 #define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1096 #define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1097 #define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1098 #define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1099 #define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1100 #define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1101 #define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1102 #define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1103 #define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1104 #define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1105 #define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1106 #define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1107 #define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1108 #define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1109 #define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1110 #define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1111 #define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1112 #define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1113 #define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1114 #define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1115 #define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1116 #define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1117 #define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1118 #define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1119 #define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1120 #define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1121 #define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1122 #define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1123 #define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1124 #define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1125 #define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1126 #define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1127 #define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1128 #define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1129 #define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1130 #define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1131 #define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1132 #define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1133 #define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1134 #define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1135 #define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1136 #define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1137 #define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1138 #define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1139 #define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1140 #define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1141 #define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1142 #define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1143 #define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf 1144 #define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 1145 #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff 1146 #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 1147 #define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 1148 #define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 1149 #define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 1150 #define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 1151 #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 1152 #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d 1153 #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 1154 #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 1155 #define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 1156 #define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f 1157 #define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf 1158 #define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 1159 #define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 1160 #define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 1161 #define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc 1162 #define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 1163 #define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 1164 #define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 1165 #define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 1166 #define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 1167 #define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 1168 #define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 1169 #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 1170 #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 1171 #define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff 1172 #define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 1173 #define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 1174 #define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f 1175 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0 1176 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4 1177 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 1178 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 1179 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 1180 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 1181 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 1182 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c 1183 #define DH_TEST__DH_TEST_MASK 0x1 1184 #define DH_TEST__DH_TEST__SHIFT 0x0 1185 #define KHFS0__RESERVED_MASK 0xffffffff 1186 #define KHFS0__RESERVED__SHIFT 0x0 1187 #define KHFS1__RESERVED_MASK 0xffffffff 1188 #define KHFS1__RESERVED__SHIFT 0x0 1189 #define KHFS2__RESERVED_MASK 0xffffffff 1190 #define KHFS2__RESERVED__SHIFT 0x0 1191 #define KHFS3__RESERVED_MASK 0xffffffff 1192 #define KHFS3__RESERVED__SHIFT 0x0 1193 #define KSESSION0__RESERVED_MASK 0xffffffff 1194 #define KSESSION0__RESERVED__SHIFT 0x0 1195 #define KSESSION1__RESERVED_MASK 0xffffffff 1196 #define KSESSION1__RESERVED__SHIFT 0x0 1197 #define KSESSION2__RESERVED_MASK 0xffffffff 1198 #define KSESSION2__RESERVED__SHIFT 0x0 1199 #define KSESSION3__RESERVED_MASK 0xffffffff 1200 #define KSESSION3__RESERVED__SHIFT 0x0 1201 #define KSIG0__RESERVED_MASK 0xffffffff 1202 #define KSIG0__RESERVED__SHIFT 0x0 1203 #define KSIG1__RESERVED_MASK 0xffffffff 1204 #define KSIG1__RESERVED__SHIFT 0x0 1205 #define KSIG2__RESERVED_MASK 0xffffffff 1206 #define KSIG2__RESERVED__SHIFT 0x0 1207 #define KSIG3__RESERVED_MASK 0xffffffff 1208 #define KSIG3__RESERVED__SHIFT 0x0 1209 #define EXP0__RESERVED_MASK 0xffffffff 1210 #define EXP0__RESERVED__SHIFT 0x0 1211 #define EXP1__RESERVED_MASK 0xffffffff 1212 #define EXP1__RESERVED__SHIFT 0x0 1213 #define EXP2__RESERVED_MASK 0xffffffff 1214 #define EXP2__RESERVED__SHIFT 0x0 1215 #define EXP3__RESERVED_MASK 0xffffffff 1216 #define EXP3__RESERVED__SHIFT 0x0 1217 #define EXP4__RESERVED_MASK 0xffffffff 1218 #define EXP4__RESERVED__SHIFT 0x0 1219 #define EXP5__RESERVED_MASK 0xffffffff 1220 #define EXP5__RESERVED__SHIFT 0x0 1221 #define EXP6__RESERVED_MASK 0xffffffff 1222 #define EXP6__RESERVED__SHIFT 0x0 1223 #define EXP7__RESERVED_MASK 0xffffffff 1224 #define EXP7__RESERVED__SHIFT 0x0 1225 #define LX0__RESERVED_MASK 0xffffffff 1226 #define LX0__RESERVED__SHIFT 0x0 1227 #define LX1__RESERVED_MASK 0xffffffff 1228 #define LX1__RESERVED__SHIFT 0x0 1229 #define LX2__RESERVED_MASK 0xffffffff 1230 #define LX2__RESERVED__SHIFT 0x0 1231 #define LX3__RESERVED_MASK 0xffffffff 1232 #define LX3__RESERVED__SHIFT 0x0 1233 #define CLIENT2_K0__RESERVED_MASK 0xffffffff 1234 #define CLIENT2_K0__RESERVED__SHIFT 0x0 1235 #define CLIENT2_K1__RESERVED_MASK 0xffffffff 1236 #define CLIENT2_K1__RESERVED__SHIFT 0x0 1237 #define CLIENT2_K2__RESERVED_MASK 0xffffffff 1238 #define CLIENT2_K2__RESERVED__SHIFT 0x0 1239 #define CLIENT2_K3__RESERVED_MASK 0xffffffff 1240 #define CLIENT2_K3__RESERVED__SHIFT 0x0 1241 #define CLIENT2_CK0__RESERVED_MASK 0xffffffff 1242 #define CLIENT2_CK0__RESERVED__SHIFT 0x0 1243 #define CLIENT2_CK1__RESERVED_MASK 0xffffffff 1244 #define CLIENT2_CK1__RESERVED__SHIFT 0x0 1245 #define CLIENT2_CK2__RESERVED_MASK 0xffffffff 1246 #define CLIENT2_CK2__RESERVED__SHIFT 0x0 1247 #define CLIENT2_CK3__RESERVED_MASK 0xffffffff 1248 #define CLIENT2_CK3__RESERVED__SHIFT 0x0 1249 #define CLIENT2_CD0__RESERVED_MASK 0xffffffff 1250 #define CLIENT2_CD0__RESERVED__SHIFT 0x0 1251 #define CLIENT2_CD1__RESERVED_MASK 0xffffffff 1252 #define CLIENT2_CD1__RESERVED__SHIFT 0x0 1253 #define CLIENT2_CD2__RESERVED_MASK 0xffffffff 1254 #define CLIENT2_CD2__RESERVED__SHIFT 0x0 1255 #define CLIENT2_CD3__RESERVED_MASK 0xffffffff 1256 #define CLIENT2_CD3__RESERVED__SHIFT 0x0 1257 #define CLIENT2_BM__RESERVED_MASK 0xffffffff 1258 #define CLIENT2_BM__RESERVED__SHIFT 0x0 1259 #define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff 1260 #define CLIENT2_OFFSET__RESERVED__SHIFT 0x0 1261 #define CLIENT2_STATUS__RESERVED_MASK 0xffffffff 1262 #define CLIENT2_STATUS__RESERVED__SHIFT 0x0 1263 #define CLIENT0_K0__RESERVED_MASK 0xffffffff 1264 #define CLIENT0_K0__RESERVED__SHIFT 0x0 1265 #define CLIENT0_K1__RESERVED_MASK 0xffffffff 1266 #define CLIENT0_K1__RESERVED__SHIFT 0x0 1267 #define CLIENT0_K2__RESERVED_MASK 0xffffffff 1268 #define CLIENT0_K2__RESERVED__SHIFT 0x0 1269 #define CLIENT0_K3__RESERVED_MASK 0xffffffff 1270 #define CLIENT0_K3__RESERVED__SHIFT 0x0 1271 #define CLIENT0_CK0__RESERVED_MASK 0xffffffff 1272 #define CLIENT0_CK0__RESERVED__SHIFT 0x0 1273 #define CLIENT0_CK1__RESERVED_MASK 0xffffffff 1274 #define CLIENT0_CK1__RESERVED__SHIFT 0x0 1275 #define CLIENT0_CK2__RESERVED_MASK 0xffffffff 1276 #define CLIENT0_CK2__RESERVED__SHIFT 0x0 1277 #define CLIENT0_CK3__RESERVED_MASK 0xffffffff 1278 #define CLIENT0_CK3__RESERVED__SHIFT 0x0 1279 #define CLIENT0_CD0__RESERVED_MASK 0xffffffff 1280 #define CLIENT0_CD0__RESERVED__SHIFT 0x0 1281 #define CLIENT0_CD1__RESERVED_MASK 0xffffffff 1282 #define CLIENT0_CD1__RESERVED__SHIFT 0x0 1283 #define CLIENT0_CD2__RESERVED_MASK 0xffffffff 1284 #define CLIENT0_CD2__RESERVED__SHIFT 0x0 1285 #define CLIENT0_CD3__RESERVED_MASK 0xffffffff 1286 #define CLIENT0_CD3__RESERVED__SHIFT 0x0 1287 #define CLIENT0_BM__RESERVED_MASK 0xffffffff 1288 #define CLIENT0_BM__RESERVED__SHIFT 0x0 1289 #define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff 1290 #define CLIENT0_OFFSET__RESERVED__SHIFT 0x0 1291 #define CLIENT0_STATUS__RESERVED_MASK 0xffffffff 1292 #define CLIENT0_STATUS__RESERVED__SHIFT 0x0 1293 #define CLIENT1_K0__RESERVED_MASK 0xffffffff 1294 #define CLIENT1_K0__RESERVED__SHIFT 0x0 1295 #define CLIENT1_K1__RESERVED_MASK 0xffffffff 1296 #define CLIENT1_K1__RESERVED__SHIFT 0x0 1297 #define CLIENT1_K2__RESERVED_MASK 0xffffffff 1298 #define CLIENT1_K2__RESERVED__SHIFT 0x0 1299 #define CLIENT1_K3__RESERVED_MASK 0xffffffff 1300 #define CLIENT1_K3__RESERVED__SHIFT 0x0 1301 #define CLIENT1_CK0__RESERVED_MASK 0xffffffff 1302 #define CLIENT1_CK0__RESERVED__SHIFT 0x0 1303 #define CLIENT1_CK1__RESERVED_MASK 0xffffffff 1304 #define CLIENT1_CK1__RESERVED__SHIFT 0x0 1305 #define CLIENT1_CK2__RESERVED_MASK 0xffffffff 1306 #define CLIENT1_CK2__RESERVED__SHIFT 0x0 1307 #define CLIENT1_CK3__RESERVED_MASK 0xffffffff 1308 #define CLIENT1_CK3__RESERVED__SHIFT 0x0 1309 #define CLIENT1_CD0__RESERVED_MASK 0xffffffff 1310 #define CLIENT1_CD0__RESERVED__SHIFT 0x0 1311 #define CLIENT1_CD1__RESERVED_MASK 0xffffffff 1312 #define CLIENT1_CD1__RESERVED__SHIFT 0x0 1313 #define CLIENT1_CD2__RESERVED_MASK 0xffffffff 1314 #define CLIENT1_CD2__RESERVED__SHIFT 0x0 1315 #define CLIENT1_CD3__RESERVED_MASK 0xffffffff 1316 #define CLIENT1_CD3__RESERVED__SHIFT 0x0 1317 #define CLIENT1_BM__RESERVED_MASK 0xffffffff 1318 #define CLIENT1_BM__RESERVED__SHIFT 0x0 1319 #define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff 1320 #define CLIENT1_OFFSET__RESERVED__SHIFT 0x0 1321 #define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff 1322 #define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0 1323 #define KEFUSE0__RESERVED_MASK 0xffffffff 1324 #define KEFUSE0__RESERVED__SHIFT 0x0 1325 #define KEFUSE1__RESERVED_MASK 0xffffffff 1326 #define KEFUSE1__RESERVED__SHIFT 0x0 1327 #define KEFUSE2__RESERVED_MASK 0xffffffff 1328 #define KEFUSE2__RESERVED__SHIFT 0x0 1329 #define KEFUSE3__RESERVED_MASK 0xffffffff 1330 #define KEFUSE3__RESERVED__SHIFT 0x0 1331 #define HFS_SEED0__RESERVED_MASK 0xffffffff 1332 #define HFS_SEED0__RESERVED__SHIFT 0x0 1333 #define HFS_SEED1__RESERVED_MASK 0xffffffff 1334 #define HFS_SEED1__RESERVED__SHIFT 0x0 1335 #define HFS_SEED2__RESERVED_MASK 0xffffffff 1336 #define HFS_SEED2__RESERVED__SHIFT 0x0 1337 #define HFS_SEED3__RESERVED_MASK 0xffffffff 1338 #define HFS_SEED3__RESERVED__SHIFT 0x0 1339 #define RINGOSC_MASK__MASK_MASK 0xffff 1340 #define RINGOSC_MASK__MASK__SHIFT 0x0 1341 #define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff 1342 #define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0 1343 #define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff 1344 #define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0 1345 #define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff 1346 #define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0 1347 #define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff 1348 #define SPU_PORT_STATUS__RESERVED__SHIFT 0x0 1349 #define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff 1350 #define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0 1351 #define CLIENT3_K0__RESERVED_MASK 0xffffffff 1352 #define CLIENT3_K0__RESERVED__SHIFT 0x0 1353 #define CLIENT3_K1__RESERVED_MASK 0xffffffff 1354 #define CLIENT3_K1__RESERVED__SHIFT 0x0 1355 #define CLIENT3_K2__RESERVED_MASK 0xffffffff 1356 #define CLIENT3_K2__RESERVED__SHIFT 0x0 1357 #define CLIENT3_K3__RESERVED_MASK 0xffffffff 1358 #define CLIENT3_K3__RESERVED__SHIFT 0x0 1359 #define CLIENT3_CK0__RESERVED_MASK 0xffffffff 1360 #define CLIENT3_CK0__RESERVED__SHIFT 0x0 1361 #define CLIENT3_CK1__RESERVED_MASK 0xffffffff 1362 #define CLIENT3_CK1__RESERVED__SHIFT 0x0 1363 #define CLIENT3_CK2__RESERVED_MASK 0xffffffff 1364 #define CLIENT3_CK2__RESERVED__SHIFT 0x0 1365 #define CLIENT3_CK3__RESERVED_MASK 0xffffffff 1366 #define CLIENT3_CK3__RESERVED__SHIFT 0x0 1367 #define CLIENT3_CD0__RESERVED_MASK 0xffffffff 1368 #define CLIENT3_CD0__RESERVED__SHIFT 0x0 1369 #define CLIENT3_CD1__RESERVED_MASK 0xffffffff 1370 #define CLIENT3_CD1__RESERVED__SHIFT 0x0 1371 #define CLIENT3_CD2__RESERVED_MASK 0xffffffff 1372 #define CLIENT3_CD2__RESERVED__SHIFT 0x0 1373 #define CLIENT3_CD3__RESERVED_MASK 0xffffffff 1374 #define CLIENT3_CD3__RESERVED__SHIFT 0x0 1375 #define CLIENT3_BM__RESERVED_MASK 0xffffffff 1376 #define CLIENT3_BM__RESERVED__SHIFT 0x0 1377 #define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff 1378 #define CLIENT3_OFFSET__RESERVED__SHIFT 0x0 1379 #define CLIENT3_STATUS__RESERVED_MASK 0xffffffff 1380 #define CLIENT3_STATUS__RESERVED__SHIFT 0x0 1381 #define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff 1382 #define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0 1383 #define CLIENT4_K0__RESERVED_MASK 0xffffffff 1384 #define CLIENT4_K0__RESERVED__SHIFT 0x0 1385 #define CLIENT4_K1__RESERVED_MASK 0xffffffff 1386 #define CLIENT4_K1__RESERVED__SHIFT 0x0 1387 #define CLIENT4_K2__RESERVED_MASK 0xffffffff 1388 #define CLIENT4_K2__RESERVED__SHIFT 0x0 1389 #define CLIENT4_K3__RESERVED_MASK 0xffffffff 1390 #define CLIENT4_K3__RESERVED__SHIFT 0x0 1391 #define CLIENT4_CK0__RESERVED_MASK 0xffffffff 1392 #define CLIENT4_CK0__RESERVED__SHIFT 0x0 1393 #define CLIENT4_CK1__RESERVED_MASK 0xffffffff 1394 #define CLIENT4_CK1__RESERVED__SHIFT 0x0 1395 #define CLIENT4_CK2__RESERVED_MASK 0xffffffff 1396 #define CLIENT4_CK2__RESERVED__SHIFT 0x0 1397 #define CLIENT4_CK3__RESERVED_MASK 0xffffffff 1398 #define CLIENT4_CK3__RESERVED__SHIFT 0x0 1399 #define CLIENT4_CD0__RESERVED_MASK 0xffffffff 1400 #define CLIENT4_CD0__RESERVED__SHIFT 0x0 1401 #define CLIENT4_CD1__RESERVED_MASK 0xffffffff 1402 #define CLIENT4_CD1__RESERVED__SHIFT 0x0 1403 #define CLIENT4_CD2__RESERVED_MASK 0xffffffff 1404 #define CLIENT4_CD2__RESERVED__SHIFT 0x0 1405 #define CLIENT4_CD3__RESERVED_MASK 0xffffffff 1406 #define CLIENT4_CD3__RESERVED__SHIFT 0x0 1407 #define CLIENT4_BM__RESERVED_MASK 0xffffffff 1408 #define CLIENT4_BM__RESERVED__SHIFT 0x0 1409 #define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff 1410 #define CLIENT4_OFFSET__RESERVED__SHIFT 0x0 1411 #define CLIENT4_STATUS__RESERVED_MASK 0xffffffff 1412 #define CLIENT4_STATUS__RESERVED__SHIFT 0x0 1413 #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff 1414 #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0 1415 #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100 1416 #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 1417 #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff 1418 #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0 1419 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff 1420 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 1421 #define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff 1422 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 1423 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 1424 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 1425 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 1426 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 1427 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 1428 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 1429 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 1430 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 1431 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 1432 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 1433 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf 1434 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 1435 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1436 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1437 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 1438 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 1439 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 1440 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 1441 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 1442 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 1443 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 1444 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 1445 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 1446 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 1447 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 1448 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1449 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 1450 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 1451 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 1452 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 1453 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 1454 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 1455 #define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 1456 #define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 1457 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 1458 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 1459 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 1460 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 1461 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 1462 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 1463 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 1464 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 1465 #define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 1466 #define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 1467 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 1468 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 1469 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 1470 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 1471 #define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 1472 #define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 1473 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 1474 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 1475 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 1476 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 1477 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 1478 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 1479 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 1480 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 1481 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 1482 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 1483 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 1484 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 1485 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 1486 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 1487 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 1488 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 1489 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 1490 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 1491 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 1492 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 1493 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 1494 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 1495 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 1496 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 1497 #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1498 #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1499 #define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 1500 #define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 1501 #define SDMA0_HASH__BANK_BITS_MASK 0x70 1502 #define SDMA0_HASH__BANK_BITS__SHIFT 0x4 1503 #define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 1504 #define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 1505 #define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 1506 #define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc 1507 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 1508 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 1509 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 1510 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 1511 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 1512 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 1513 #define SDMA0_PROGRAM__STREAM_MASK 0xffffffff 1514 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 1515 #define SDMA0_STATUS_REG__IDLE_MASK 0x1 1516 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 1517 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 1518 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 1519 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 1520 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 1521 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 1522 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 1523 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 1524 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 1525 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 1526 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 1527 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 1528 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 1529 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 1530 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 1531 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 1532 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 1533 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 1534 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 1535 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 1536 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 1537 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 1538 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 1539 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 1540 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 1541 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 1542 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 1543 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 1544 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 1545 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 1546 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 1547 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 1548 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 1549 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 1550 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 1551 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 1552 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 1553 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 1554 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 1555 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 1556 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 1557 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 1558 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 1559 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 1560 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 1561 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 1562 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 1563 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 1564 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 1565 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 1566 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 1567 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 1568 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 1569 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 1570 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 1571 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 1572 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 1573 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 1574 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 1575 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 1576 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 1577 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 1578 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 1579 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 1580 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 1581 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 1582 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 1583 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 1584 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 1585 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 1586 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 1587 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 1588 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 1589 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 1590 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 1591 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 1592 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 1593 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 1594 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 1595 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 1596 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 1597 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 1598 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 1599 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 1600 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 1601 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 1602 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1603 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 1604 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1605 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 1606 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1607 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 1608 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 1609 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 1610 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 1611 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 1612 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 1613 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 1614 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1615 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 1616 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1617 #define SDMA0_F32_CNTL__HALT_MASK 0x1 1618 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 1619 #define SDMA0_F32_CNTL__STEP_MASK 0x2 1620 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 1621 #define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 1622 #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 1623 #define SDMA0_FREEZE__FREEZE_MASK 0x10 1624 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 1625 #define SDMA0_FREEZE__FROZEN_MASK 0x20 1626 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 1627 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 1628 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 1629 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf 1630 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 1631 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 1632 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 1633 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 1634 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 1635 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf 1636 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 1637 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 1638 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 1639 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 1640 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 1641 #define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 1642 #define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 1643 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 1644 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 1645 #define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 1646 #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 1647 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 1648 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 1649 #define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 1650 #define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 1651 #define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 1652 #define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 1653 #define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 1654 #define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 1655 #define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 1656 #define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 1657 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 1658 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 1659 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 1660 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 1661 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 1662 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 1663 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 1664 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 1665 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 1666 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 1667 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 1668 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 1669 #define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 1670 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 1671 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 1672 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 1673 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 1674 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 1675 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff 1676 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 1677 #define SDMA_PGFSM_READ__VALUE_MASK 0xffffff 1678 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 1679 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 1680 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1681 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 1682 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 1683 #define SDMA0_VM_CNTL__CMD_MASK 0xf 1684 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 1685 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc 1686 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 1687 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff 1688 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 1689 #define SDMA0_STATUS2_REG__ID_MASK 0x3 1690 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 1691 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc 1692 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 1693 #define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 1694 #define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe 1695 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 1696 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 1697 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf 1698 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1699 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 1700 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1701 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 1702 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 1703 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 1704 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 1705 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff 1706 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 1707 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 1708 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 1709 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 1710 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 1711 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff 1712 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 1713 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 1714 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 1715 #define SDMA0_ID__DEVICE_ID_MASK 0xff 1716 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 1717 #define SDMA0_VERSION__VALUE_MASK 0xffff 1718 #define SDMA0_VERSION__VALUE__SHIFT 0x0 1719 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 1720 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 1721 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 1722 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 1723 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 1724 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 1725 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 1726 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 1727 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff 1728 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 1729 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 1730 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 1731 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 1732 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 1733 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 1734 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 1735 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 1736 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 1737 #define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 1738 #define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 1739 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 1740 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 1741 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 1742 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 1743 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 1744 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 1745 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 1746 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 1747 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 1748 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 1749 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 1750 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 1751 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 1752 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 1753 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 1754 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 1755 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 1756 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 1757 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 1758 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 1759 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 1760 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 1761 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 1762 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 1763 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 1764 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 1765 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 1766 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 1767 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 1768 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 1769 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 1770 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 1771 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 1772 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 1773 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 1774 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 1775 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 1776 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 1777 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 1778 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 1779 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 1780 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 1781 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 1782 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 1783 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 1784 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 1785 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 1786 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 1787 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 1788 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb 1789 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 1790 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 1791 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 1792 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 1793 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 1794 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 1795 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 1796 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 1797 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 1798 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 1799 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 1800 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 1801 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 1802 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 1803 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 1804 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 1805 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 1806 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 1807 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 1808 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 1809 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 1810 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 1811 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 1812 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 1813 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 1814 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 1815 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40 1816 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6 1817 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 1818 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 1819 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 1820 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 1821 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 1822 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 1823 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 1824 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 1825 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 1826 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 1827 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 1828 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 1829 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 1830 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 1831 #define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 1832 #define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 1833 #define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 1834 #define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 1835 #define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 1836 #define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 1837 #define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 1838 #define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa 1839 #define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 1840 #define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb 1841 #define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 1842 #define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc 1843 #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 1844 #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd 1845 #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 1846 #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe 1847 #define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 1848 #define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf 1849 #define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 1850 #define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 1851 #define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 1852 #define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 1853 #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 1854 #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 1855 #define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 1856 #define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 1857 #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 1858 #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 1859 #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 1860 #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 1861 #define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 1862 #define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 1863 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 1864 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 1865 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 1866 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 1867 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 1868 #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 1869 #define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 1870 #define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a 1871 #define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 1872 #define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b 1873 #define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 1874 #define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c 1875 #define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 1876 #define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d 1877 #define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 1878 #define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 1879 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 1880 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 1881 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 1882 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 1883 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 1884 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 1885 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 1886 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 1887 #define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 1888 #define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 1889 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 1890 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 1891 #define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 1892 #define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 1893 #define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 1894 #define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 1895 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 1896 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 1897 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 1898 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 1899 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 1900 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa 1901 #define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 1902 #define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb 1903 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 1904 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1905 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 1906 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1907 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 1908 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1909 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 1910 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1911 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 1912 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1913 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 1914 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1915 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 1916 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1917 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 1918 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1919 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff 1920 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1921 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 1922 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1923 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 1924 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 1925 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 1926 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 1927 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 1928 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1929 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 1930 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1931 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 1932 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1933 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 1934 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1935 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 1936 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1937 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 1938 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1939 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 1940 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1941 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 1942 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1943 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 1944 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1945 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 1946 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1947 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 1948 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1949 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 1950 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1951 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 1952 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1953 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 1954 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1955 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 1956 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1957 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 1958 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1959 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 1960 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1961 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff 1962 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1963 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 1964 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1965 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 1966 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1967 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 1968 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1969 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 1970 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1971 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 1972 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1973 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 1974 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1975 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 1976 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1977 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 1978 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1979 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 1980 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1981 #define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff 1982 #define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 1983 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 1984 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1985 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 1986 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1987 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 1988 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1989 #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 1990 #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 1991 #define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 1992 #define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 1993 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 1994 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 1995 #define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 1996 #define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 1997 #define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 1998 #define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 1999 #define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2000 #define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2001 #define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff 2002 #define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 2003 #define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 2004 #define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 2005 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 2006 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2007 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 2008 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 2009 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2010 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2011 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2012 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2013 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2014 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 2015 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2016 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 2017 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2018 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2019 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 2020 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 2021 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 2022 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 2023 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2024 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 2025 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2026 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 2027 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2028 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 2029 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2030 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 2031 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2032 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 2033 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2034 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 2035 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2036 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2037 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2038 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2039 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2040 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2041 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2042 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2043 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 2044 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 2045 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 2046 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 2047 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2048 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2049 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2050 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2051 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2052 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2053 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2054 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2055 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 2056 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 2057 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 2058 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 2059 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff 2060 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 2061 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 2062 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 2063 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 2064 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 2065 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 2066 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 2067 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2068 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2069 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2070 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2071 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2072 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2073 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2074 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2075 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2076 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2077 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2078 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2079 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2080 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2081 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2082 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2083 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2084 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2085 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 2086 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 2087 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2088 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2089 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2090 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2091 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 2092 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 2093 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 2094 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 2095 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 2096 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 2097 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 2098 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 2099 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 2100 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 2101 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff 2102 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 2103 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2104 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2105 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 2106 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2107 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 2108 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 2109 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 2110 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2111 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2112 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2113 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2114 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2115 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2116 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2117 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2118 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2119 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2120 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2121 #define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 2122 #define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 2123 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 2124 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 2125 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 2126 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 2127 #define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 2128 #define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 2129 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 2130 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2131 #define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 2132 #define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2133 #define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2134 #define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2135 #define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2136 #define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2137 #define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff 2138 #define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 2139 #define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 2140 #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 2141 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 2142 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2143 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 2144 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 2145 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2146 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2147 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2148 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2149 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2150 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 2151 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2152 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 2153 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2154 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2155 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 2156 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 2157 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 2158 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 2159 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2160 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 2161 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2162 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 2163 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2164 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 2165 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2166 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 2167 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2168 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 2169 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2170 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 2171 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2172 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2173 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2174 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2175 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2176 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2177 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2178 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2179 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 2180 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 2181 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 2182 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 2183 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2184 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2185 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2186 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2187 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2188 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2189 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2190 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2191 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 2192 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 2193 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 2194 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 2195 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff 2196 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 2197 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 2198 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 2199 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 2200 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 2201 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 2202 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 2203 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2204 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2205 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2206 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2207 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2208 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2209 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2210 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2211 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2212 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2213 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2214 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2215 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2216 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2217 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2218 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2219 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2220 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2221 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 2222 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 2223 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2224 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2225 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2226 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2227 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 2228 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 2229 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 2230 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 2231 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 2232 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 2233 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 2234 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 2235 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 2236 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 2237 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff 2238 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 2239 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2240 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2241 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 2242 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2243 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 2244 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 2245 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 2246 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2247 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2248 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2249 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2250 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2251 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2252 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2253 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2254 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2255 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2256 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2257 #define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 2258 #define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 2259 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 2260 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 2261 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 2262 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 2263 #define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 2264 #define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 2265 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 2266 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2267 #define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 2268 #define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2269 #define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2270 #define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2271 #define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2272 #define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2273 #define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff 2274 #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 2275 #define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 2276 #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 2277 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 2278 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2279 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 2280 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 2281 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2282 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2283 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2284 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2285 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2286 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 2287 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2288 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 2289 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2290 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2291 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 2292 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 2293 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 2294 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 2295 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2296 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 2297 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2298 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 2299 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2300 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 2301 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2302 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 2303 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2304 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 2305 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2306 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 2307 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2308 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2309 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2310 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2311 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2312 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2313 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2314 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2315 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff 2316 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 2317 #define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff 2318 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 2319 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 2320 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 2321 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 2322 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 2323 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 2324 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 2325 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 2326 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 2327 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 2328 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 2329 #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf 2330 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 2331 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 2332 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2333 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 2334 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 2335 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 2336 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 2337 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 2338 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 2339 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 2340 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 2341 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 2342 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 2343 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 2344 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 2345 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 2346 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 2347 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 2348 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 2349 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 2350 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 2351 #define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 2352 #define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 2353 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 2354 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 2355 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 2356 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 2357 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 2358 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 2359 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 2360 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 2361 #define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 2362 #define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 2363 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 2364 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 2365 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 2366 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 2367 #define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 2368 #define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 2369 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 2370 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 2371 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 2372 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 2373 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 2374 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 2375 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 2376 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 2377 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 2378 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 2379 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 2380 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 2381 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 2382 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 2383 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 2384 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 2385 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 2386 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 2387 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 2388 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 2389 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 2390 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 2391 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 2392 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 2393 #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 2394 #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 2395 #define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 2396 #define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 2397 #define SDMA1_HASH__BANK_BITS_MASK 0x70 2398 #define SDMA1_HASH__BANK_BITS__SHIFT 0x4 2399 #define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 2400 #define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 2401 #define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 2402 #define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc 2403 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 2404 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 2405 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 2406 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 2407 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 2408 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 2409 #define SDMA1_PROGRAM__STREAM_MASK 0xffffffff 2410 #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 2411 #define SDMA1_STATUS_REG__IDLE_MASK 0x1 2412 #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 2413 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 2414 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 2415 #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 2416 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 2417 #define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 2418 #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 2419 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 2420 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 2421 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 2422 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 2423 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 2424 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 2425 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 2426 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 2427 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 2428 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 2429 #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 2430 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 2431 #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 2432 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 2433 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 2434 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 2435 #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 2436 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 2437 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 2438 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 2439 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 2440 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 2441 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 2442 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 2443 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 2444 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 2445 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 2446 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 2447 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 2448 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 2449 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 2450 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 2451 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 2452 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 2453 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 2454 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 2455 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 2456 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 2457 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 2458 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 2459 #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 2460 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 2461 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 2462 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 2463 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 2464 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 2465 #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 2466 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 2467 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 2468 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 2469 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 2470 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 2471 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 2472 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 2473 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 2474 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 2475 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 2476 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 2477 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 2478 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 2479 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 2480 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 2481 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 2482 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 2483 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 2484 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 2485 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 2486 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 2487 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 2488 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 2489 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 2490 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 2491 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 2492 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 2493 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 2494 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 2495 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 2496 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 2497 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 2498 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 2499 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 2500 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 2501 #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 2502 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 2503 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 2504 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 2505 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 2506 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 2507 #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 2508 #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 2509 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 2510 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 2511 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 2512 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 2513 #define SDMA1_F32_CNTL__HALT_MASK 0x1 2514 #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 2515 #define SDMA1_F32_CNTL__STEP_MASK 0x2 2516 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 2517 #define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 2518 #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 2519 #define SDMA1_FREEZE__FREEZE_MASK 0x10 2520 #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 2521 #define SDMA1_FREEZE__FROZEN_MASK 0x20 2522 #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 2523 #define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 2524 #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 2525 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf 2526 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 2527 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 2528 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 2529 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 2530 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 2531 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf 2532 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 2533 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 2534 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 2535 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 2536 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 2537 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 2538 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 2539 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 2540 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 2541 #define SDMA1_VM_CNTL__CMD_MASK 0xf 2542 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 2543 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc 2544 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 2545 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff 2546 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 2547 #define SDMA1_STATUS2_REG__ID_MASK 0x3 2548 #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 2549 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc 2550 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 2551 #define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 2552 #define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe 2553 #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 2554 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 2555 #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf 2556 #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 2557 #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 2558 #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 2559 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 2560 #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 2561 #define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 2562 #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 2563 #define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff 2564 #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 2565 #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 2566 #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 2567 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 2568 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 2569 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff 2570 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 2571 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 2572 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 2573 #define SDMA1_ID__DEVICE_ID_MASK 0xff 2574 #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 2575 #define SDMA1_VERSION__VALUE_MASK 0xffff 2576 #define SDMA1_VERSION__VALUE__SHIFT 0x0 2577 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 2578 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 2579 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 2580 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 2581 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 2582 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 2583 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 2584 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 2585 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff 2586 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 2587 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 2588 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 2589 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 2590 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 2591 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 2592 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 2593 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 2594 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 2595 #define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 2596 #define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 2597 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 2598 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 2599 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 2600 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 2601 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 2602 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 2603 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 2604 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 2605 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 2606 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 2607 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 2608 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 2609 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 2610 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 2611 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 2612 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 2613 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 2614 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 2615 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 2616 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 2617 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 2618 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 2619 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 2620 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 2621 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 2622 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 2623 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 2624 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 2625 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 2626 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 2627 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 2628 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 2629 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 2630 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 2631 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 2632 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 2633 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 2634 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 2635 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 2636 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 2637 #define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 2638 #define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 2639 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f 2640 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 2641 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 2642 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 2643 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 2644 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 2645 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 2646 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 2647 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 2648 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 2649 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 2650 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb 2651 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 2652 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 2653 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 2654 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 2655 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 2656 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe 2657 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 2658 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 2659 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 2660 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 2661 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 2662 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 2663 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 2664 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 2665 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 2666 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 2667 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 2668 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 2669 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 2670 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 2671 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 2672 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 2673 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 2674 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 2675 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 2676 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 2677 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40 2678 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6 2679 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 2680 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 2681 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 2682 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 2683 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 2684 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 2685 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 2686 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 2687 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 2688 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 2689 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 2690 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 2691 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 2692 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 2693 #define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 2694 #define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 2695 #define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 2696 #define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 2697 #define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 2698 #define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 2699 #define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 2700 #define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa 2701 #define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 2702 #define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb 2703 #define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 2704 #define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc 2705 #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 2706 #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd 2707 #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 2708 #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe 2709 #define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 2710 #define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf 2711 #define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 2712 #define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 2713 #define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 2714 #define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 2715 #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 2716 #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 2717 #define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 2718 #define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 2719 #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 2720 #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 2721 #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 2722 #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 2723 #define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 2724 #define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 2725 #define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 2726 #define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a 2727 #define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 2728 #define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b 2729 #define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 2730 #define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c 2731 #define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 2732 #define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d 2733 #define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 2734 #define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 2735 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 2736 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 2737 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 2738 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 2739 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 2740 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 2741 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 2742 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 2743 #define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 2744 #define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 2745 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 2746 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 2747 #define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 2748 #define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 2749 #define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 2750 #define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 2751 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 2752 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 2753 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 2754 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 2755 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 2756 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa 2757 #define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 2758 #define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb 2759 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 2760 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 2761 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 2762 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 2763 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2764 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2765 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2766 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2767 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2768 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2769 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2770 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2771 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 2772 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 2773 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 2774 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 2775 #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff 2776 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 2777 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 2778 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 2779 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 2780 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 2781 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 2782 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 2783 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2784 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2785 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2786 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2787 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2788 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2789 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2790 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2791 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2792 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2793 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2794 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2795 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2796 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2797 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2798 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2799 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2800 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2801 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 2802 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 2803 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2804 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2805 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2806 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2807 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 2808 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 2809 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 2810 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 2811 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 2812 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 2813 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 2814 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 2815 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 2816 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 2817 #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff 2818 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 2819 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2820 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2821 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 2822 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2823 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 2824 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 2825 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 2826 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2827 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2828 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2829 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2830 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2831 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2832 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2833 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2834 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2835 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2836 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2837 #define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff 2838 #define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 2839 #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 2840 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 2841 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 2842 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 2843 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 2844 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 2845 #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 2846 #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 2847 #define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 2848 #define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 2849 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 2850 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2851 #define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 2852 #define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2853 #define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2854 #define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2855 #define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2856 #define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2857 #define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff 2858 #define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 2859 #define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 2860 #define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 2861 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 2862 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2863 #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 2864 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 2865 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2866 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2867 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2868 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2869 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2870 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 2871 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2872 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 2873 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2874 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2875 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 2876 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 2877 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 2878 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 2879 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2880 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 2881 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2882 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 2883 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2884 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 2885 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2886 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 2887 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2888 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 2889 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2890 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 2891 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2892 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2893 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2894 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2895 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2896 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2897 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2898 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2899 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 2900 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 2901 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 2902 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 2903 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2904 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2905 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2906 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2907 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2908 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2909 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2910 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2911 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 2912 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 2913 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 2914 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 2915 #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff 2916 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 2917 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 2918 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 2919 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 2920 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 2921 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 2922 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 2923 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2924 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2925 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2926 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2927 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2928 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2929 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2930 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2931 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2932 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2933 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2934 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2935 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2936 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2937 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2938 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2939 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2940 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2941 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 2942 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 2943 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2944 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2945 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2946 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2947 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 2948 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 2949 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 2950 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 2951 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 2952 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 2953 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 2954 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 2955 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 2956 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 2957 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff 2958 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 2959 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2960 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2961 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 2962 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2963 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 2964 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 2965 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 2966 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2967 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2968 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2969 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2970 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2971 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2972 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2973 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2974 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2975 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2976 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2977 #define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 2978 #define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 2979 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 2980 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 2981 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 2982 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 2983 #define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 2984 #define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 2985 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 2986 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2987 #define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 2988 #define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2989 #define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2990 #define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2991 #define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2992 #define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2993 #define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff 2994 #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 2995 #define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 2996 #define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 2997 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 2998 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2999 #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 3000 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 3001 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 3002 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3003 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 3004 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3005 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 3006 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 3007 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 3008 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 3009 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 3010 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3011 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 3012 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 3013 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 3014 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 3015 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 3016 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 3017 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 3018 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 3019 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 3020 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 3021 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 3022 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 3023 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 3024 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 3025 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 3026 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 3027 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 3028 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3029 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 3030 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3031 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 3032 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3033 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 3034 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3035 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 3036 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 3037 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 3038 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 3039 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 3040 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 3041 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 3042 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 3043 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 3044 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 3045 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 3046 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 3047 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 3048 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 3049 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 3050 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 3051 #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff 3052 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 3053 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 3054 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 3055 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 3056 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 3057 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 3058 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 3059 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 3060 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 3061 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 3062 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 3063 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 3064 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 3065 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 3066 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 3067 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 3068 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3069 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 3070 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3071 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 3072 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 3073 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 3074 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 3075 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 3076 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 3077 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 3078 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 3079 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 3080 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 3081 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 3082 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 3083 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 3084 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 3085 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 3086 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 3087 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 3088 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 3089 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 3090 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 3091 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 3092 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 3093 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff 3094 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 3095 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 3096 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 3097 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 3098 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 3099 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 3100 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 3101 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 3102 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 3103 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 3104 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 3105 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 3106 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 3107 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 3108 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 3109 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 3110 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3111 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 3112 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3113 #define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 3114 #define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 3115 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 3116 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 3117 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 3118 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 3119 #define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 3120 #define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 3121 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 3122 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 3123 #define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 3124 #define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 3125 #define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 3126 #define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 3127 #define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 3128 #define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 3129 #define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff 3130 #define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 3131 #define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 3132 #define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 3133 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 3134 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3135 #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 3136 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 3137 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 3138 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3139 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 3140 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3141 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 3142 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 3143 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 3144 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 3145 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 3146 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3147 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 3148 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 3149 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 3150 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 3151 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 3152 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 3153 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 3154 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 3155 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 3156 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 3157 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 3158 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 3159 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 3160 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 3161 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 3162 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 3163 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 3164 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3165 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 3166 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3167 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 3168 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3169 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 3170 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3171 #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 3172 #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 3173 #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 3174 #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 3175 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 3176 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 3177 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 3178 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 3179 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 3180 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 3181 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 3182 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 3183 #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 3184 #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 3185 #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 3186 #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 3187 #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 3188 #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 3189 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 3190 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 3191 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 3192 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 3193 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 3194 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 3195 #define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff 3196 #define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 3197 #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 3198 #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 3199 #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e 3200 #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 3201 #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 3202 #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 3203 #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 3204 #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 3205 #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 3206 #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa 3207 #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 3208 #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd 3209 #define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 3210 #define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf 3211 #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 3212 #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 3213 #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 3214 #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 3215 #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 3216 #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 3217 #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 3218 #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 3219 #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 3220 #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 3221 #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 3222 #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a 3223 #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 3224 #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c 3225 #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 3226 #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f 3227 #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff 3228 #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 3229 #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 3230 #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb 3231 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 3232 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 3233 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 3234 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 3235 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 3236 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 3237 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 3238 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 3239 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff 3240 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 3241 #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 3242 #define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 3243 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f 3244 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 3245 #define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe 3246 #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 3247 #define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 3248 #define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 3249 #define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 3250 #define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 3251 #define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 3252 #define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 3253 #define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 3254 #define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb 3255 #define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 3256 #define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe 3257 #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 3258 #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 3259 #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 3260 #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 3261 #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff 3262 #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 3263 #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 3264 #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 3265 #define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 3266 #define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 3267 #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 3268 #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 3269 #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 3270 #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 3271 #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 3272 #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 3273 #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 3274 #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 3275 #define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 3276 #define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 3277 #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 3278 #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 3279 #define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 3280 #define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 3281 #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 3282 #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 3283 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 3284 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 3285 #define HDP_MISC_CNTL__VM_ID_MASK 0x1e 3286 #define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 3287 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 3288 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 3289 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 3290 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 3291 #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 3292 #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 3293 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 3294 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 3295 #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 3296 #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc 3297 #define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 3298 #define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 3299 #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 3300 #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 3301 #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 3302 #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 3303 #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 3304 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 3305 #define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 3306 #define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 3307 #define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 3308 #define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 3309 #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 3310 #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 3311 #define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e 3312 #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 3313 #define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 3314 #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 3315 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 3316 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 3317 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 3318 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 3319 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 3320 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 3321 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 3322 #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 3323 #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 3324 #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b 3325 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 3326 #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 3327 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 3328 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 3329 #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c 3330 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 3331 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 3332 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 3333 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 3334 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 3335 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 3336 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 3337 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 3338 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 3339 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 3340 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 3341 #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 3342 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 3343 #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 3344 #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 3345 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff 3346 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 3347 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 3348 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 3349 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 3350 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 3351 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 3352 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 3353 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 3354 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 3355 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff 3356 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 3357 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff 3358 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 3359 #define HDP_VF_ENABLE__VF_EN_MASK 0x1 3360 #define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 3361 #define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 3362 #define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 3363 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff 3364 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 3365 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf 3366 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 3367 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 3368 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 3369 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 3370 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 3371 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 3372 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 3373 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 3374 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 3375 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 3376 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 3377 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 3378 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 3379 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 3380 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 3381 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 3382 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 3383 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff 3384 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 3385 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 3386 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 3387 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 3388 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 3389 #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff 3390 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 3391 #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff 3392 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 3393 #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff 3394 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 3395 #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff 3396 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 3397 #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff 3398 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 3399 #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff 3400 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 3401 #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff 3402 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 3403 #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff 3404 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 3405 #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff 3406 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 3407 #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff 3408 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 3409 #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff 3410 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 3411 #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff 3412 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 3413 #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff 3414 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 3415 #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff 3416 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 3417 #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff 3418 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 3419 #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff 3420 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 3421 #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff 3422 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 3423 #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff 3424 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 3425 #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff 3426 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 3427 #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff 3428 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 3429 #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff 3430 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 3431 #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff 3432 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 3433 #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff 3434 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 3435 #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff 3436 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 3437 #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff 3438 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 3439 #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff 3440 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 3441 #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff 3442 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 3443 #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff 3444 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 3445 #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff 3446 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 3447 #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff 3448 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 3449 #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff 3450 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 3451 #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff 3452 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 3453 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff 3454 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 3455 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf 3456 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 3457 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 3458 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 3459 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff 3460 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 3461 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 3462 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 3463 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe 3464 #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 3465 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 3466 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 3467 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 3468 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 3469 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe 3470 #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 3471 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 3472 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 3473 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 3474 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 3475 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe 3476 #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 3477 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 3478 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 3479 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 3480 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 3481 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe 3482 #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 3483 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 3484 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 3485 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 3486 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 3487 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe 3488 #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 3489 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 3490 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 3491 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 3492 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 3493 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe 3494 #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 3495 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 3496 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 3497 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 3498 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 3499 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe 3500 #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 3501 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 3502 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 3503 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 3504 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 3505 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 3506 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 3507 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 3508 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 3509 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 3510 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 3511 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 3512 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 3513 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 3514 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 3515 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 3516 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 3517 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 3518 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 3519 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 3520 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 3521 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 3522 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 3523 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 3524 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 3525 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 3526 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 3527 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 3528 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 3529 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 3530 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 3531 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 3532 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b 3533 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 3534 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 3535 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 3536 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3537 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 3538 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 3539 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 3540 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3541 #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 3542 #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 3543 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f 3544 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 3545 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 3546 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 3547 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 3548 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 3549 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 3550 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 3551 #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f 3552 #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 3553 #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 3554 #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 3555 #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 3556 #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 3557 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf 3558 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 3559 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 3560 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 3561 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 3562 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc 3563 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 3564 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e 3565 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 3566 #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f 3567 #define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff 3568 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 3569 #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 3570 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 3571 #define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 3572 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 3573 #define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff 3574 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 3575 #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 3576 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 3577 #define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 3578 #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 3579 #define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff 3580 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 3581 #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 3582 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 3583 #define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 3584 #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 3585 #define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff 3586 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 3587 #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 3588 #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 3589 #define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 3590 #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 3591 #define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff 3592 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 3593 #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 3594 #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 3595 #define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 3596 #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 3597 #define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff 3598 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 3599 #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 3600 #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 3601 #define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 3602 #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 3603 #define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff 3604 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 3605 #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 3606 #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 3607 #define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 3608 #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 3609 #define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff 3610 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 3611 #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 3612 #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 3613 #define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 3614 #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 3615 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff 3616 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 3617 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff 3618 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 3619 #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff 3620 #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 3621 #define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff 3622 #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 3623 #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 3624 #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 3625 #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff 3626 #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 3627 #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 3628 #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 3629 #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 3630 #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 3631 #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 3632 #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 3633 #define HDP_XDP_DBG_ADDR__STS_MASK 0xffff 3634 #define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 3635 #define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 3636 #define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 3637 #define HDP_XDP_DBG_DATA__STS_MASK 0xffff 3638 #define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 3639 #define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 3640 #define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 3641 #define HDP_XDP_DBG_MASK__STS_MASK 0xffff 3642 #define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 3643 #define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 3644 #define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 3645 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf 3646 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 3647 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 3648 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 3649 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 3650 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 3651 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 3652 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 3653 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 3654 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 3655 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 3656 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 3657 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 3658 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 3659 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 3660 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 3661 3662 #endif /* OSS_3_0_SH_MASK_H */ 3663