1 /* $NetBSD: oss_3_0_d.h,v 1.3 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * OSS_3_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef OSS_3_0_D_H 27 #define OSS_3_0_D_H 28 29 #define mmIH_VMID_0_LUT 0xe00 30 #define mmIH_VMID_1_LUT 0xe01 31 #define mmIH_VMID_2_LUT 0xe02 32 #define mmIH_VMID_3_LUT 0xe03 33 #define mmIH_VMID_4_LUT 0xe04 34 #define mmIH_VMID_5_LUT 0xe05 35 #define mmIH_VMID_6_LUT 0xe06 36 #define mmIH_VMID_7_LUT 0xe07 37 #define mmIH_VMID_8_LUT 0xe08 38 #define mmIH_VMID_9_LUT 0xe09 39 #define mmIH_VMID_10_LUT 0xe0a 40 #define mmIH_VMID_11_LUT 0xe0b 41 #define mmIH_VMID_12_LUT 0xe0c 42 #define mmIH_VMID_13_LUT 0xe0d 43 #define mmIH_VMID_14_LUT 0xe0e 44 #define mmIH_VMID_15_LUT 0xe0f 45 #define mmIH_RB_CNTL 0xe30 46 #define mmIH_RB_BASE 0xe31 47 #define mmIH_RB_RPTR 0xe32 48 #define mmIH_RB_WPTR 0xe33 49 #define mmIH_RB_WPTR_ADDR_HI 0xe34 50 #define mmIH_RB_WPTR_ADDR_LO 0xe35 51 #define mmIH_CNTL 0xe36 52 #define mmIH_LEVEL_STATUS 0xe37 53 #define mmIH_STATUS 0xe38 54 #define mmIH_PERFMON_CNTL 0xe39 55 #define mmIH_PERFCOUNTER0_RESULT 0xe3a 56 #define mmIH_PERFCOUNTER1_RESULT 0xe3b 57 #define mmIH_DEBUG 0xe3c 58 #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d 59 #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e 60 #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f 61 #define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 62 #define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 63 #define mmIH_DOORBELL_RPTR 0xe42 64 #define mmIH_ACTIVE_FCN_ID 0xe43 65 #define mmIH_VF_RB_STATUS 0xe44 66 #define mmIH_VF_ENABLE 0xe45 67 #define mmIH_VIRT_RESET_REQ 0xe46 68 #define mmIH_VF_RB_BIF_STATUS 0xe47 69 #define mmIH_VERSION 0xe48 70 #define mmIH_LEVEL_INTR_MASK 0xe49 71 #define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a 72 #define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b 73 #define mmSEM_MCIF_CONFIG 0xf90 74 #define mmSDMA_CONFIG 0xf91 75 #define mmSDMA1_CONFIG 0xf92 76 #define mmUVD_CONFIG 0xf93 77 #define mmVCE_CONFIG 0xf94 78 #define mmSEM_VF_ENABLE 0xf95 79 #define mmCP_CONFIG 0xf96 80 #define mmSEM_ACTIVE_FCN_ID 0xf97 81 #define mmSEM_VIRT_RESET_REQ 0xf98 82 #define mmSEM_STATUS 0xf99 83 #define mmSEM_EDC_CONFIG 0xf9a 84 #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b 85 #define mmSEM_MAILBOX 0xf9c 86 #define mmSEM_MAILBOX_CONTROL 0xf9d 87 #define mmSEM_CHICKEN_BITS 0xf9e 88 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f 89 #define mmSRBM_CNTL 0x390 90 #define mmSRBM_GFX_CNTL 0x391 91 #define mmSRBM_READ_CNTL 0x392 92 #define mmSRBM_STATUS2 0x393 93 #define mmSRBM_STATUS 0x394 94 #define mmSRBM_STATUS3 0x395 95 #define mmSRBM_SOFT_RESET 0x398 96 #define mmSRBM_DEBUG_CNTL 0x399 97 #define mmSRBM_DEBUG_DATA 0x39a 98 #define mmSRBM_CHIP_REVISION 0x39b 99 #define mmSRBM_CREDIT_RECOVER_CNTL 0x39c 100 #define mmSRBM_CREDIT_RECOVER 0x39d 101 #define mmSRBM_CREDIT_RESET 0x39e 102 #define mmCC_SYS_RB_REDUNDANCY 0x39f 103 #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 104 #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 105 #define mmSRBM_MC_CLKEN_CNTL 0x3b3 106 #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 107 #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 108 #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 109 #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 110 #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 111 #define mmSRBM_ISP_CLKEN_CNTL 0x3b9 112 #define mmSRBM_VP8_CLKEN_CNTL 0x3ba 113 #define mmSRBM_DEBUG 0x3a4 114 #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 115 #define mmSRBM_DEBUG_SNAPSHOT2 0x3ad 116 #define mmSRBM_READ_ERROR 0x3a6 117 #define mmSRBM_READ_ERROR2 0x3ae 118 #define mmSRBM_INT_CNTL 0x3a8 119 #define mmSRBM_INT_STATUS 0x3a9 120 #define mmSRBM_INT_ACK 0x3aa 121 #define mmSRBM_FIREWALL_ERROR_SRC 0x3ab 122 #define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac 123 #define mmSRBM_DSM_TRIG_CNTL0 0x3af 124 #define mmSRBM_DSM_TRIG_CNTL1 0x3b0 125 #define mmSRBM_DSM_TRIG_MASK0 0x3b1 126 #define mmSRBM_DSM_TRIG_MASK1 0x3b2 127 #define mmSRBM_PERFMON_CNTL 0x7c00 128 #define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 129 #define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 130 #define mmSRBM_PERFCOUNTER0_LO 0x7c03 131 #define mmSRBM_PERFCOUNTER0_HI 0x7c04 132 #define mmSRBM_PERFCOUNTER1_LO 0x7c05 133 #define mmSRBM_PERFCOUNTER1_HI 0x7c06 134 #define mmSRBM_CAM_INDEX 0xfe34 135 #define mmSRBM_CAM_DATA 0xfe35 136 #define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 137 #define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 138 #define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 139 #define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 140 #define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 141 #define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 142 #define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 143 #define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 144 #define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 145 #define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a 146 #define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b 147 #define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c 148 #define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d 149 #define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e 150 #define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 151 #define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 152 #define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 153 #define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 154 #define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 155 #define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 156 #define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 157 #define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 158 #define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 159 #define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a 160 #define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c 161 #define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d 162 #define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e 163 #define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 164 #define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 165 #define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 166 #define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 167 #define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c 168 #define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d 169 #define mmSRBM_GFX_CNTL_SELECT 0xfa2e 170 #define mmSRBM_GFX_CNTL_DATA 0xfa2f 171 #define mmSRBM_VF_ENABLE 0xfa30 172 #define mmSRBM_VIRT_CNTL 0xfa31 173 #define mmSRBM_VIRT_RESET_REQ 0xfa32 174 #define mmCC_DRM_ID_STRAPS 0x1559 175 #define mmCGTT_DRM_CLK_CTRL0 0x1579 176 #define ixDH_TEST 0x0 177 #define ixKHFS0 0x4 178 #define ixKHFS1 0x8 179 #define ixKHFS2 0xc 180 #define ixKHFS3 0x10 181 #define ixKSESSION0 0x14 182 #define ixKSESSION1 0x18 183 #define ixKSESSION2 0x1c 184 #define ixKSESSION3 0x20 185 #define ixKSIG0 0x24 186 #define ixKSIG1 0x28 187 #define ixKSIG2 0x2c 188 #define ixKSIG3 0x30 189 #define ixEXP0 0x34 190 #define ixEXP1 0x38 191 #define ixEXP2 0x3c 192 #define ixEXP3 0x40 193 #define ixEXP4 0x44 194 #define ixEXP5 0x48 195 #define ixEXP6 0x4c 196 #define ixEXP7 0x50 197 #define ixLX0 0x54 198 #define ixLX1 0x58 199 #define ixLX2 0x5c 200 #define ixLX3 0x60 201 #define ixCLIENT2_K0 0x1b4 202 #define ixCLIENT2_K1 0x1b8 203 #define ixCLIENT2_K2 0x1bc 204 #define ixCLIENT2_K3 0x1c0 205 #define ixCLIENT2_CK0 0x1c4 206 #define ixCLIENT2_CK1 0x1c8 207 #define ixCLIENT2_CK2 0x1cc 208 #define ixCLIENT2_CK3 0x1d0 209 #define ixCLIENT2_CD0 0x1d4 210 #define ixCLIENT2_CD1 0x1d8 211 #define ixCLIENT2_CD2 0x1dc 212 #define ixCLIENT2_CD3 0x1e0 213 #define ixCLIENT2_BM 0x1e4 214 #define ixCLIENT2_OFFSET 0x1e8 215 #define ixCLIENT2_STATUS 0x1ec 216 #define ixCLIENT0_K0 0x1f0 217 #define ixCLIENT0_K1 0x1f4 218 #define ixCLIENT0_K2 0x1f8 219 #define ixCLIENT0_K3 0x1fc 220 #define ixCLIENT0_CK0 0x200 221 #define ixCLIENT0_CK1 0x204 222 #define ixCLIENT0_CK2 0x208 223 #define ixCLIENT0_CK3 0x20c 224 #define ixCLIENT0_CD0 0x210 225 #define ixCLIENT0_CD1 0x214 226 #define ixCLIENT0_CD2 0x218 227 #define ixCLIENT0_CD3 0x21c 228 #define ixCLIENT0_BM 0x220 229 #define ixCLIENT0_OFFSET 0x224 230 #define ixCLIENT0_STATUS 0x228 231 #define ixCLIENT1_K0 0x22c 232 #define ixCLIENT1_K1 0x230 233 #define ixCLIENT1_K2 0x234 234 #define ixCLIENT1_K3 0x238 235 #define ixCLIENT1_CK0 0x23c 236 #define ixCLIENT1_CK1 0x240 237 #define ixCLIENT1_CK2 0x244 238 #define ixCLIENT1_CK3 0x248 239 #define ixCLIENT1_CD0 0x24c 240 #define ixCLIENT1_CD1 0x250 241 #define ixCLIENT1_CD2 0x254 242 #define ixCLIENT1_CD3 0x258 243 #define ixCLIENT1_BM 0x25c 244 #define ixCLIENT1_OFFSET 0x260 245 #define ixCLIENT1_PORT_STATUS 0x264 246 #define ixKEFUSE0 0x268 247 #define ixKEFUSE1 0x26c 248 #define ixKEFUSE2 0x270 249 #define ixKEFUSE3 0x274 250 #define ixHFS_SEED0 0x278 251 #define ixHFS_SEED1 0x27c 252 #define ixHFS_SEED2 0x280 253 #define ixHFS_SEED3 0x284 254 #define ixRINGOSC_MASK 0x288 255 #define ixCLIENT0_OFFSET_HI 0x290 256 #define ixCLIENT1_OFFSET_HI 0x294 257 #define ixCLIENT2_OFFSET_HI 0x298 258 #define ixSPU_PORT_STATUS 0x29c 259 #define ixCLIENT3_OFFSET_HI 0x2a0 260 #define ixCLIENT3_K0 0x2a4 261 #define ixCLIENT3_K1 0x2a8 262 #define ixCLIENT3_K2 0x2ac 263 #define ixCLIENT3_K3 0x2b0 264 #define ixCLIENT3_CK0 0x2b4 265 #define ixCLIENT3_CK1 0x2b8 266 #define ixCLIENT3_CK2 0x2bc 267 #define ixCLIENT3_CK3 0x2c0 268 #define ixCLIENT3_CD0 0x2c4 269 #define ixCLIENT3_CD1 0x2c8 270 #define ixCLIENT3_CD2 0x2cc 271 #define ixCLIENT3_CD3 0x2d0 272 #define ixCLIENT3_BM 0x2d4 273 #define ixCLIENT3_OFFSET 0x2d8 274 #define ixCLIENT3_STATUS 0x2dc 275 #define ixCLIENT4_OFFSET_HI 0x2e0 276 #define ixCLIENT4_K0 0x2e4 277 #define ixCLIENT4_K1 0x2e8 278 #define ixCLIENT4_K2 0x2ec 279 #define ixCLIENT4_K3 0x2f0 280 #define ixCLIENT4_CK0 0x2f4 281 #define ixCLIENT4_CK1 0x2f8 282 #define ixCLIENT4_CK2 0x2fc 283 #define ixCLIENT4_CK3 0x300 284 #define ixCLIENT4_CD0 0x304 285 #define ixCLIENT4_CD1 0x308 286 #define ixCLIENT4_CD2 0x30c 287 #define ixCLIENT4_CD3 0x310 288 #define ixCLIENT4_BM 0x314 289 #define ixCLIENT4_OFFSET 0x318 290 #define ixCLIENT4_STATUS 0x31c 291 #define mmDC_TEST_DEBUG_INDEX 0x157c 292 #define mmDC_TEST_DEBUG_DATA 0x157d 293 #define mmSDMA0_UCODE_ADDR 0x3400 294 #define mmSDMA0_UCODE_DATA 0x3401 295 #define mmSDMA0_POWER_CNTL 0x3402 296 #define mmSDMA0_CLK_CTRL 0x3403 297 #define mmSDMA0_CNTL 0x3404 298 #define mmSDMA0_CHICKEN_BITS 0x3405 299 #define mmSDMA0_TILING_CONFIG 0x3406 300 #define mmSDMA0_HASH 0x3407 301 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 302 #define mmSDMA0_RB_RPTR_FETCH 0x340a 303 #define mmSDMA0_IB_OFFSET_FETCH 0x340b 304 #define mmSDMA0_PROGRAM 0x340c 305 #define mmSDMA0_STATUS_REG 0x340d 306 #define mmSDMA0_STATUS1_REG 0x340e 307 #define mmSDMA0_RD_BURST_CNTL 0x340f 308 #define mmSDMA0_PERFMON_CNTL 0x9000 309 #define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 310 #define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 311 #define mmSDMA0_F32_CNTL 0x3412 312 #define mmSDMA0_FREEZE 0x3413 313 #define mmSDMA0_PHASE0_QUANTUM 0x3414 314 #define mmSDMA0_PHASE1_QUANTUM 0x3415 315 #define mmSDMA_POWER_GATING 0x3416 316 #define mmSDMA_PGFSM_CONFIG 0x3417 317 #define mmSDMA_PGFSM_WRITE 0x3418 318 #define mmSDMA_PGFSM_READ 0x3419 319 #define mmSDMA0_EDC_CONFIG 0x341a 320 #define mmSDMA0_VM_CNTL 0x3420 321 #define mmSDMA0_VM_CTX_LO 0x3421 322 #define mmSDMA0_VM_CTX_HI 0x3422 323 #define mmSDMA0_STATUS2_REG 0x3423 324 #define mmSDMA0_ACTIVE_FCN_ID 0x3424 325 #define mmSDMA0_VM_CTX_CNTL 0x3425 326 #define mmSDMA0_VIRT_RESET_REQ 0x3426 327 #define mmSDMA0_VF_ENABLE 0x3427 328 #define mmSDMA0_BA_THRESHOLD 0x341b 329 #define mmSDMA0_ID 0x341c 330 #define mmSDMA0_VERSION 0x341d 331 #define mmSDMA0_ATOMIC_CNTL 0x3428 332 #define mmSDMA0_ATOMIC_PREOP_LO 0x3429 333 #define mmSDMA0_ATOMIC_PREOP_HI 0x342a 334 #define mmSDMA0_POWER_CNTL_IDLE 0x342c 335 #define mmSDMA0_PERF_REG_TYPE0 0x3477 336 #define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 337 #define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 338 #define mmSDMA0_CONTEXT_REG_TYPE2 0x347a 339 #define mmSDMA0_PUB_REG_TYPE0 0x347c 340 #define mmSDMA0_PUB_REG_TYPE1 0x347d 341 #define mmSDMA0_GFX_RB_CNTL 0x3480 342 #define mmSDMA0_GFX_RB_BASE 0x3481 343 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 344 #define mmSDMA0_GFX_RB_RPTR 0x3483 345 #define mmSDMA0_GFX_RB_WPTR 0x3484 346 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 347 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 348 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 349 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 350 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 351 #define mmSDMA0_GFX_IB_CNTL 0x348a 352 #define mmSDMA0_GFX_IB_RPTR 0x348b 353 #define mmSDMA0_GFX_IB_OFFSET 0x348c 354 #define mmSDMA0_GFX_IB_BASE_LO 0x348d 355 #define mmSDMA0_GFX_IB_BASE_HI 0x348e 356 #define mmSDMA0_GFX_IB_SIZE 0x348f 357 #define mmSDMA0_GFX_SKIP_CNTL 0x3490 358 #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 359 #define mmSDMA0_GFX_DOORBELL 0x3492 360 #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 361 #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 362 #define mmSDMA0_GFX_APE1_CNTL 0x34a8 363 #define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 364 #define mmSDMA0_GFX_WATERMARK 0x34aa 365 #define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac 366 #define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad 367 #define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af 368 #define mmSDMA0_GFX_PREEMPT 0x34b0 369 #define mmSDMA0_GFX_DUMMY_REG 0x34b1 370 #define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 371 #define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 372 #define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 373 #define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 374 #define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 375 #define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 376 #define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7 377 #define mmSDMA0_RLC0_RB_CNTL 0x3500 378 #define mmSDMA0_RLC0_RB_BASE 0x3501 379 #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 380 #define mmSDMA0_RLC0_RB_RPTR 0x3503 381 #define mmSDMA0_RLC0_RB_WPTR 0x3504 382 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 383 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 384 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 385 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 386 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 387 #define mmSDMA0_RLC0_IB_CNTL 0x350a 388 #define mmSDMA0_RLC0_IB_RPTR 0x350b 389 #define mmSDMA0_RLC0_IB_OFFSET 0x350c 390 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d 391 #define mmSDMA0_RLC0_IB_BASE_HI 0x350e 392 #define mmSDMA0_RLC0_IB_SIZE 0x350f 393 #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 394 #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 395 #define mmSDMA0_RLC0_DOORBELL 0x3512 396 #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 397 #define mmSDMA0_RLC0_APE1_CNTL 0x3528 398 #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 399 #define mmSDMA0_RLC0_WATERMARK 0x352a 400 #define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c 401 #define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d 402 #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f 403 #define mmSDMA0_RLC0_PREEMPT 0x3530 404 #define mmSDMA0_RLC0_DUMMY_REG 0x3531 405 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 406 #define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 407 #define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 408 #define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 409 #define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 410 #define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 411 #define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547 412 #define mmSDMA0_RLC1_RB_CNTL 0x3580 413 #define mmSDMA0_RLC1_RB_BASE 0x3581 414 #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 415 #define mmSDMA0_RLC1_RB_RPTR 0x3583 416 #define mmSDMA0_RLC1_RB_WPTR 0x3584 417 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 418 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 419 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 420 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 421 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 422 #define mmSDMA0_RLC1_IB_CNTL 0x358a 423 #define mmSDMA0_RLC1_IB_RPTR 0x358b 424 #define mmSDMA0_RLC1_IB_OFFSET 0x358c 425 #define mmSDMA0_RLC1_IB_BASE_LO 0x358d 426 #define mmSDMA0_RLC1_IB_BASE_HI 0x358e 427 #define mmSDMA0_RLC1_IB_SIZE 0x358f 428 #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 429 #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 430 #define mmSDMA0_RLC1_DOORBELL 0x3592 431 #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 432 #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 433 #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 434 #define mmSDMA0_RLC1_WATERMARK 0x35aa 435 #define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac 436 #define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad 437 #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af 438 #define mmSDMA0_RLC1_PREEMPT 0x35b0 439 #define mmSDMA0_RLC1_DUMMY_REG 0x35b1 440 #define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 441 #define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 442 #define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 443 #define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 444 #define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 445 #define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 446 #define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7 447 #define mmSDMA1_UCODE_ADDR 0x3600 448 #define mmSDMA1_UCODE_DATA 0x3601 449 #define mmSDMA1_POWER_CNTL 0x3602 450 #define mmSDMA1_CLK_CTRL 0x3603 451 #define mmSDMA1_CNTL 0x3604 452 #define mmSDMA1_CHICKEN_BITS 0x3605 453 #define mmSDMA1_TILING_CONFIG 0x3606 454 #define mmSDMA1_HASH 0x3607 455 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 456 #define mmSDMA1_RB_RPTR_FETCH 0x360a 457 #define mmSDMA1_IB_OFFSET_FETCH 0x360b 458 #define mmSDMA1_PROGRAM 0x360c 459 #define mmSDMA1_STATUS_REG 0x360d 460 #define mmSDMA1_STATUS1_REG 0x360e 461 #define mmSDMA1_RD_BURST_CNTL 0x360f 462 #define mmSDMA1_PERFMON_CNTL 0x9010 463 #define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 464 #define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 465 #define mmSDMA1_F32_CNTL 0x3612 466 #define mmSDMA1_FREEZE 0x3613 467 #define mmSDMA1_PHASE0_QUANTUM 0x3614 468 #define mmSDMA1_PHASE1_QUANTUM 0x3615 469 #define mmSDMA1_EDC_CONFIG 0x361a 470 #define mmSDMA1_VM_CNTL 0x3620 471 #define mmSDMA1_VM_CTX_LO 0x3621 472 #define mmSDMA1_VM_CTX_HI 0x3622 473 #define mmSDMA1_STATUS2_REG 0x3623 474 #define mmSDMA1_ACTIVE_FCN_ID 0x3624 475 #define mmSDMA1_VM_CTX_CNTL 0x3625 476 #define mmSDMA1_VIRT_RESET_REQ 0x3626 477 #define mmSDMA1_VF_ENABLE 0x3627 478 #define mmSDMA1_BA_THRESHOLD 0x361b 479 #define mmSDMA1_ID 0x361c 480 #define mmSDMA1_VERSION 0x361d 481 #define mmSDMA1_ATOMIC_CNTL 0x3628 482 #define mmSDMA1_ATOMIC_PREOP_LO 0x3629 483 #define mmSDMA1_ATOMIC_PREOP_HI 0x362a 484 #define mmSDMA1_POWER_CNTL_IDLE 0x362c 485 #define mmSDMA1_PERF_REG_TYPE0 0x3677 486 #define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 487 #define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 488 #define mmSDMA1_CONTEXT_REG_TYPE2 0x367a 489 #define mmSDMA1_PUB_REG_TYPE0 0x367c 490 #define mmSDMA1_PUB_REG_TYPE1 0x367d 491 #define mmSDMA1_GFX_RB_CNTL 0x3680 492 #define mmSDMA1_GFX_RB_BASE 0x3681 493 #define mmSDMA1_GFX_RB_BASE_HI 0x3682 494 #define mmSDMA1_GFX_RB_RPTR 0x3683 495 #define mmSDMA1_GFX_RB_WPTR 0x3684 496 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 497 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 498 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 499 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 500 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 501 #define mmSDMA1_GFX_IB_CNTL 0x368a 502 #define mmSDMA1_GFX_IB_RPTR 0x368b 503 #define mmSDMA1_GFX_IB_OFFSET 0x368c 504 #define mmSDMA1_GFX_IB_BASE_LO 0x368d 505 #define mmSDMA1_GFX_IB_BASE_HI 0x368e 506 #define mmSDMA1_GFX_IB_SIZE 0x368f 507 #define mmSDMA1_GFX_SKIP_CNTL 0x3690 508 #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 509 #define mmSDMA1_GFX_DOORBELL 0x3692 510 #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 511 #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 512 #define mmSDMA1_GFX_APE1_CNTL 0x36a8 513 #define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 514 #define mmSDMA1_GFX_WATERMARK 0x36aa 515 #define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac 516 #define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad 517 #define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af 518 #define mmSDMA1_GFX_PREEMPT 0x36b0 519 #define mmSDMA1_GFX_DUMMY_REG 0x36b1 520 #define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 521 #define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 522 #define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 523 #define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 524 #define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 525 #define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 526 #define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7 527 #define mmSDMA1_RLC0_RB_CNTL 0x3700 528 #define mmSDMA1_RLC0_RB_BASE 0x3701 529 #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 530 #define mmSDMA1_RLC0_RB_RPTR 0x3703 531 #define mmSDMA1_RLC0_RB_WPTR 0x3704 532 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 533 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 534 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 535 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 536 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 537 #define mmSDMA1_RLC0_IB_CNTL 0x370a 538 #define mmSDMA1_RLC0_IB_RPTR 0x370b 539 #define mmSDMA1_RLC0_IB_OFFSET 0x370c 540 #define mmSDMA1_RLC0_IB_BASE_LO 0x370d 541 #define mmSDMA1_RLC0_IB_BASE_HI 0x370e 542 #define mmSDMA1_RLC0_IB_SIZE 0x370f 543 #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 544 #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 545 #define mmSDMA1_RLC0_DOORBELL 0x3712 546 #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 547 #define mmSDMA1_RLC0_APE1_CNTL 0x3728 548 #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 549 #define mmSDMA1_RLC0_WATERMARK 0x372a 550 #define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c 551 #define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d 552 #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f 553 #define mmSDMA1_RLC0_PREEMPT 0x3730 554 #define mmSDMA1_RLC0_DUMMY_REG 0x3731 555 #define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 556 #define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 557 #define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 558 #define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 559 #define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 560 #define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 561 #define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747 562 #define mmSDMA1_RLC1_RB_CNTL 0x3780 563 #define mmSDMA1_RLC1_RB_BASE 0x3781 564 #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 565 #define mmSDMA1_RLC1_RB_RPTR 0x3783 566 #define mmSDMA1_RLC1_RB_WPTR 0x3784 567 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 568 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 569 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 570 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 571 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 572 #define mmSDMA1_RLC1_IB_CNTL 0x378a 573 #define mmSDMA1_RLC1_IB_RPTR 0x378b 574 #define mmSDMA1_RLC1_IB_OFFSET 0x378c 575 #define mmSDMA1_RLC1_IB_BASE_LO 0x378d 576 #define mmSDMA1_RLC1_IB_BASE_HI 0x378e 577 #define mmSDMA1_RLC1_IB_SIZE 0x378f 578 #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 579 #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 580 #define mmSDMA1_RLC1_DOORBELL 0x3792 581 #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 582 #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 583 #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 584 #define mmSDMA1_RLC1_WATERMARK 0x37aa 585 #define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac 586 #define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad 587 #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af 588 #define mmSDMA1_RLC1_PREEMPT 0x37b0 589 #define mmSDMA1_RLC1_DUMMY_REG 0x37b1 590 #define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 591 #define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 592 #define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 593 #define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 594 #define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 595 #define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 596 #define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7 597 #define mmHDP_HOST_PATH_CNTL 0xb00 598 #define mmHDP_NONSURFACE_BASE 0xb01 599 #define mmHDP_NONSURFACE_INFO 0xb02 600 #define mmHDP_NONSURFACE_SIZE 0xb03 601 #define mmHDP_NONSURF_FLAGS 0xbc9 602 #define mmHDP_NONSURF_FLAGS_CLR 0xbca 603 #define mmHDP_SW_SEMAPHORE 0xbcb 604 #define mmHDP_DEBUG0 0xbcc 605 #define mmHDP_DEBUG1 0xbcd 606 #define mmHDP_LAST_SURFACE_HIT 0xbce 607 #define mmHDP_TILING_CONFIG 0xbcf 608 #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 609 #define mmHDP_OUTSTANDING_REQ 0xbd1 610 #define mmHDP_ADDR_CONFIG 0xbd2 611 #define mmHDP_MISC_CNTL 0xbd3 612 #define mmHDP_MEM_POWER_LS 0xbd4 613 #define mmHDP_NONSURFACE_PREFETCH 0xbd5 614 #define mmHDP_MEMIO_CNTL 0xbf6 615 #define mmHDP_MEMIO_ADDR 0xbf7 616 #define mmHDP_MEMIO_STATUS 0xbf8 617 #define mmHDP_MEMIO_WR_DATA 0xbf9 618 #define mmHDP_MEMIO_RD_DATA 0xbfa 619 #define mmHDP_VF_ENABLE 0xbfb 620 #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 621 #define mmHDP_XDP_D2H_FLUSH 0xc01 622 #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 623 #define mmHDP_XDP_D2H_RSVD_3 0xc03 624 #define mmHDP_XDP_D2H_RSVD_4 0xc04 625 #define mmHDP_XDP_D2H_RSVD_5 0xc05 626 #define mmHDP_XDP_D2H_RSVD_6 0xc06 627 #define mmHDP_XDP_D2H_RSVD_7 0xc07 628 #define mmHDP_XDP_D2H_RSVD_8 0xc08 629 #define mmHDP_XDP_D2H_RSVD_9 0xc09 630 #define mmHDP_XDP_D2H_RSVD_10 0xc0a 631 #define mmHDP_XDP_D2H_RSVD_11 0xc0b 632 #define mmHDP_XDP_D2H_RSVD_12 0xc0c 633 #define mmHDP_XDP_D2H_RSVD_13 0xc0d 634 #define mmHDP_XDP_D2H_RSVD_14 0xc0e 635 #define mmHDP_XDP_D2H_RSVD_15 0xc0f 636 #define mmHDP_XDP_D2H_RSVD_16 0xc10 637 #define mmHDP_XDP_D2H_RSVD_17 0xc11 638 #define mmHDP_XDP_D2H_RSVD_18 0xc12 639 #define mmHDP_XDP_D2H_RSVD_19 0xc13 640 #define mmHDP_XDP_D2H_RSVD_20 0xc14 641 #define mmHDP_XDP_D2H_RSVD_21 0xc15 642 #define mmHDP_XDP_D2H_RSVD_22 0xc16 643 #define mmHDP_XDP_D2H_RSVD_23 0xc17 644 #define mmHDP_XDP_D2H_RSVD_24 0xc18 645 #define mmHDP_XDP_D2H_RSVD_25 0xc19 646 #define mmHDP_XDP_D2H_RSVD_26 0xc1a 647 #define mmHDP_XDP_D2H_RSVD_27 0xc1b 648 #define mmHDP_XDP_D2H_RSVD_28 0xc1c 649 #define mmHDP_XDP_D2H_RSVD_29 0xc1d 650 #define mmHDP_XDP_D2H_RSVD_30 0xc1e 651 #define mmHDP_XDP_D2H_RSVD_31 0xc1f 652 #define mmHDP_XDP_D2H_RSVD_32 0xc20 653 #define mmHDP_XDP_D2H_RSVD_33 0xc21 654 #define mmHDP_XDP_D2H_RSVD_34 0xc22 655 #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 656 #define mmHDP_XDP_P2P_BAR_CFG 0xc24 657 #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 658 #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 659 #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 660 #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 661 #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 662 #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a 663 #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b 664 #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c 665 #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d 666 #define mmHDP_XDP_HDP_MC_CFG 0xc2e 667 #define mmHDP_XDP_HST_CFG 0xc2f 668 #define mmHDP_XDP_SID_CFG 0xc30 669 #define mmHDP_XDP_HDP_IPH_CFG 0xc31 670 #define mmHDP_XDP_SRBM_CFG 0xc32 671 #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 672 #define mmHDP_XDP_P2P_BAR0 0xc34 673 #define mmHDP_XDP_P2P_BAR1 0xc35 674 #define mmHDP_XDP_P2P_BAR2 0xc36 675 #define mmHDP_XDP_P2P_BAR3 0xc37 676 #define mmHDP_XDP_P2P_BAR4 0xc38 677 #define mmHDP_XDP_P2P_BAR5 0xc39 678 #define mmHDP_XDP_P2P_BAR6 0xc3a 679 #define mmHDP_XDP_P2P_BAR7 0xc3b 680 #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c 681 #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d 682 #define mmHDP_XDP_BUSY_STS 0xc3e 683 #define mmHDP_XDP_STICKY 0xc3f 684 #define mmHDP_XDP_CHKN 0xc40 685 #define mmHDP_XDP_DBG_ADDR 0xc41 686 #define mmHDP_XDP_DBG_DATA 0xc42 687 #define mmHDP_XDP_DBG_MASK 0xc43 688 #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 689 690 #endif /* OSS_3_0_D_H */ 691