1 /* $NetBSD: osssys_4_0_sh_mask.h,v 1.2 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _osssys_4_0_SH_MASK_HEADER 24 #define _osssys_4_0_SH_MASK_HEADER 25 26 27 // addressBlock: osssys_osssysdec 28 //IH_VMID_0_LUT 29 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 30 #define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL 31 //IH_VMID_1_LUT 32 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL 34 //IH_VMID_2_LUT 35 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 36 #define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL 37 //IH_VMID_3_LUT 38 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 39 #define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL 40 //IH_VMID_4_LUT 41 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 42 #define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL 43 //IH_VMID_5_LUT 44 #define IH_VMID_5_LUT__PASID__SHIFT 0x0 45 #define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL 46 //IH_VMID_6_LUT 47 #define IH_VMID_6_LUT__PASID__SHIFT 0x0 48 #define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL 49 //IH_VMID_7_LUT 50 #define IH_VMID_7_LUT__PASID__SHIFT 0x0 51 #define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL 52 //IH_VMID_8_LUT 53 #define IH_VMID_8_LUT__PASID__SHIFT 0x0 54 #define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL 55 //IH_VMID_9_LUT 56 #define IH_VMID_9_LUT__PASID__SHIFT 0x0 57 #define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL 58 //IH_VMID_10_LUT 59 #define IH_VMID_10_LUT__PASID__SHIFT 0x0 60 #define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL 61 //IH_VMID_11_LUT 62 #define IH_VMID_11_LUT__PASID__SHIFT 0x0 63 #define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL 64 //IH_VMID_12_LUT 65 #define IH_VMID_12_LUT__PASID__SHIFT 0x0 66 #define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL 67 //IH_VMID_13_LUT 68 #define IH_VMID_13_LUT__PASID__SHIFT 0x0 69 #define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL 70 //IH_VMID_14_LUT 71 #define IH_VMID_14_LUT__PASID__SHIFT 0x0 72 #define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL 73 //IH_VMID_15_LUT 74 #define IH_VMID_15_LUT__PASID__SHIFT 0x0 75 #define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL 76 //IH_VMID_0_LUT_MM 77 #define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 78 #define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL 79 //IH_VMID_1_LUT_MM 80 #define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 81 #define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL 82 //IH_VMID_2_LUT_MM 83 #define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 84 #define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL 85 //IH_VMID_3_LUT_MM 86 #define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 87 #define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL 88 //IH_VMID_4_LUT_MM 89 #define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 90 #define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL 91 //IH_VMID_5_LUT_MM 92 #define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 93 #define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL 94 //IH_VMID_6_LUT_MM 95 #define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 96 #define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL 97 //IH_VMID_7_LUT_MM 98 #define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 99 #define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL 100 //IH_VMID_8_LUT_MM 101 #define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 102 #define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL 103 //IH_VMID_9_LUT_MM 104 #define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 105 #define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL 106 //IH_VMID_10_LUT_MM 107 #define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 108 #define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL 109 //IH_VMID_11_LUT_MM 110 #define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 111 #define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL 112 //IH_VMID_12_LUT_MM 113 #define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 114 #define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL 115 //IH_VMID_13_LUT_MM 116 #define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 117 #define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL 118 //IH_VMID_14_LUT_MM 119 #define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 120 #define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL 121 //IH_VMID_15_LUT_MM 122 #define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 123 #define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL 124 //IH_COOKIE_0 125 #define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 126 #define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 127 #define IH_COOKIE_0__RING_ID__SHIFT 0x10 128 #define IH_COOKIE_0__VM_ID__SHIFT 0x18 129 #define IH_COOKIE_0__RESERVED__SHIFT 0x1c 130 #define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f 131 #define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL 132 #define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L 133 #define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L 134 #define IH_COOKIE_0__VM_ID_MASK 0x0F000000L 135 #define IH_COOKIE_0__RESERVED_MASK 0x70000000L 136 #define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L 137 //IH_COOKIE_1 138 #define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 139 #define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL 140 //IH_COOKIE_2 141 #define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 142 #define IH_COOKIE_2__RESERVED__SHIFT 0x10 143 #define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f 144 #define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL 145 #define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L 146 #define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L 147 //IH_COOKIE_3 148 #define IH_COOKIE_3__PAS_ID__SHIFT 0x0 149 #define IH_COOKIE_3__RESERVED__SHIFT 0x10 150 #define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f 151 #define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL 152 #define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L 153 #define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L 154 //IH_COOKIE_4 155 #define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 156 #define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL 157 //IH_COOKIE_5 158 #define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 159 #define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL 160 //IH_COOKIE_6 161 #define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 162 #define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL 163 //IH_COOKIE_7 164 #define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 165 #define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL 166 //IH_REGISTER_LAST_PART0 167 #define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 168 #define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 169 //SEM_REQ_INPUT_0 170 #define SEM_REQ_INPUT_0__DATA__SHIFT 0x0 171 #define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL 172 //SEM_REQ_INPUT_1 173 #define SEM_REQ_INPUT_1__DATA__SHIFT 0x0 174 #define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL 175 //SEM_REQ_INPUT_2 176 #define SEM_REQ_INPUT_2__DATA__SHIFT 0x0 177 #define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL 178 //SEM_REQ_INPUT_3 179 #define SEM_REQ_INPUT_3__DATA__SHIFT 0x0 180 #define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL 181 //SEM_REGISTER_LAST_PART0 182 #define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 183 #define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 184 //IH_RB_CNTL 185 #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 186 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 187 #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 188 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 189 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 190 #define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa 191 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc 192 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 193 #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 194 #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 195 #define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 196 #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 197 #define IH_RB_CNTL__MC_RO__SHIFT 0x16 198 #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 199 #define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c 200 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 201 #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L 202 #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL 203 #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L 204 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L 205 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 206 #define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L 207 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 208 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 209 #define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L 210 #define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L 211 #define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L 212 #define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L 213 #define IH_RB_CNTL__MC_RO_MASK 0x00400000L 214 #define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L 215 #define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L 216 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 217 //IH_RB_BASE 218 #define IH_RB_BASE__ADDR__SHIFT 0x0 219 #define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL 220 //IH_RB_BASE_HI 221 #define IH_RB_BASE_HI__ADDR__SHIFT 0x0 222 #define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL 223 //IH_RB_RPTR 224 #define IH_RB_RPTR__OFFSET__SHIFT 0x2 225 #define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL 226 //IH_RB_WPTR 227 #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 228 #define IH_RB_WPTR__OFFSET__SHIFT 0x2 229 #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 230 #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 231 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L 232 #define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL 233 #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L 234 #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L 235 //IH_RB_WPTR_ADDR_HI 236 #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 237 #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL 238 //IH_RB_WPTR_ADDR_LO 239 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 240 #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 241 //IH_DOORBELL_RPTR 242 #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 243 #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 244 #define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL 245 #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L 246 //IH_RB_CNTL_RING1 247 #define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 248 #define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 249 #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 250 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 251 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa 252 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc 253 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 254 #define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 255 #define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 256 #define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 257 #define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 258 #define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c 259 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 260 #define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L 261 #define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL 262 #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L 263 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 264 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L 265 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 266 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 267 #define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L 268 #define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L 269 #define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L 270 #define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L 271 #define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L 272 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 273 //IH_RB_BASE_RING1 274 #define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 275 #define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL 276 //IH_RB_BASE_HI_RING1 277 #define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 278 #define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL 279 //IH_RB_RPTR_RING1 280 #define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 281 #define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL 282 //IH_RB_WPTR_RING1 283 #define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 284 #define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 285 #define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 286 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 287 #define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L 288 #define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL 289 #define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L 290 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L 291 //IH_DOORBELL_RPTR_RING1 292 #define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 293 #define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c 294 #define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL 295 #define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L 296 //IH_RB_CNTL_RING2 297 #define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0 298 #define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1 299 #define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7 300 #define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 301 #define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa 302 #define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc 303 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 304 #define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12 305 #define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14 306 #define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16 307 #define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18 308 #define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c 309 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 310 #define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L 311 #define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL 312 #define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L 313 #define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 314 #define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L 315 #define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 316 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 317 #define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L 318 #define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L 319 #define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L 320 #define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L 321 #define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L 322 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 323 //IH_RB_BASE_RING2 324 #define IH_RB_BASE_RING2__ADDR__SHIFT 0x0 325 #define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL 326 //IH_RB_BASE_HI_RING2 327 #define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0 328 #define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL 329 //IH_RB_RPTR_RING2 330 #define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2 331 #define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL 332 //IH_RB_WPTR_RING2 333 #define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0 334 #define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2 335 #define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12 336 #define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13 337 #define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L 338 #define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL 339 #define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L 340 #define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L 341 //IH_DOORBELL_RPTR_RING2 342 #define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0 343 #define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c 344 #define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL 345 #define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L 346 //IH_VERSION 347 #define IH_VERSION__MINVER__SHIFT 0x0 348 #define IH_VERSION__MAJVER__SHIFT 0x8 349 #define IH_VERSION__REV__SHIFT 0x10 350 #define IH_VERSION__MINVER_MASK 0x0000007FL 351 #define IH_VERSION__MAJVER_MASK 0x00007F00L 352 #define IH_VERSION__REV_MASK 0x003F0000L 353 //IH_CNTL 354 #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 355 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 356 #define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 357 #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 358 #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL 359 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L 360 #define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L 361 #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L 362 //IH_CNTL2 363 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 364 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 365 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x000000FFL 366 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L 367 //IH_STATUS 368 #define IH_STATUS__IDLE__SHIFT 0x0 369 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 370 #define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 371 #define IH_STATUS__RB_FULL__SHIFT 0x3 372 #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 373 #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 374 #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 375 #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 376 #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 377 #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 378 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 379 #define IH_STATUS__SWITCH_READY__SHIFT 0xb 380 #define IH_STATUS__RB1_FULL__SHIFT 0xc 381 #define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd 382 #define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe 383 #define IH_STATUS__RB2_FULL__SHIFT 0xf 384 #define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10 385 #define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11 386 #define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 387 #define IH_STATUS__IDLE_MASK 0x00000001L 388 #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L 389 #define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L 390 #define IH_STATUS__RB_FULL_MASK 0x00000008L 391 #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L 392 #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L 393 #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L 394 #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L 395 #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L 396 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L 397 #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L 398 #define IH_STATUS__SWITCH_READY_MASK 0x00000800L 399 #define IH_STATUS__RB1_FULL_MASK 0x00001000L 400 #define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L 401 #define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L 402 #define IH_STATUS__RB2_FULL_MASK 0x00008000L 403 #define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L 404 #define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L 405 #define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L 406 //IH_PERFMON_CNTL 407 #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 408 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 409 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 410 #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 411 #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 412 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 413 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L 414 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L 415 #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL 416 #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L 417 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L 418 #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L 419 //IH_PERFCOUNTER0_RESULT 420 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 421 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 422 //IH_PERFCOUNTER1_RESULT 423 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 424 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 425 //IH_DSM_MATCH_VALUE_BIT_31_0 426 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 427 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL 428 //IH_DSM_MATCH_VALUE_BIT_63_32 429 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 430 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL 431 //IH_DSM_MATCH_VALUE_BIT_95_64 432 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 433 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL 434 //IH_DSM_MATCH_FIELD_CONTROL 435 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 436 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 437 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 438 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 439 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 440 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 441 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 442 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L 443 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L 444 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L 445 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L 446 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L 447 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L 448 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L 449 //IH_DSM_MATCH_DATA_CONTROL 450 #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 451 #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL 452 //IH_DSM_MATCH_FCN_ID 453 #define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0 454 #define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1 455 #define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L 456 #define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL 457 //IH_LIMIT_INT_RATE_CNTL 458 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 459 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 460 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 461 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 462 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 463 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L 464 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL 465 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L 466 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L 467 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L 468 //IH_VF_RB_STATUS 469 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 470 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 471 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 472 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 473 //IH_VF_RB_STATUS2 474 #define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 475 #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 476 #define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 477 #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L 478 //IH_VF_RB1_STATUS 479 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 480 #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 481 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 482 #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 483 //IH_VF_RB1_STATUS2 484 #define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 485 #define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 486 //IH_VF_RB2_STATUS 487 #define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 488 #define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 489 #define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 490 #define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 491 //IH_VF_RB2_STATUS2 492 #define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0 493 #define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 494 //IH_INT_FLOOD_CNTL 495 #define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 496 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 497 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 498 #define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L 499 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L 500 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L 501 //IH_RB0_INT_FLOOD_STATUS 502 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 503 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 504 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 505 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 506 //IH_RB1_INT_FLOOD_STATUS 507 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 508 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 509 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 510 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 511 //IH_RB2_INT_FLOOD_STATUS 512 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 513 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 514 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 515 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 516 //IH_INT_FLOOD_STATUS 517 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 518 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 519 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 520 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 521 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c 522 #define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e 523 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL 524 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L 525 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L 526 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L 527 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L 528 #define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L 529 //IH_STORM_CLIENT_LIST_CNTL 530 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 531 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 532 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 533 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 534 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 535 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 536 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 537 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 538 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 539 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa 540 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb 541 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc 542 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd 543 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe 544 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf 545 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 546 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 547 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 548 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 549 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 550 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 551 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 552 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 553 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 554 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 555 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a 556 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b 557 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c 558 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d 559 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e 560 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f 561 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L 562 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L 563 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L 564 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L 565 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L 566 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L 567 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L 568 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L 569 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L 570 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L 571 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L 572 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L 573 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L 574 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L 575 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L 576 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L 577 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L 578 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L 579 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L 580 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L 581 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L 582 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L 583 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L 584 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L 585 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L 586 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L 587 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L 588 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L 589 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L 590 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L 591 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L 592 //IH_CLK_CTRL 593 #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 594 #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 595 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b 596 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c 597 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 598 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e 599 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 600 #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L 601 #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 602 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L 603 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L 604 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 605 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L 606 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 607 //IH_INT_FLAGS 608 #define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 609 #define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 610 #define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 611 #define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 612 #define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 613 #define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 614 #define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 615 #define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 616 #define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 617 #define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 618 #define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa 619 #define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb 620 #define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc 621 #define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd 622 #define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe 623 #define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf 624 #define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 625 #define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 626 #define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 627 #define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 628 #define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 629 #define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 630 #define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 631 #define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 632 #define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 633 #define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 634 #define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a 635 #define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b 636 #define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c 637 #define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d 638 #define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e 639 #define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f 640 #define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L 641 #define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L 642 #define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L 643 #define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L 644 #define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L 645 #define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L 646 #define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L 647 #define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L 648 #define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L 649 #define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L 650 #define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L 651 #define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L 652 #define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L 653 #define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L 654 #define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L 655 #define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L 656 #define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L 657 #define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L 658 #define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L 659 #define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L 660 #define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L 661 #define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L 662 #define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L 663 #define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L 664 #define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L 665 #define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L 666 #define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L 667 #define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L 668 #define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L 669 #define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L 670 #define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L 671 #define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L 672 //IH_LAST_INT_INFO0 673 #define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 674 #define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 675 #define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 676 #define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 677 #define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f 678 #define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL 679 #define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L 680 #define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L 681 #define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L 682 #define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L 683 //IH_LAST_INT_INFO1 684 #define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 685 #define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL 686 //IH_LAST_INT_INFO2 687 #define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 688 #define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 689 #define IH_LAST_INT_INFO2__VF__SHIFT 0x14 690 #define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL 691 #define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L 692 #define IH_LAST_INT_INFO2__VF_MASK 0x00100000L 693 //IH_SCRATCH 694 #define IH_SCRATCH__DATA__SHIFT 0x0 695 #define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL 696 //IH_CLIENT_CREDIT_ERROR 697 #define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 698 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 699 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 700 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 701 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 702 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 703 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 704 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 705 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 706 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 707 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa 708 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb 709 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc 710 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd 711 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe 712 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf 713 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 714 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 715 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 716 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 717 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 718 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 719 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 720 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 721 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 722 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 723 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a 724 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b 725 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c 726 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d 727 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e 728 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f 729 #define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L 730 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L 731 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L 732 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L 733 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L 734 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L 735 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L 736 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L 737 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L 738 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L 739 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L 740 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L 741 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L 742 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L 743 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L 744 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L 745 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L 746 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L 747 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L 748 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L 749 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L 750 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L 751 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L 752 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L 753 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L 754 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L 755 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L 756 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L 757 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L 758 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L 759 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L 760 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L 761 //IH_GPU_IOV_VIOLATION_LOG 762 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 763 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 764 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 765 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 766 #define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 767 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 768 #define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 769 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 770 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 771 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 772 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 773 #define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 774 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 775 #define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 776 //IH_COOKIE_REC_VIOLATION_LOG 777 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 778 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10 779 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 780 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 781 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L 782 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 783 //IH_CREDIT_STATUS 784 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 785 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 786 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 787 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 788 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 789 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 790 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 791 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 792 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 793 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa 794 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb 795 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc 796 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd 797 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe 798 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf 799 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 800 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 801 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 802 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 803 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 804 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 805 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 806 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 807 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 808 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 809 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a 810 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b 811 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c 812 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d 813 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e 814 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f 815 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L 816 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L 817 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L 818 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L 819 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L 820 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L 821 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L 822 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L 823 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L 824 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L 825 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L 826 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L 827 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L 828 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L 829 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L 830 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L 831 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L 832 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L 833 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L 834 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L 835 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L 836 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L 837 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L 838 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L 839 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L 840 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L 841 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L 842 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L 843 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L 844 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L 845 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L 846 //IH_MMHUB_ERROR 847 #define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 848 #define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 849 #define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 850 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 851 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 852 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 853 #define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L 854 #define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L 855 #define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L 856 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L 857 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L 858 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L 859 //IH_REGISTER_LAST_PART2 860 #define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 861 #define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 862 //SEM_CLK_CTRL 863 #define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0 864 #define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 865 #define SEM_CLK_CTRL__RESERVED__SHIFT 0xc 866 #define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 867 #define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 868 #define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 869 #define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 870 #define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 871 #define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 872 #define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 873 #define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 874 #define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 875 #define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 876 #define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L 877 #define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 878 #define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 879 #define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 880 #define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 881 #define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 882 #define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 883 #define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 884 #define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 885 //SEM_UTC_CREDIT 886 #define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0 887 #define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8 888 #define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL 889 #define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L 890 //SEM_UTC_CONFIG 891 #define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0 892 #define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3 893 #define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4 894 #define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5 895 #define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L 896 #define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L 897 #define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L 898 #define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L 899 //SEM_UTCL2_TRAN_EN_LUT 900 #define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0 901 #define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1 902 #define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2 903 #define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3 904 #define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4 905 #define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5 906 #define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6 907 #define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7 908 #define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8 909 #define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f 910 #define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L 911 #define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L 912 #define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L 913 #define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L 914 #define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L 915 #define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L 916 #define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L 917 #define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L 918 #define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L 919 #define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L 920 //SEM_MCIF_CONFIG 921 #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 922 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 923 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 924 #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L 925 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL 926 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L 927 //SEM_PERFMON_CNTL 928 #define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 929 #define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 930 #define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 931 #define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 932 #define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 933 #define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 934 #define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 935 #define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 936 #define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 937 #define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 938 #define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 939 #define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 940 //SEM_PERFCOUNTER0_RESULT 941 #define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 942 #define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 943 //SEM_PERFCOUNTER1_RESULT 944 #define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 945 #define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 946 //SEM_STATUS 947 #define SEM_STATUS__SEM_IDLE__SHIFT 0x0 948 #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 949 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 950 #define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 951 #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 952 #define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 953 #define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 954 #define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 955 #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 956 #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 957 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 958 #define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 959 #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 960 #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 961 #define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 962 #define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf 963 #define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10 964 #define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11 965 #define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12 966 #define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13 967 #define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14 968 #define SEM_STATUS__MIF_IDLE__SHIFT 0x15 969 #define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16 970 #define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17 971 #define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 972 #define SEM_STATUS__SEM_IDLE_MASK 0x00000001L 973 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L 974 #define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L 975 #define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L 976 #define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L 977 #define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L 978 #define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L 979 #define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L 980 #define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L 981 #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L 982 #define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L 983 #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L 984 #define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L 985 #define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L 986 #define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L 987 #define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L 988 #define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L 989 #define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L 990 #define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L 991 #define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L 992 #define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L 993 #define SEM_STATUS__MIF_IDLE_MASK 0x00200000L 994 #define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L 995 #define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L 996 #define SEM_STATUS__SWITCH_READY_MASK 0x80000000L 997 //SEM_MAILBOX_CLIENTCONFIG 998 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 999 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 1000 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 1001 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 1002 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 1003 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 1004 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 1005 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 1006 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L 1007 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L 1008 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L 1009 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L 1010 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L 1011 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L 1012 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L 1013 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L 1014 //SEM_MAILBOX 1015 #define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 1016 #define SEM_MAILBOX__RESERVED__SHIFT 0x10 1017 #define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL 1018 #define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L 1019 //SEM_MAILBOX_CONTROL 1020 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0 1021 #define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10 1022 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL 1023 #define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L 1024 //SEM_CHICKEN_BITS 1025 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 1026 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 1027 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 1028 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 1029 #define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 1030 #define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 1031 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 1032 #define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa 1033 #define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc 1034 #define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe 1035 #define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf 1036 #define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10 1037 #define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12 1038 #define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13 1039 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L 1040 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L 1041 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L 1042 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L 1043 #define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L 1044 #define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L 1045 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L 1046 #define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L 1047 #define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L 1048 #define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L 1049 #define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L 1050 #define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L 1051 #define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L 1052 #define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L 1053 //SEM_MAILBOX_CLIENTCONFIG_EXTRA 1054 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 1055 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL 1056 //SEM_GPU_IOV_VIOLATION_LOG 1057 #define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1058 #define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1059 #define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1060 #define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 1061 #define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1062 #define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 1063 #define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1064 #define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1065 #define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1066 #define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1067 #define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 1068 #define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1069 #define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 1070 #define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1071 //SEM_OUTSTANDING_THRESHOLD 1072 #define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0 1073 #define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL 1074 //SEM_REGISTER_LAST_PART2 1075 #define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 1076 #define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 1077 //IH_ACTIVE_FCN_ID 1078 #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 1079 #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 1080 #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 1081 #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL 1082 #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 1083 #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 1084 //IH_VIRT_RESET_REQ 1085 #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 1086 #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 1087 #define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1088 #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L 1089 //IH_CLIENT_CFG 1090 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 1091 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL 1092 //IH_CLIENT_CFG_INDEX 1093 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 1094 #define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL 1095 //IH_CLIENT_CFG_DATA 1096 #define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0 1097 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 1098 #define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 1099 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 1100 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 1101 #define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001FFFFL 1102 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L 1103 #define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L 1104 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L 1105 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L 1106 //IH_CID_REMAP_INDEX 1107 #define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1108 #define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1109 //IH_CID_REMAP_DATA 1110 #define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1111 #define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1112 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1113 #define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1114 #define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1115 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1116 //IH_CHICKEN 1117 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1118 #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 1119 #define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 1120 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1121 #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L 1122 #define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L 1123 //IH_MMHUB_CNTL 1124 #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 1125 #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 1126 #define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc 1127 #define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL 1128 #define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L 1129 #define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L 1130 //IH_REGISTER_LAST_PART1 1131 #define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1132 #define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1133 //SEM_ACTIVE_FCN_ID 1134 #define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1135 #define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1136 #define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 1137 #define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L 1138 //SEM_VIRT_RESET_REQ 1139 #define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 1140 #define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 1141 #define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1142 #define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L 1143 //SEM_RESP_SDMA0 1144 #define SEM_RESP_SDMA0__ADDR__SHIFT 0x2 1145 #define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL 1146 //SEM_RESP_SDMA1 1147 #define SEM_RESP_SDMA1__ADDR__SHIFT 0x2 1148 #define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL 1149 //SEM_RESP_UVD 1150 #define SEM_RESP_UVD__ADDR__SHIFT 0x2 1151 #define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL 1152 //SEM_RESP_VCE_0 1153 #define SEM_RESP_VCE_0__ADDR__SHIFT 0x2 1154 #define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL 1155 //SEM_RESP_ACP 1156 #define SEM_RESP_ACP__ADDR__SHIFT 0x2 1157 #define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL 1158 //SEM_RESP_ISP 1159 #define SEM_RESP_ISP__ADDR__SHIFT 0x2 1160 #define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL 1161 //SEM_RESP_VCE_1 1162 #define SEM_RESP_VCE_1__ADDR__SHIFT 0x2 1163 #define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL 1164 //SEM_RESP_VP8 1165 #define SEM_RESP_VP8__ADDR__SHIFT 0x2 1166 #define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL 1167 //SEM_RESP_GC 1168 #define SEM_RESP_GC__ADDR__SHIFT 0x2 1169 #define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL 1170 //SEM_CID_REMAP_INDEX 1171 #define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1172 #define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1173 //SEM_CID_REMAP_DATA 1174 #define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1175 #define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1176 #define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1177 #define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1178 #define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1179 #define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1180 //SEM_ATOMIC_OP_LUT 1181 #define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0 1182 #define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7 1183 #define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe 1184 #define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15 1185 #define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL 1186 #define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L 1187 #define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L 1188 #define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L 1189 //SEM_EDC_CONFIG 1190 #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1191 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 1192 //SEM_CHICKEN_BITS2 1193 #define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1194 #define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1 1195 #define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1196 #define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L 1197 //SEM_MMHUB_CNTL 1198 #define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 1199 #define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8 1200 #define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 1201 #define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L 1202 //SEM_REGISTER_LAST_PART1 1203 #define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1204 #define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1205 1206 #endif 1207