1 /* $NetBSD: oss_3_0_1_d.h,v 1.3 2021/12/18 23:45:22 riastradh Exp $ */ 2 3 /* 4 * OSS_3_0_1 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef OSS_3_0_1_D_H 27 #define OSS_3_0_1_D_H 28 29 #define mmIH_VMID_0_LUT 0xe00 30 #define mmIH_VMID_1_LUT 0xe01 31 #define mmIH_VMID_2_LUT 0xe02 32 #define mmIH_VMID_3_LUT 0xe03 33 #define mmIH_VMID_4_LUT 0xe04 34 #define mmIH_VMID_5_LUT 0xe05 35 #define mmIH_VMID_6_LUT 0xe06 36 #define mmIH_VMID_7_LUT 0xe07 37 #define mmIH_VMID_8_LUT 0xe08 38 #define mmIH_VMID_9_LUT 0xe09 39 #define mmIH_VMID_10_LUT 0xe0a 40 #define mmIH_VMID_11_LUT 0xe0b 41 #define mmIH_VMID_12_LUT 0xe0c 42 #define mmIH_VMID_13_LUT 0xe0d 43 #define mmIH_VMID_14_LUT 0xe0e 44 #define mmIH_VMID_15_LUT 0xe0f 45 #define mmIH_RB_CNTL 0xe30 46 #define mmIH_RB_BASE 0xe31 47 #define mmIH_RB_RPTR 0xe32 48 #define mmIH_RB_WPTR 0xe33 49 #define mmIH_RB_WPTR_ADDR_HI 0xe34 50 #define mmIH_RB_WPTR_ADDR_LO 0xe35 51 #define mmIH_CNTL 0xe36 52 #define mmIH_LEVEL_STATUS 0xe37 53 #define mmIH_STATUS 0xe38 54 #define mmIH_PERFMON_CNTL 0xe39 55 #define mmIH_PERFCOUNTER0_RESULT 0xe3a 56 #define mmIH_PERFCOUNTER1_RESULT 0xe3b 57 #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d 58 #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e 59 #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f 60 #define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 61 #define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 62 #define mmIH_VERSION 0xe48 63 #define mmSEM_MCIF_CONFIG 0xf90 64 #define mmSEM_PERFMON_CNTL 0xf91 65 #define mmSEM_PERFCOUNTER0_RESULT 0xf92 66 #define mmSEM_PERFCOUNTER1_RESULT 0xf93 67 #define mmSEM_VF_ENABLE 0xf95 68 #define mmSEM_ACTIVE_FCN_ID 0xf97 69 #define mmSEM_VIRT_RESET_REQ 0xf98 70 #define mmSEM_STATUS 0xf99 71 #define mmSEM_EDC_CONFIG 0xf9a 72 #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b 73 #define mmSEM_MAILBOX 0xf9c 74 #define mmSEM_MAILBOX_CONTROL 0xf9d 75 #define mmSEM_CHICKEN_BITS 0xf9e 76 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f 77 #define mmSRBM_CNTL 0x390 78 #define mmSRBM_GFX_CNTL 0x391 79 #define mmSRBM_READ_CNTL 0x392 80 #define mmSRBM_STATUS2 0x393 81 #define mmSRBM_STATUS 0x394 82 #define mmSRBM_STATUS3 0x395 83 #define mmSRBM_SOFT_RESET 0x398 84 #define mmSRBM_DEBUG_CNTL 0x399 85 #define mmSRBM_DEBUG_DATA 0x39a 86 #define mmSRBM_CHIP_REVISION 0x39b 87 #define mmCC_SYS_RB_REDUNDANCY 0x39f 88 #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 89 #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 90 #define mmSRBM_MC_CLKEN_CNTL 0x3b3 91 #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 92 #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 93 #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 94 #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 95 #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 96 #define mmSRBM_ISP_CLKEN_CNTL 0x3b9 97 #define mmSRBM_VP8_CLKEN_CNTL 0x3ba 98 #define mmSRBM_DEBUG 0x3a4 99 #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 100 #define mmSRBM_DEBUG_SNAPSHOT2 0x3ad 101 #define mmSRBM_READ_ERROR 0x3a6 102 #define mmSRBM_READ_ERROR2 0x3ae 103 #define mmSRBM_INT_CNTL 0x3a8 104 #define mmSRBM_INT_STATUS 0x3a9 105 #define mmSRBM_INT_ACK 0x3aa 106 #define mmSRBM_FIREWALL_ERROR_SRC 0x3ab 107 #define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac 108 #define mmSRBM_DSM_TRIG_CNTL0 0x3af 109 #define mmSRBM_DSM_TRIG_CNTL1 0x3b0 110 #define mmSRBM_DSM_TRIG_MASK0 0x3b1 111 #define mmSRBM_DSM_TRIG_MASK1 0x3b2 112 #define mmSRBM_PERFMON_CNTL 0x7c00 113 #define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 114 #define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 115 #define mmSRBM_PERFCOUNTER0_LO 0x7c03 116 #define mmSRBM_PERFCOUNTER0_HI 0x7c04 117 #define mmSRBM_PERFCOUNTER1_LO 0x7c05 118 #define mmSRBM_PERFCOUNTER1_HI 0x7c06 119 #define mmSRBM_CAM_INDEX 0xfe34 120 #define mmSRBM_CAM_DATA 0xfe35 121 #define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 122 #define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 123 #define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 124 #define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 125 #define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 126 #define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 127 #define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 128 #define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 129 #define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 130 #define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a 131 #define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b 132 #define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c 133 #define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d 134 #define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e 135 #define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 136 #define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 137 #define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 138 #define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 139 #define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 140 #define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 141 #define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 142 #define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 143 #define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 144 #define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a 145 #define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 146 #define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 147 #define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 148 #define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 149 #define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c 150 #define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d 151 #define mmSRBM_GFX_CNTL_SELECT 0xfa2e 152 #define mmSRBM_GFX_CNTL_DATA 0xfa2f 153 #define mmSRBM_VF_ENABLE 0xfa30 154 #define mmSRBM_VIRT_CNTL 0xfa31 155 #define mmSRBM_VIRT_RESET_REQ 0xfa32 156 #define mmSDMA0_UCODE_ADDR 0x3400 157 #define mmSDMA0_UCODE_DATA 0x3401 158 #define mmSDMA0_POWER_CNTL 0x3402 159 #define mmSDMA0_CLK_CTRL 0x3403 160 #define mmSDMA0_CNTL 0x3404 161 #define mmSDMA0_CHICKEN_BITS 0x3405 162 #define mmSDMA0_TILING_CONFIG 0x3406 163 #define mmSDMA0_HASH 0x3407 164 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 165 #define mmSDMA0_RB_RPTR_FETCH 0x340a 166 #define mmSDMA0_IB_OFFSET_FETCH 0x340b 167 #define mmSDMA0_PROGRAM 0x340c 168 #define mmSDMA0_STATUS_REG 0x340d 169 #define mmSDMA0_STATUS1_REG 0x340e 170 #define mmSDMA0_RD_BURST_CNTL 0x340f 171 #define mmSDMA0_PERFMON_CNTL 0x9000 172 #define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 173 #define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 174 #define mmSDMA0_F32_CNTL 0x3412 175 #define mmSDMA0_FREEZE 0x3413 176 #define mmSDMA0_PHASE0_QUANTUM 0x3414 177 #define mmSDMA0_PHASE1_QUANTUM 0x3415 178 #define mmSDMA_POWER_GATING 0x3416 179 #define mmSDMA_PGFSM_CONFIG 0x3417 180 #define mmSDMA_PGFSM_WRITE 0x3418 181 #define mmSDMA_PGFSM_READ 0x3419 182 #define mmSDMA0_EDC_CONFIG 0x341a 183 #define mmSDMA0_BA_THRESHOLD 0x341b 184 #define mmSDMA0_ID 0x341c 185 #define mmSDMA0_VERSION 0x341d 186 #define mmSDMA0_VM_CNTL 0x3420 187 #define mmSDMA0_VM_CTX_LO 0x3421 188 #define mmSDMA0_VM_CTX_HI 0x3422 189 #define mmSDMA0_STATUS2_REG 0x3423 190 #define mmSDMA0_ACTIVE_FCN_ID 0x3424 191 #define mmSDMA0_VM_CTX_CNTL 0x3425 192 #define mmSDMA0_VIRT_RESET_REQ 0x3426 193 #define mmSDMA0_VF_ENABLE 0x3427 194 #define mmSDMA0_ATOMIC_CNTL 0x3428 195 #define mmSDMA0_ATOMIC_PREOP_LO 0x3429 196 #define mmSDMA0_ATOMIC_PREOP_HI 0x342a 197 #define mmSDMA0_ATCL1_CNTL 0x342b 198 #define mmSDMA0_ATCL1_WATERMK 0x342c 199 #define mmSDMA0_ATCL1_RD_STATUS 0x342d 200 #define mmSDMA0_ATCL1_WR_STATUS 0x342e 201 #define mmSDMA0_ATCL1_INV0 0x342f 202 #define mmSDMA0_ATCL1_INV1 0x3430 203 #define mmSDMA0_ATCL1_INV2 0x3431 204 #define mmSDMA0_ATCL1_RD_XNACK0 0x3432 205 #define mmSDMA0_ATCL1_RD_XNACK1 0x3433 206 #define mmSDMA0_ATCL1_WR_XNACK0 0x3434 207 #define mmSDMA0_ATCL1_WR_XNACK1 0x3435 208 #define mmSDMA0_ATCL1_TIMEOUT 0x3436 209 #define mmSDMA0_POWER_CNTL_IDLE 0x3438 210 #define mmSDMA0_PERF_REG_TYPE0 0x3477 211 #define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 212 #define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 213 #define mmSDMA0_CONTEXT_REG_TYPE2 0x347a 214 #define mmSDMA0_PUB_REG_TYPE0 0x347c 215 #define mmSDMA0_PUB_REG_TYPE1 0x347d 216 #define mmSDMA0_GFX_RB_CNTL 0x3480 217 #define mmSDMA0_GFX_RB_BASE 0x3481 218 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 219 #define mmSDMA0_GFX_RB_RPTR 0x3483 220 #define mmSDMA0_GFX_RB_WPTR 0x3484 221 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 222 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 223 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 224 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 225 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 226 #define mmSDMA0_GFX_IB_CNTL 0x348a 227 #define mmSDMA0_GFX_IB_RPTR 0x348b 228 #define mmSDMA0_GFX_IB_OFFSET 0x348c 229 #define mmSDMA0_GFX_IB_BASE_LO 0x348d 230 #define mmSDMA0_GFX_IB_BASE_HI 0x348e 231 #define mmSDMA0_GFX_IB_SIZE 0x348f 232 #define mmSDMA0_GFX_SKIP_CNTL 0x3490 233 #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 234 #define mmSDMA0_GFX_DOORBELL 0x3492 235 #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 236 #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 237 #define mmSDMA0_GFX_APE1_CNTL 0x34a8 238 #define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 239 #define mmSDMA0_GFX_WATERMARK 0x34aa 240 #define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac 241 #define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad 242 #define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af 243 #define mmSDMA0_GFX_PREEMPT 0x34b0 244 #define mmSDMA0_GFX_DUMMY_REG 0x34b1 245 #define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 246 #define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 247 #define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 248 #define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 249 #define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 250 #define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 251 #define mmSDMA0_GFX_MIDCMD_DATA6 0x34c7 252 #define mmSDMA0_GFX_MIDCMD_DATA7 0x34c8 253 #define mmSDMA0_GFX_MIDCMD_DATA8 0x34c9 254 #define mmSDMA0_GFX_MIDCMD_CNTL 0x34ca 255 #define mmSDMA0_RLC0_RB_CNTL 0x3500 256 #define mmSDMA0_RLC0_RB_BASE 0x3501 257 #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 258 #define mmSDMA0_RLC0_RB_RPTR 0x3503 259 #define mmSDMA0_RLC0_RB_WPTR 0x3504 260 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 261 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 262 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 263 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 264 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 265 #define mmSDMA0_RLC0_IB_CNTL 0x350a 266 #define mmSDMA0_RLC0_IB_RPTR 0x350b 267 #define mmSDMA0_RLC0_IB_OFFSET 0x350c 268 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d 269 #define mmSDMA0_RLC0_IB_BASE_HI 0x350e 270 #define mmSDMA0_RLC0_IB_SIZE 0x350f 271 #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 272 #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 273 #define mmSDMA0_RLC0_DOORBELL 0x3512 274 #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 275 #define mmSDMA0_RLC0_APE1_CNTL 0x3528 276 #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 277 #define mmSDMA0_RLC0_WATERMARK 0x352a 278 #define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c 279 #define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d 280 #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f 281 #define mmSDMA0_RLC0_PREEMPT 0x3530 282 #define mmSDMA0_RLC0_DUMMY_REG 0x3531 283 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 284 #define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 285 #define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 286 #define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 287 #define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 288 #define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 289 #define mmSDMA0_RLC0_MIDCMD_DATA6 0x3547 290 #define mmSDMA0_RLC0_MIDCMD_DATA7 0x3548 291 #define mmSDMA0_RLC0_MIDCMD_DATA8 0x3549 292 #define mmSDMA0_RLC0_MIDCMD_CNTL 0x354a 293 #define mmSDMA0_RLC1_RB_CNTL 0x3580 294 #define mmSDMA0_RLC1_RB_BASE 0x3581 295 #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 296 #define mmSDMA0_RLC1_RB_RPTR 0x3583 297 #define mmSDMA0_RLC1_RB_WPTR 0x3584 298 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 299 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 300 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 301 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 302 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 303 #define mmSDMA0_RLC1_IB_CNTL 0x358a 304 #define mmSDMA0_RLC1_IB_RPTR 0x358b 305 #define mmSDMA0_RLC1_IB_OFFSET 0x358c 306 #define mmSDMA0_RLC1_IB_BASE_LO 0x358d 307 #define mmSDMA0_RLC1_IB_BASE_HI 0x358e 308 #define mmSDMA0_RLC1_IB_SIZE 0x358f 309 #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 310 #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 311 #define mmSDMA0_RLC1_DOORBELL 0x3592 312 #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 313 #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 314 #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 315 #define mmSDMA0_RLC1_WATERMARK 0x35aa 316 #define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac 317 #define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad 318 #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af 319 #define mmSDMA0_RLC1_PREEMPT 0x35b0 320 #define mmSDMA0_RLC1_DUMMY_REG 0x35b1 321 #define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 322 #define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 323 #define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 324 #define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 325 #define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 326 #define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 327 #define mmSDMA0_RLC1_MIDCMD_DATA6 0x35c7 328 #define mmSDMA0_RLC1_MIDCMD_DATA7 0x35c8 329 #define mmSDMA0_RLC1_MIDCMD_DATA8 0x35c9 330 #define mmSDMA0_RLC1_MIDCMD_CNTL 0x35ca 331 #define mmSDMA1_UCODE_ADDR 0x3600 332 #define mmSDMA1_UCODE_DATA 0x3601 333 #define mmSDMA1_POWER_CNTL 0x3602 334 #define mmSDMA1_CLK_CTRL 0x3603 335 #define mmSDMA1_CNTL 0x3604 336 #define mmSDMA1_CHICKEN_BITS 0x3605 337 #define mmSDMA1_TILING_CONFIG 0x3606 338 #define mmSDMA1_HASH 0x3607 339 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 340 #define mmSDMA1_RB_RPTR_FETCH 0x360a 341 #define mmSDMA1_IB_OFFSET_FETCH 0x360b 342 #define mmSDMA1_PROGRAM 0x360c 343 #define mmSDMA1_STATUS_REG 0x360d 344 #define mmSDMA1_STATUS1_REG 0x360e 345 #define mmSDMA1_RD_BURST_CNTL 0x360f 346 #define mmSDMA1_PERFMON_CNTL 0x9010 347 #define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 348 #define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 349 #define mmSDMA1_F32_CNTL 0x3612 350 #define mmSDMA1_FREEZE 0x3613 351 #define mmSDMA1_PHASE0_QUANTUM 0x3614 352 #define mmSDMA1_PHASE1_QUANTUM 0x3615 353 #define mmSDMA1_EDC_CONFIG 0x361a 354 #define mmSDMA1_BA_THRESHOLD 0x361b 355 #define mmSDMA1_ID 0x361c 356 #define mmSDMA1_VERSION 0x361d 357 #define mmSDMA1_VM_CNTL 0x3620 358 #define mmSDMA1_VM_CTX_LO 0x3621 359 #define mmSDMA1_VM_CTX_HI 0x3622 360 #define mmSDMA1_STATUS2_REG 0x3623 361 #define mmSDMA1_ACTIVE_FCN_ID 0x3624 362 #define mmSDMA1_VM_CTX_CNTL 0x3625 363 #define mmSDMA1_VIRT_RESET_REQ 0x3626 364 #define mmSDMA1_VF_ENABLE 0x3627 365 #define mmSDMA1_ATOMIC_CNTL 0x3628 366 #define mmSDMA1_ATOMIC_PREOP_LO 0x3629 367 #define mmSDMA1_ATOMIC_PREOP_HI 0x362a 368 #define mmSDMA1_ATCL1_CNTL 0x362b 369 #define mmSDMA1_ATCL1_WATERMK 0x362c 370 #define mmSDMA1_ATCL1_RD_STATUS 0x362d 371 #define mmSDMA1_ATCL1_WR_STATUS 0x362e 372 #define mmSDMA1_ATCL1_INV0 0x362f 373 #define mmSDMA1_ATCL1_INV1 0x3630 374 #define mmSDMA1_ATCL1_INV2 0x3631 375 #define mmSDMA1_ATCL1_RD_XNACK0 0x3632 376 #define mmSDMA1_ATCL1_RD_XNACK1 0x3633 377 #define mmSDMA1_ATCL1_WR_XNACK0 0x3634 378 #define mmSDMA1_ATCL1_WR_XNACK1 0x3635 379 #define mmSDMA1_ATCL1_TIMEOUT 0x3636 380 #define mmSDMA1_POWER_CNTL_IDLE 0x3638 381 #define mmSDMA1_PERF_REG_TYPE0 0x3677 382 #define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 383 #define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 384 #define mmSDMA1_CONTEXT_REG_TYPE2 0x367a 385 #define mmSDMA1_PUB_REG_TYPE0 0x367c 386 #define mmSDMA1_PUB_REG_TYPE1 0x367d 387 #define mmSDMA1_GFX_RB_CNTL 0x3680 388 #define mmSDMA1_GFX_RB_BASE 0x3681 389 #define mmSDMA1_GFX_RB_BASE_HI 0x3682 390 #define mmSDMA1_GFX_RB_RPTR 0x3683 391 #define mmSDMA1_GFX_RB_WPTR 0x3684 392 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 393 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 394 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 395 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 396 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 397 #define mmSDMA1_GFX_IB_CNTL 0x368a 398 #define mmSDMA1_GFX_IB_RPTR 0x368b 399 #define mmSDMA1_GFX_IB_OFFSET 0x368c 400 #define mmSDMA1_GFX_IB_BASE_LO 0x368d 401 #define mmSDMA1_GFX_IB_BASE_HI 0x368e 402 #define mmSDMA1_GFX_IB_SIZE 0x368f 403 #define mmSDMA1_GFX_SKIP_CNTL 0x3690 404 #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 405 #define mmSDMA1_GFX_DOORBELL 0x3692 406 #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 407 #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 408 #define mmSDMA1_GFX_APE1_CNTL 0x36a8 409 #define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 410 #define mmSDMA1_GFX_WATERMARK 0x36aa 411 #define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac 412 #define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad 413 #define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af 414 #define mmSDMA1_GFX_PREEMPT 0x36b0 415 #define mmSDMA1_GFX_DUMMY_REG 0x36b1 416 #define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 417 #define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 418 #define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 419 #define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 420 #define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 421 #define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 422 #define mmSDMA1_GFX_MIDCMD_DATA6 0x36c7 423 #define mmSDMA1_GFX_MIDCMD_DATA7 0x36c8 424 #define mmSDMA1_GFX_MIDCMD_DATA8 0x36c9 425 #define mmSDMA1_GFX_MIDCMD_CNTL 0x36ca 426 #define mmSDMA1_RLC0_RB_CNTL 0x3700 427 #define mmSDMA1_RLC0_RB_BASE 0x3701 428 #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 429 #define mmSDMA1_RLC0_RB_RPTR 0x3703 430 #define mmSDMA1_RLC0_RB_WPTR 0x3704 431 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 432 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 433 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 434 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 435 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 436 #define mmSDMA1_RLC0_IB_CNTL 0x370a 437 #define mmSDMA1_RLC0_IB_RPTR 0x370b 438 #define mmSDMA1_RLC0_IB_OFFSET 0x370c 439 #define mmSDMA1_RLC0_IB_BASE_LO 0x370d 440 #define mmSDMA1_RLC0_IB_BASE_HI 0x370e 441 #define mmSDMA1_RLC0_IB_SIZE 0x370f 442 #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 443 #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 444 #define mmSDMA1_RLC0_DOORBELL 0x3712 445 #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 446 #define mmSDMA1_RLC0_APE1_CNTL 0x3728 447 #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 448 #define mmSDMA1_RLC0_WATERMARK 0x372a 449 #define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c 450 #define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d 451 #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f 452 #define mmSDMA1_RLC0_PREEMPT 0x3730 453 #define mmSDMA1_RLC0_DUMMY_REG 0x3731 454 #define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 455 #define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 456 #define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 457 #define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 458 #define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 459 #define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 460 #define mmSDMA1_RLC0_MIDCMD_DATA6 0x3747 461 #define mmSDMA1_RLC0_MIDCMD_DATA7 0x3748 462 #define mmSDMA1_RLC0_MIDCMD_DATA8 0x3749 463 #define mmSDMA1_RLC0_MIDCMD_CNTL 0x374a 464 #define mmSDMA1_RLC1_RB_CNTL 0x3780 465 #define mmSDMA1_RLC1_RB_BASE 0x3781 466 #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 467 #define mmSDMA1_RLC1_RB_RPTR 0x3783 468 #define mmSDMA1_RLC1_RB_WPTR 0x3784 469 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 470 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 471 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 472 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 473 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 474 #define mmSDMA1_RLC1_IB_CNTL 0x378a 475 #define mmSDMA1_RLC1_IB_RPTR 0x378b 476 #define mmSDMA1_RLC1_IB_OFFSET 0x378c 477 #define mmSDMA1_RLC1_IB_BASE_LO 0x378d 478 #define mmSDMA1_RLC1_IB_BASE_HI 0x378e 479 #define mmSDMA1_RLC1_IB_SIZE 0x378f 480 #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 481 #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 482 #define mmSDMA1_RLC1_DOORBELL 0x3792 483 #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 484 #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 485 #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 486 #define mmSDMA1_RLC1_WATERMARK 0x37aa 487 #define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac 488 #define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad 489 #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af 490 #define mmSDMA1_RLC1_PREEMPT 0x37b0 491 #define mmSDMA1_RLC1_DUMMY_REG 0x37b1 492 #define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 493 #define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 494 #define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 495 #define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 496 #define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 497 #define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 498 #define mmSDMA1_RLC1_MIDCMD_DATA6 0x37c7 499 #define mmSDMA1_RLC1_MIDCMD_DATA7 0x37c8 500 #define mmSDMA1_RLC1_MIDCMD_DATA8 0x37c9 501 #define mmSDMA1_RLC1_MIDCMD_CNTL 0x37ca 502 #define mmHDP_HOST_PATH_CNTL 0xb00 503 #define mmHDP_NONSURFACE_BASE 0xb01 504 #define mmHDP_NONSURFACE_INFO 0xb02 505 #define mmHDP_NONSURFACE_SIZE 0xb03 506 #define mmHDP_NONSURF_FLAGS 0xbc9 507 #define mmHDP_NONSURF_FLAGS_CLR 0xbca 508 #define mmHDP_SW_SEMAPHORE 0xbcb 509 #define mmHDP_DEBUG0 0xbcc 510 #define mmHDP_DEBUG1 0xbcd 511 #define mmHDP_LAST_SURFACE_HIT 0xbce 512 #define mmHDP_TILING_CONFIG 0xbcf 513 #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 514 #define mmHDP_OUTSTANDING_REQ 0xbd1 515 #define mmHDP_ADDR_CONFIG 0xbd2 516 #define mmHDP_MISC_CNTL 0xbd3 517 #define mmHDP_MEM_POWER_LS 0xbd4 518 #define mmHDP_NONSURFACE_PREFETCH 0xbd5 519 #define mmHDP_MEMIO_CNTL 0xbf6 520 #define mmHDP_MEMIO_ADDR 0xbf7 521 #define mmHDP_MEMIO_STATUS 0xbf8 522 #define mmHDP_MEMIO_WR_DATA 0xbf9 523 #define mmHDP_MEMIO_RD_DATA 0xbfa 524 #define mmHDP_VF_ENABLE 0xbfb 525 #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 526 #define mmHDP_XDP_D2H_FLUSH 0xc01 527 #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 528 #define mmHDP_XDP_D2H_RSVD_3 0xc03 529 #define mmHDP_XDP_D2H_RSVD_4 0xc04 530 #define mmHDP_XDP_D2H_RSVD_5 0xc05 531 #define mmHDP_XDP_D2H_RSVD_6 0xc06 532 #define mmHDP_XDP_D2H_RSVD_7 0xc07 533 #define mmHDP_XDP_D2H_RSVD_8 0xc08 534 #define mmHDP_XDP_D2H_RSVD_9 0xc09 535 #define mmHDP_XDP_D2H_RSVD_10 0xc0a 536 #define mmHDP_XDP_D2H_RSVD_11 0xc0b 537 #define mmHDP_XDP_D2H_RSVD_12 0xc0c 538 #define mmHDP_XDP_D2H_RSVD_13 0xc0d 539 #define mmHDP_XDP_D2H_RSVD_14 0xc0e 540 #define mmHDP_XDP_D2H_RSVD_15 0xc0f 541 #define mmHDP_XDP_D2H_RSVD_16 0xc10 542 #define mmHDP_XDP_D2H_RSVD_17 0xc11 543 #define mmHDP_XDP_D2H_RSVD_18 0xc12 544 #define mmHDP_XDP_D2H_RSVD_19 0xc13 545 #define mmHDP_XDP_D2H_RSVD_20 0xc14 546 #define mmHDP_XDP_D2H_RSVD_21 0xc15 547 #define mmHDP_XDP_D2H_RSVD_22 0xc16 548 #define mmHDP_XDP_D2H_RSVD_23 0xc17 549 #define mmHDP_XDP_D2H_RSVD_24 0xc18 550 #define mmHDP_XDP_D2H_RSVD_25 0xc19 551 #define mmHDP_XDP_D2H_RSVD_26 0xc1a 552 #define mmHDP_XDP_D2H_RSVD_27 0xc1b 553 #define mmHDP_XDP_D2H_RSVD_28 0xc1c 554 #define mmHDP_XDP_D2H_RSVD_29 0xc1d 555 #define mmHDP_XDP_D2H_RSVD_30 0xc1e 556 #define mmHDP_XDP_D2H_RSVD_31 0xc1f 557 #define mmHDP_XDP_D2H_RSVD_32 0xc20 558 #define mmHDP_XDP_D2H_RSVD_33 0xc21 559 #define mmHDP_XDP_D2H_RSVD_34 0xc22 560 #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 561 #define mmHDP_XDP_P2P_BAR_CFG 0xc24 562 #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 563 #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 564 #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 565 #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 566 #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 567 #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a 568 #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b 569 #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c 570 #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d 571 #define mmHDP_XDP_HDP_MC_CFG 0xc2e 572 #define mmHDP_XDP_HST_CFG 0xc2f 573 #define mmHDP_XDP_SID_CFG 0xc30 574 #define mmHDP_XDP_HDP_IPH_CFG 0xc31 575 #define mmHDP_XDP_SRBM_CFG 0xc32 576 #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 577 #define mmHDP_XDP_P2P_BAR0 0xc34 578 #define mmHDP_XDP_P2P_BAR1 0xc35 579 #define mmHDP_XDP_P2P_BAR2 0xc36 580 #define mmHDP_XDP_P2P_BAR3 0xc37 581 #define mmHDP_XDP_P2P_BAR4 0xc38 582 #define mmHDP_XDP_P2P_BAR5 0xc39 583 #define mmHDP_XDP_P2P_BAR6 0xc3a 584 #define mmHDP_XDP_P2P_BAR7 0xc3b 585 #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c 586 #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d 587 #define mmHDP_XDP_BUSY_STS 0xc3e 588 #define mmHDP_XDP_STICKY 0xc3f 589 #define mmHDP_XDP_CHKN 0xc40 590 #define mmHDP_XDP_DBG_ADDR 0xc41 591 #define mmHDP_XDP_DBG_DATA 0xc42 592 #define mmHDP_XDP_DBG_MASK 0xc43 593 #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 594 595 #endif /* OSS_3_0_1_D_H */ 596