1 /* $NetBSD: oss_2_0_d.h,v 1.3 2021/12/18 23:45:21 riastradh Exp $ */ 2 3 /* 4 * OSS_2_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef OSS_2_0_D_H 27 #define OSS_2_0_D_H 28 29 #define mmIH_VMID_0_LUT 0xf50 30 #define mmIH_VMID_1_LUT 0xf51 31 #define mmIH_VMID_2_LUT 0xf52 32 #define mmIH_VMID_3_LUT 0xf53 33 #define mmIH_VMID_4_LUT 0xf54 34 #define mmIH_VMID_5_LUT 0xf55 35 #define mmIH_VMID_6_LUT 0xf56 36 #define mmIH_VMID_7_LUT 0xf57 37 #define mmIH_VMID_8_LUT 0xf58 38 #define mmIH_VMID_9_LUT 0xf59 39 #define mmIH_VMID_10_LUT 0xf5a 40 #define mmIH_VMID_11_LUT 0xf5b 41 #define mmIH_VMID_12_LUT 0xf5c 42 #define mmIH_VMID_13_LUT 0xf5d 43 #define mmIH_VMID_14_LUT 0xf5e 44 #define mmIH_VMID_15_LUT 0xf5f 45 #define mmIH_RB_CNTL 0xf80 46 #define mmIH_RB_BASE 0xf81 47 #define mmIH_RB_RPTR 0xf82 48 #define mmIH_RB_WPTR 0xf83 49 #define mmIH_RB_WPTR_ADDR_HI 0xf84 50 #define mmIH_RB_WPTR_ADDR_LO 0xf85 51 #define mmIH_CNTL 0xf86 52 #define mmIH_LEVEL_STATUS 0xf87 53 #define mmIH_STATUS 0xf88 54 #define mmIH_PERFMON_CNTL 0xf89 55 #define mmIH_PERFCOUNTER0_RESULT 0xf8a 56 #define mmIH_PERFCOUNTER1_RESULT 0xf8b 57 #define mmIH_ADVFAULT_CNTL 0xf8c 58 #define mmSEM_MCIF_CONFIG 0xf90 59 #define mmSDMA_CONFIG 0xf91 60 #define mmSDMA1_CONFIG 0xf92 61 #define mmUVD_CONFIG 0xf93 62 #define mmVCE_CONFIG 0xf94 63 #define mmACP_CONFIG 0xf95 64 #define mmCPG_CONFIG 0xf96 65 #define mmCPC1_CONFIG 0xf97 66 #define mmCPC2_CONFIG 0xf98 67 #define mmSEM_STATUS 0xf99 68 #define mmSEM_EDC_CONFIG 0xf9a 69 #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b 70 #define mmSEM_MAILBOX 0xf9c 71 #define mmSEM_MAILBOX_CONTROL 0xf9d 72 #define mmSEM_CHICKEN_BITS 0xf9e 73 #define mmSRBM_CNTL 0x390 74 #define mmSRBM_GFX_CNTL 0x391 75 #define mmSRBM_STATUS2 0x393 76 #define mmSRBM_STATUS 0x394 77 #define mmSRBM_CAM_INDEX 0x396 78 #define mmSRBM_CAM_DATA 0x397 79 #define mmSRBM_SOFT_RESET 0x398 80 #define mmSRBM_DEBUG_CNTL 0x399 81 #define mmSRBM_DEBUG_DATA 0x39a 82 #define mmSRBM_CHIP_REVISION 0x39b 83 #define mmCC_SYS_RB_REDUNDANCY 0x39f 84 #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 85 #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 86 #define mmSRBM_MC_CLKEN_CNTL 0x3b3 87 #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 88 #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 89 #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 90 #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 91 #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 92 #define mmSRBM_DEBUG 0x3a4 93 #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 94 #define mmSRBM_READ_ERROR 0x3a6 95 #define mmSRBM_INT_CNTL 0x3a8 96 #define mmSRBM_INT_STATUS 0x3a9 97 #define mmSRBM_INT_ACK 0x3aa 98 #define mmSRBM_PERFMON_CNTL 0x700 99 #define mmSRBM_PERFCOUNTER0_SELECT 0x701 100 #define mmSRBM_PERFCOUNTER1_SELECT 0x702 101 #define mmSRBM_PERFCOUNTER0_LO 0x703 102 #define mmSRBM_PERFCOUNTER0_HI 0x704 103 #define mmSRBM_PERFCOUNTER1_LO 0x705 104 #define mmSRBM_PERFCOUNTER1_HI 0x706 105 #define mmCC_DRM_ID_STRAPS 0x1559 106 #define mmCGTT_DRM_CLK_CTRL0 0x1579 107 #define ixDH_TEST 0x0 108 #define ixKHFS0 0x4 109 #define ixKHFS1 0x8 110 #define ixKHFS2 0xc 111 #define ixKHFS3 0x10 112 #define ixKSESSION0 0x14 113 #define ixKSESSION1 0x18 114 #define ixKSESSION2 0x1c 115 #define ixKSESSION3 0x20 116 #define ixKSIG0 0x24 117 #define ixKSIG1 0x28 118 #define ixKSIG2 0x2c 119 #define ixKSIG3 0x30 120 #define ixEXP0 0x34 121 #define ixEXP1 0x38 122 #define ixEXP2 0x3c 123 #define ixEXP3 0x40 124 #define ixEXP4 0x44 125 #define ixEXP5 0x48 126 #define ixEXP6 0x4c 127 #define ixEXP7 0x50 128 #define ixLX0 0x54 129 #define ixLX1 0x58 130 #define ixLX2 0x5c 131 #define ixLX3 0x60 132 #define ixCLIENT2_K0 0x1b4 133 #define ixCLIENT2_K1 0x1b8 134 #define ixCLIENT2_K2 0x1bc 135 #define ixCLIENT2_K3 0x1c0 136 #define ixCLIENT2_CK0 0x1c4 137 #define ixCLIENT2_CK1 0x1c8 138 #define ixCLIENT2_CK2 0x1cc 139 #define ixCLIENT2_CK3 0x1d0 140 #define ixCLIENT2_CD0 0x1d4 141 #define ixCLIENT2_CD1 0x1d8 142 #define ixCLIENT2_CD2 0x1dc 143 #define ixCLIENT2_CD3 0x1e0 144 #define ixCLIENT2_BM 0x1e4 145 #define ixCLIENT2_OFFSET 0x1e8 146 #define ixCLIENT2_STATUS 0x1ec 147 #define ixCLIENT0_K0 0x1f0 148 #define ixCLIENT0_K1 0x1f4 149 #define ixCLIENT0_K2 0x1f8 150 #define ixCLIENT0_K3 0x1fc 151 #define ixCLIENT0_CK0 0x200 152 #define ixCLIENT0_CK1 0x204 153 #define ixCLIENT0_CK2 0x208 154 #define ixCLIENT0_CK3 0x20c 155 #define ixCLIENT0_CD0 0x210 156 #define ixCLIENT0_CD1 0x214 157 #define ixCLIENT0_CD2 0x218 158 #define ixCLIENT0_CD3 0x21c 159 #define ixCLIENT0_BM 0x220 160 #define ixCLIENT0_OFFSET 0x224 161 #define ixCLIENT0_STATUS 0x228 162 #define ixCLIENT1_K0 0x22c 163 #define ixCLIENT1_K1 0x230 164 #define ixCLIENT1_K2 0x234 165 #define ixCLIENT1_K3 0x238 166 #define ixCLIENT1_CK0 0x23c 167 #define ixCLIENT1_CK1 0x240 168 #define ixCLIENT1_CK2 0x244 169 #define ixCLIENT1_CK3 0x248 170 #define ixCLIENT1_CD0 0x24c 171 #define ixCLIENT1_CD1 0x250 172 #define ixCLIENT1_CD2 0x254 173 #define ixCLIENT1_CD3 0x258 174 #define ixCLIENT1_BM 0x25c 175 #define ixCLIENT1_OFFSET 0x260 176 #define ixCLIENT1_PORT_STATUS 0x264 177 #define ixKEFUSE0 0x268 178 #define ixKEFUSE1 0x26c 179 #define ixKEFUSE2 0x270 180 #define ixKEFUSE3 0x274 181 #define ixHFS_SEED0 0x278 182 #define ixHFS_SEED1 0x27c 183 #define ixHFS_SEED2 0x280 184 #define ixHFS_SEED3 0x284 185 #define ixRINGOSC_MASK 0x288 186 #define ixCLIENT0_OFFSET_HI 0x290 187 #define ixCLIENT1_OFFSET_HI 0x294 188 #define ixCLIENT2_OFFSET_HI 0x298 189 #define ixSPU_PORT_STATUS 0x29c 190 #define ixCLIENT3_OFFSET_HI 0x2a0 191 #define ixCLIENT3_K0 0x2a4 192 #define ixCLIENT3_K1 0x2a8 193 #define ixCLIENT3_K2 0x2ac 194 #define ixCLIENT3_K3 0x2b0 195 #define ixCLIENT3_CK0 0x2b4 196 #define ixCLIENT3_CK1 0x2b8 197 #define ixCLIENT3_CK2 0x2bc 198 #define ixCLIENT3_CK3 0x2c0 199 #define ixCLIENT3_CD0 0x2c4 200 #define ixCLIENT3_CD1 0x2c8 201 #define ixCLIENT3_CD2 0x2cc 202 #define ixCLIENT3_CD3 0x2d0 203 #define ixCLIENT3_BM 0x2d4 204 #define ixCLIENT3_OFFSET 0x2d8 205 #define ixCLIENT3_STATUS 0x2dc 206 #define mmDC_TEST_DEBUG_INDEX 0x157c 207 #define mmDC_TEST_DEBUG_DATA 0x157d 208 #define mmXDMA_SLV_CNTL 0x460 209 #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 210 #define mmXDMA_SLV_SLS_PITCH 0x462 211 #define mmXDMA_SLV_READ_URGENT_CNTL 0x463 212 #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 213 #define mmXDMA_SLV_WB_RATE_CNTL 0x465 214 #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 215 #define mmXDMA_SLV_READ_LATENCY_AVE 0x467 216 #define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 217 #define mmXDMA_SLV_MEM_NACK_STATUS 0x469 218 #define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a 219 #define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b 220 #define mmXDMA_SLV_FLIP_PENDING 0x46c 221 #define mmSDMA0_UCODE_ADDR 0x3400 222 #define mmSDMA0_UCODE_DATA 0x3401 223 #define mmSDMA0_POWER_CNTL 0x3402 224 #define mmSDMA0_CLK_CTRL 0x3403 225 #define mmSDMA0_CNTL 0x3404 226 #define mmSDMA0_CHICKEN_BITS 0x3405 227 #define mmSDMA0_TILING_CONFIG 0x3406 228 #define mmSDMA0_HASH 0x3407 229 #define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL 0x3408 230 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 231 #define mmSDMA0_RB_RPTR_FETCH 0x340a 232 #define mmSDMA0_IB_OFFSET_FETCH 0x340b 233 #define mmSDMA0_PROGRAM 0x340c 234 #define mmSDMA0_STATUS_REG 0x340d 235 #define mmSDMA0_STATUS1_REG 0x340e 236 #define mmSDMA0_PERFMON_CNTL 0x340f 237 #define mmSDMA0_PERFCOUNTER0_RESULT 0x3410 238 #define mmSDMA0_PERFCOUNTER1_RESULT 0x3411 239 #define mmSDMA0_F32_CNTL 0x3412 240 #define mmSDMA0_FREEZE 0x3413 241 #define mmSDMA0_PHASE0_QUANTUM 0x3414 242 #define mmSDMA0_PHASE1_QUANTUM 0x3415 243 #define mmSDMA_POWER_GATING 0x3416 244 #define mmSDMA_PGFSM_CONFIG 0x3417 245 #define mmSDMA_PGFSM_WRITE 0x3418 246 #define mmSDMA_PGFSM_READ 0x3419 247 #define mmSDMA0_EDC_CONFIG 0x341a 248 #define mmSDMA0_GFX_RB_CNTL 0x3480 249 #define mmSDMA0_GFX_RB_BASE 0x3481 250 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 251 #define mmSDMA0_GFX_RB_RPTR 0x3483 252 #define mmSDMA0_GFX_RB_WPTR 0x3484 253 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 254 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 255 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 256 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 257 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 258 #define mmSDMA0_GFX_IB_CNTL 0x348a 259 #define mmSDMA0_GFX_IB_RPTR 0x348b 260 #define mmSDMA0_GFX_IB_OFFSET 0x348c 261 #define mmSDMA0_GFX_IB_BASE_LO 0x348d 262 #define mmSDMA0_GFX_IB_BASE_HI 0x348e 263 #define mmSDMA0_GFX_IB_SIZE 0x348f 264 #define mmSDMA0_GFX_SKIP_CNTL 0x3490 265 #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 266 #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 267 #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 268 #define mmSDMA0_GFX_APE1_CNTL 0x34a8 269 #define mmSDMA0_GFX_WATERMARK 0x34aa 270 #define mmSDMA0_RLC0_RB_CNTL 0x3500 271 #define mmSDMA0_RLC0_RB_BASE 0x3501 272 #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 273 #define mmSDMA0_RLC0_RB_RPTR 0x3503 274 #define mmSDMA0_RLC0_RB_WPTR 0x3504 275 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 276 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 277 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 278 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 279 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 280 #define mmSDMA0_RLC0_IB_CNTL 0x350a 281 #define mmSDMA0_RLC0_IB_RPTR 0x350b 282 #define mmSDMA0_RLC0_IB_OFFSET 0x350c 283 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d 284 #define mmSDMA0_RLC0_IB_BASE_HI 0x350e 285 #define mmSDMA0_RLC0_IB_SIZE 0x350f 286 #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 287 #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 288 #define mmSDMA0_RLC0_DOORBELL 0x3512 289 #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 290 #define mmSDMA0_RLC0_APE1_CNTL 0x3528 291 #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 292 #define mmSDMA0_RLC0_WATERMARK 0x352a 293 #define mmSDMA0_RLC1_RB_CNTL 0x3580 294 #define mmSDMA0_RLC1_RB_BASE 0x3581 295 #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 296 #define mmSDMA0_RLC1_RB_RPTR 0x3583 297 #define mmSDMA0_RLC1_RB_WPTR 0x3584 298 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 299 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 300 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 301 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 302 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 303 #define mmSDMA0_RLC1_IB_CNTL 0x358a 304 #define mmSDMA0_RLC1_IB_RPTR 0x358b 305 #define mmSDMA0_RLC1_IB_OFFSET 0x358c 306 #define mmSDMA0_RLC1_IB_BASE_LO 0x358d 307 #define mmSDMA0_RLC1_IB_BASE_HI 0x358e 308 #define mmSDMA0_RLC1_IB_SIZE 0x358f 309 #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 310 #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 311 #define mmSDMA0_RLC1_DOORBELL 0x3592 312 #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 313 #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 314 #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 315 #define mmSDMA0_RLC1_WATERMARK 0x35aa 316 #define mmSDMA1_UCODE_ADDR 0x3600 317 #define mmSDMA1_UCODE_DATA 0x3601 318 #define mmSDMA1_POWER_CNTL 0x3602 319 #define mmSDMA1_CLK_CTRL 0x3603 320 #define mmSDMA1_CNTL 0x3604 321 #define mmSDMA1_CHICKEN_BITS 0x3605 322 #define mmSDMA1_TILING_CONFIG 0x3606 323 #define mmSDMA1_HASH 0x3607 324 #define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL 0x3608 325 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 326 #define mmSDMA1_RB_RPTR_FETCH 0x360a 327 #define mmSDMA1_IB_OFFSET_FETCH 0x360b 328 #define mmSDMA1_PROGRAM 0x360c 329 #define mmSDMA1_STATUS_REG 0x360d 330 #define mmSDMA1_STATUS1_REG 0x360e 331 #define mmSDMA1_PERFMON_CNTL 0x360f 332 #define mmSDMA1_PERFCOUNTER0_RESULT 0x3610 333 #define mmSDMA1_PERFCOUNTER1_RESULT 0x3611 334 #define mmSDMA1_F32_CNTL 0x3612 335 #define mmSDMA1_FREEZE 0x3613 336 #define mmSDMA1_PHASE0_QUANTUM 0x3614 337 #define mmSDMA1_PHASE1_QUANTUM 0x3615 338 #define mmSDMA1_EDC_CONFIG 0x361a 339 #define mmSDMA1_GFX_RB_CNTL 0x3680 340 #define mmSDMA1_GFX_RB_BASE 0x3681 341 #define mmSDMA1_GFX_RB_BASE_HI 0x3682 342 #define mmSDMA1_GFX_RB_RPTR 0x3683 343 #define mmSDMA1_GFX_RB_WPTR 0x3684 344 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 345 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 346 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 347 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 348 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 349 #define mmSDMA1_GFX_IB_CNTL 0x368a 350 #define mmSDMA1_GFX_IB_RPTR 0x368b 351 #define mmSDMA1_GFX_IB_OFFSET 0x368c 352 #define mmSDMA1_GFX_IB_BASE_LO 0x368d 353 #define mmSDMA1_GFX_IB_BASE_HI 0x368e 354 #define mmSDMA1_GFX_IB_SIZE 0x368f 355 #define mmSDMA1_GFX_SKIP_CNTL 0x3690 356 #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 357 #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 358 #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 359 #define mmSDMA1_GFX_APE1_CNTL 0x36a8 360 #define mmSDMA1_GFX_WATERMARK 0x36aa 361 #define mmSDMA1_RLC0_RB_CNTL 0x3700 362 #define mmSDMA1_RLC0_RB_BASE 0x3701 363 #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 364 #define mmSDMA1_RLC0_RB_RPTR 0x3703 365 #define mmSDMA1_RLC0_RB_WPTR 0x3704 366 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 367 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 368 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 369 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 370 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 371 #define mmSDMA1_RLC0_IB_CNTL 0x370a 372 #define mmSDMA1_RLC0_IB_RPTR 0x370b 373 #define mmSDMA1_RLC0_IB_OFFSET 0x370c 374 #define mmSDMA1_RLC0_IB_BASE_LO 0x370d 375 #define mmSDMA1_RLC0_IB_BASE_HI 0x370e 376 #define mmSDMA1_RLC0_IB_SIZE 0x370f 377 #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 378 #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 379 #define mmSDMA1_RLC0_DOORBELL 0x3712 380 #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 381 #define mmSDMA1_RLC0_APE1_CNTL 0x3728 382 #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 383 #define mmSDMA1_RLC0_WATERMARK 0x372a 384 #define mmSDMA1_RLC1_RB_CNTL 0x3780 385 #define mmSDMA1_RLC1_RB_BASE 0x3781 386 #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 387 #define mmSDMA1_RLC1_RB_RPTR 0x3783 388 #define mmSDMA1_RLC1_RB_WPTR 0x3784 389 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 390 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 391 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 392 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 393 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 394 #define mmSDMA1_RLC1_IB_CNTL 0x378a 395 #define mmSDMA1_RLC1_IB_RPTR 0x378b 396 #define mmSDMA1_RLC1_IB_OFFSET 0x378c 397 #define mmSDMA1_RLC1_IB_BASE_LO 0x378d 398 #define mmSDMA1_RLC1_IB_BASE_HI 0x378e 399 #define mmSDMA1_RLC1_IB_SIZE 0x378f 400 #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 401 #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 402 #define mmSDMA1_RLC1_DOORBELL 0x3792 403 #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 404 #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 405 #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 406 #define mmSDMA1_RLC1_WATERMARK 0x37aa 407 #define mmXDMA_SLV_CHANNEL_CNTL 0x470 408 #define mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 409 #define mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 410 #define mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 411 #define mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 412 #define mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 413 #define mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 414 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 415 #define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 416 #define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 417 #define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 418 #define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 419 #define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 420 #define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 421 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 422 #define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 423 #define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a 424 #define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 425 #define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a 426 #define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 427 #define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a 428 #define mmXDMA_MSTR_PIPE_CNTL 0x400 429 #define mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 430 #define mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 431 #define mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 432 #define mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 433 #define mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 434 #define mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 435 #define mmXDMA_MSTR_READ_COMMAND 0x401 436 #define mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 437 #define mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 438 #define mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 439 #define mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 440 #define mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 441 #define mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 442 #define mmXDMA_MSTR_CHANNEL_DIM 0x402 443 #define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 444 #define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 445 #define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 446 #define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 447 #define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 448 #define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 449 #define mmXDMA_MSTR_HEIGHT 0x403 450 #define mmMDMA_PIPE0_XDMA_MSTR_HEIGHT 0x403 451 #define mmMDMA_PIPE1_XDMA_MSTR_HEIGHT 0x413 452 #define mmMDMA_PIPE2_XDMA_MSTR_HEIGHT 0x423 453 #define mmMDMA_PIPE3_XDMA_MSTR_HEIGHT 0x433 454 #define mmMDMA_PIPE4_XDMA_MSTR_HEIGHT 0x443 455 #define mmMDMA_PIPE5_XDMA_MSTR_HEIGHT 0x453 456 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 457 #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 458 #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 459 #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 460 #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 461 #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 462 #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 463 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 464 #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 465 #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 466 #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 467 #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 468 #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 469 #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 470 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 471 #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 472 #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 473 #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 474 #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 475 #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 476 #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 477 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 478 #define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 479 #define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 480 #define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 481 #define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 482 #define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 483 #define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 484 #define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 485 #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 486 #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 487 #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 488 #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 489 #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 490 #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 491 #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 492 #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 493 #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 494 #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 495 #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 496 #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 497 #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 498 #define mmXDMA_MSTR_CACHE_PITCH 0x40a 499 #define mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH 0x40a 500 #define mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH 0x41a 501 #define mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH 0x42a 502 #define mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH 0x43a 503 #define mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH 0x44a 504 #define mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH 0x45a 505 #define mmXDMA_MSTR_CHANNEL_START 0x40b 506 #define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b 507 #define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b 508 #define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b 509 #define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b 510 #define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b 511 #define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b 512 #define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c 513 #define mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c 514 #define mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x41c 515 #define mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x42c 516 #define mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x43c 517 #define mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x44c 518 #define mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x45c 519 #define mmXDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d 520 #define mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d 521 #define mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x41d 522 #define mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x42d 523 #define mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x43d 524 #define mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x44d 525 #define mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x45d 526 #define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e 527 #define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e 528 #define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e 529 #define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e 530 #define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e 531 #define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e 532 #define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e 533 #define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f 534 #define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f 535 #define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f 536 #define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f 537 #define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f 538 #define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f 539 #define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f 540 #define mmXDMA_MSTR_CNTL 0x3ec 541 #define mmXDMA_MSTR_STATUS 0x3ed 542 #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee 543 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef 544 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 545 #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 546 #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 547 #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 548 #define mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG 0x3f4 549 #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 550 #define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 551 #define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 552 #define mmHDP_HOST_PATH_CNTL 0xb00 553 #define mmHDP_NONSURFACE_BASE 0xb01 554 #define mmHDP_NONSURFACE_INFO 0xb02 555 #define mmHDP_NONSURFACE_SIZE 0xb03 556 #define mmHDP_NONSURF_FLAGS 0xbc9 557 #define mmHDP_NONSURF_FLAGS_CLR 0xbca 558 #define mmHDP_SW_SEMAPHORE 0xbcb 559 #define mmHDP_DEBUG0 0xbcc 560 #define mmHDP_DEBUG1 0xbcd 561 #define mmHDP_LAST_SURFACE_HIT 0xbce 562 #define mmHDP_TILING_CONFIG 0xbcf 563 #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 564 #define mmHDP_OUTSTANDING_REQ 0xbd1 565 #define mmHDP_ADDR_CONFIG 0xbd2 566 #define mmHDP_MISC_CNTL 0xbd3 567 #define mmHDP_MEM_POWER_LS 0xbd4 568 #define mmHDP_NONSURFACE_PREFETCH 0xbd5 569 #define mmHDP_MEMIO_CNTL 0xbf6 570 #define mmHDP_MEMIO_ADDR 0xbf7 571 #define mmHDP_MEMIO_STATUS 0xbf8 572 #define mmHDP_MEMIO_WR_DATA 0xbf9 573 #define mmHDP_MEMIO_RD_DATA 0xbfa 574 #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 575 #define mmHDP_XDP_D2H_FLUSH 0xc01 576 #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 577 #define mmHDP_XDP_D2H_RSVD_3 0xc03 578 #define mmHDP_XDP_D2H_RSVD_4 0xc04 579 #define mmHDP_XDP_D2H_RSVD_5 0xc05 580 #define mmHDP_XDP_D2H_RSVD_6 0xc06 581 #define mmHDP_XDP_D2H_RSVD_7 0xc07 582 #define mmHDP_XDP_D2H_RSVD_8 0xc08 583 #define mmHDP_XDP_D2H_RSVD_9 0xc09 584 #define mmHDP_XDP_D2H_RSVD_10 0xc0a 585 #define mmHDP_XDP_D2H_RSVD_11 0xc0b 586 #define mmHDP_XDP_D2H_RSVD_12 0xc0c 587 #define mmHDP_XDP_D2H_RSVD_13 0xc0d 588 #define mmHDP_XDP_D2H_RSVD_14 0xc0e 589 #define mmHDP_XDP_D2H_RSVD_15 0xc0f 590 #define mmHDP_XDP_D2H_RSVD_16 0xc10 591 #define mmHDP_XDP_D2H_RSVD_17 0xc11 592 #define mmHDP_XDP_D2H_RSVD_18 0xc12 593 #define mmHDP_XDP_D2H_RSVD_19 0xc13 594 #define mmHDP_XDP_D2H_RSVD_20 0xc14 595 #define mmHDP_XDP_D2H_RSVD_21 0xc15 596 #define mmHDP_XDP_D2H_RSVD_22 0xc16 597 #define mmHDP_XDP_D2H_RSVD_23 0xc17 598 #define mmHDP_XDP_D2H_RSVD_24 0xc18 599 #define mmHDP_XDP_D2H_RSVD_25 0xc19 600 #define mmHDP_XDP_D2H_RSVD_26 0xc1a 601 #define mmHDP_XDP_D2H_RSVD_27 0xc1b 602 #define mmHDP_XDP_D2H_RSVD_28 0xc1c 603 #define mmHDP_XDP_D2H_RSVD_29 0xc1d 604 #define mmHDP_XDP_D2H_RSVD_30 0xc1e 605 #define mmHDP_XDP_D2H_RSVD_31 0xc1f 606 #define mmHDP_XDP_D2H_RSVD_32 0xc20 607 #define mmHDP_XDP_D2H_RSVD_33 0xc21 608 #define mmHDP_XDP_D2H_RSVD_34 0xc22 609 #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 610 #define mmHDP_XDP_P2P_BAR_CFG 0xc24 611 #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 612 #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 613 #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 614 #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 615 #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 616 #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a 617 #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b 618 #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c 619 #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d 620 #define mmHDP_XDP_HDP_MC_CFG 0xc2e 621 #define mmHDP_XDP_HST_CFG 0xc2f 622 #define mmHDP_XDP_SID_CFG 0xc30 623 #define mmHDP_XDP_HDP_IPH_CFG 0xc31 624 #define mmHDP_XDP_SRBM_CFG 0xc32 625 #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 626 #define mmHDP_XDP_P2P_BAR0 0xc34 627 #define mmHDP_XDP_P2P_BAR1 0xc35 628 #define mmHDP_XDP_P2P_BAR2 0xc36 629 #define mmHDP_XDP_P2P_BAR3 0xc37 630 #define mmHDP_XDP_P2P_BAR4 0xc38 631 #define mmHDP_XDP_P2P_BAR5 0xc39 632 #define mmHDP_XDP_P2P_BAR6 0xc3a 633 #define mmHDP_XDP_P2P_BAR7 0xc3b 634 #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c 635 #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d 636 #define mmHDP_XDP_BUSY_STS 0xc3e 637 #define mmHDP_XDP_STICKY 0xc3f 638 #define mmHDP_XDP_CHKN 0xc40 639 #define mmHDP_XDP_DBG_ADDR 0xc41 640 #define mmHDP_XDP_DBG_DATA 0xc42 641 #define mmHDP_XDP_DBG_MASK 0xc43 642 #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 643 644 #endif /* OSS_2_0_D_H */ 645