1 /* $NetBSD: omap3_dssreg.h,v 1.3 2020/04/16 23:29:52 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: omap3_dssreg.h,v 1.3 2020/04/16 23:29:52 rin Exp $"); 31 32 #ifndef OMAP3_DSSREG_H 33 #define OMAP3_DSSREG_H 34 35 #define OMAPFB_DSS_REVISION 0x0000 36 #define OMAPFB_DSS_SYSCONFIG 0x0010 37 #define OMAPFB_DSS_SYSSTATUS 0x0014 38 #define OMAPFB_DSS_IRQSTATUS 0x0018 39 #define OMAPFB_DSS_CONTROL 0x0040 40 #define OMAPFB_DSS_SDI_CONTROL 0x0044 41 #define OMAPFB_DSS_PLL_CONTROL 0x0048 42 #define OMAPFB_DSS_SDI_STATUS 0x005c 43 44 /* display controller */ 45 #define OMAPFB_DISPC_REVISION 0x0400 46 #define OMAPFB_DISPC_SYSCONFIG 0x0410 47 #define OMAPFB_DISPC_SYSSTATUS 0x0414 48 #define OMAPFB_DISPC_IRQSTATUS 0x0418 49 #define OMAPFB_DISPC_IRQENABLE 0x041c 50 #define OMAPFB_DISPC_CONTROL 0x0440 51 #define OMAPFB_DISPC_CONFIG 0x0444 52 #define OMAPFB_DISPC_DEFAULT_COLOR_0 0x044c 53 #define OMAPFB_DISPC_DEFAULT_COLOR_1 0x0450 54 #define OMAPFB_DISPC_TRANS_COLOR_0 0x0454 55 #define OMAPFB_DISPC_TRANS_COLOR_1 0x0458 56 #define OMAPFB_DISPC_LINE_STATUS 0x045c 57 #define OMAPFB_DISPC_LINE_NUMBER 0x0460 58 #define OMAPFB_DISPC_TIMING_H 0x0464 59 #define OMAPFB_DISPC_TIMING_V 0x0468 60 #define OMAPFB_DISPC_POL_FREQ 0x046c 61 #define OMAPFB_DISPC_DIVISOR 0x0470 62 #define OMAPFB_DISPC_GLOBAL_ALPHA 0x0474 63 #define OMAPFB_DISPC_SIZE_DIG 0x0478 64 #define OMAPFB_DISPC_SIZE_LCD 0x047c 65 #define OMAPFB_DISPC_GFX_BASE_0 0x0480 66 #define OMAPFB_DISPC_GFX_BASE_1 0x0484 67 #define OMAPFB_DISPC_GFX_POSITION 0x0488 68 #define OMAPFB_DISPC_GFX_SIZE 0x048c 69 #define OMAPFB_DISPC_GFX_ATTRIBUTES 0x04a0 70 #define OMAPFB_DISPC_GFX_FIFO_THRESH 0x04a4 71 #define OMAPFB_DISPC_GFX_FIFO_SZ_STATUS 0x04a8 72 #define OMAPFB_DISPC_GFX_ROW_INC 0x04ac 73 #define OMAPFB_DISPC_GFX_PIXEL_INC 0x04b0 74 #define OMAPFB_DISPC_GFX_WINDOW_SKIP 0x04b4 75 #define OMAPFB_DISPC_GFX_TABLE_BASE 0x04b8 76 #define OMAPFB_DISPC_DATA_CYCLE_0 0x05d4 77 #define OMAPFB_DISPC_DATA_CYCLE_1 0x05d8 78 #define OMAPFB_DISPC_DATA_CYCLE_2 0x05dc 79 #define OMAPFB_DISPC_CPR_COEFF_R 0x0620 80 #define OMAPFB_DISPC_CPR_COEFF_G 0x0624 81 #define OMAPFB_DISPC_CPR_COEFF_B 0x0628 82 #define OMAPFB_DISPC_GFX_PRELOAD 0x062c 83 84 /* VID1 */ 85 #define OMAPFB_DISPC_VID1_BASE_0 0x04bc 86 #define OMAPFB_DISPC_VID1_BASE_1 0x04c0 87 #define OMAPFB_DISPC_VID1_POSITION 0x04c4 88 #define OMAPFB_DISPC_VID1_SIZE 0x04c8 /* displayed size */ 89 #define OMAPFB_DISPC_VID1_ATTRIBUTES 0x04cc 90 #define OMAPFB_DISPC_VID1_FIFO_THRESH 0x04d0 91 #define OMAPFB_DISPC_VID1_FIFO_SZ_STAT 0x04d4 92 #define OMAPFB_DISPC_VID1_ROW_INC 0x04d8 93 #define OMAPFB_DISPC_VID1_PIXEL_INC 0x04dc 94 #define OMAPFB_DISPC_VID1_FIR 0x04e0 95 #define OMAPFB_DISPC_VID1_PICTURE_SIZE 0x04e4 /* original size */ 96 #define OMAPFB_DISPC_VID1_ACCU_0 0x04e8 97 #define OMAPFB_DISPC_VID1_ACCU_1 0x04ec 98 #define OMAPFB_DISPC_VID1_COEFF_H_0 0x04d0 99 #define OMAPFB_DISPC_VID1_COEFF_HV_0 0x04d4 100 #define OMAPFB_DISPC_VID1_COEFF_H_1 0x04d8 101 #define OMAPFB_DISPC_VID1_COEFF_HV_1 0x04dc 102 #define OMAPFB_DISPC_VID1_COEFF_H_2 0x04e0 103 #define OMAPFB_DISPC_VID1_COEFF_HV_2 0x04e4 104 #define OMAPFB_DISPC_VID1_COEFF_H_3 0x04e8 105 #define OMAPFB_DISPC_VID1_COEFF_HV_3 0x04ec 106 #define OMAPFB_DISPC_VID1_COEFF_H_4 0x04f0 107 #define OMAPFB_DISPC_VID1_COEFF_HV_4 0x04f4 108 #define OMAPFB_DISPC_VID1_COEFF_H_5 0x04f8 109 #define OMAPFB_DISPC_VID1_COEFF_HV_5 0x04fc 110 #define OMAPFB_DISPC_VID1_COEFF_H_6 0x0500 111 #define OMAPFB_DISPC_VID1_COEFF_HV_6 0x0504 112 #define OMAPFB_DISPC_VID1_COEFF_H_7 0x0508 113 #define OMAPFB_DISPC_VID1_COEFF_HV_7 0x050c 114 #define OMAPFB_DISPC_VID1_CONV_COEFF_0 0x0530 115 #define OMAPFB_DISPC_VID1_CONV_COEFF_1 0x0534 116 #define OMAPFB_DISPC_VID1_CONV_COEFF_2 0x0538 117 #define OMAPFB_DISPC_VID1_CONV_COEFF_3 0x053c 118 #define OMAPFB_DISPC_VID1_CONV_COEFF_4 0x0540 119 #define OMAPFB_DISPC_VID1_FIR_COEFF_V0 0x05e0 120 #define OMAPFB_DISPC_VID1_FIR_COEFF_V1 0x05e4 121 #define OMAPFB_DISPC_VID1_FIR_COEFF_V2 0x05e8 122 #define OMAPFB_DISPC_VID1_FIR_COEFF_V3 0x05ec 123 #define OMAPFB_DISPC_VID1_FIR_COEFF_V4 0x05f0 124 #define OMAPFB_DISPC_VID1_FIR_COEFF_V5 0x05f4 125 #define OMAPFB_DISPC_VID1_FIR_COEFF_V6 0x05f8 126 #define OMAPFB_DISPC_VID1_FIR_COEFF_V7 0x05fc 127 #define OMAPFB_DISPC_VID1_PRELOAD 0x0630 128 129 /* VID2 */ 130 #define OMAPFB_DISPC_VID2_BASE_0 0x054c 131 #define OMAPFB_DISPC_VID2_BASE_1 0x0550 132 #define OMAPFB_DISPC_VID2_POSITION 0x0554 133 #define OMAPFB_DISPC_VID2_SIZE 0x0558 134 #define OMAPFB_DISPC_VID2_ATTRIBUTES 0x055c 135 #define OMAPFB_DISPC_VID2_FIFO_THRESH 0x0560 136 #define OMAPFB_DISPC_VID2_FIFO_SZ_STAT 0x0564 137 #define OMAPFB_DISPC_VID2_ROW_INC 0x0568 138 #define OMAPFB_DISPC_VID2_PIXEL_INC 0x056c 139 #define OMAPFB_DISPC_VID2_FIR 0x0570 140 #define OMAPFB_DISPC_VID2_PICTURE_SIZE 0x0574 141 #define OMAPFB_DISPC_VID2_ACCU_0 0x0578 142 #define OMAPFB_DISPC_VID2_ACCU_1 0x057c 143 #define OMAPFB_DISPC_VID2_COEFF_H_0 0x0580 144 #define OMAPFB_DISPC_VID2_COEFF_HV_0 0x0584 145 #define OMAPFB_DISPC_VID2_COEFF_H_1 0x0588 146 #define OMAPFB_DISPC_VID2_COEFF_HV_1 0x058c 147 #define OMAPFB_DISPC_VID2_COEFF_H_2 0x0590 148 #define OMAPFB_DISPC_VID2_COEFF_HV_2 0x0594 149 #define OMAPFB_DISPC_VID2_COEFF_H_3 0x0598 150 #define OMAPFB_DISPC_VID2_COEFF_HV_3 0x059c 151 #define OMAPFB_DISPC_VID2_COEFF_H_4 0x05a0 152 #define OMAPFB_DISPC_VID2_COEFF_HV_4 0x05a4 153 #define OMAPFB_DISPC_VID2_COEFF_H_5 0x05a8 154 #define OMAPFB_DISPC_VID2_COEFF_HV_5 0x05ac 155 #define OMAPFB_DISPC_VID2_COEFF_H_6 0x05b0 156 #define OMAPFB_DISPC_VID2_COEFF_HV_6 0x05b4 157 #define OMAPFB_DISPC_VID2_COEFF_H_7 0x05b8 158 #define OMAPFB_DISPC_VID2_COEFF_HV_7 0x05bc 159 #define OMAPFB_DISPC_VID2_CONV_COEFF_0 0x05c0 160 #define OMAPFB_DISPC_VID2_CONV_COEFF_1 0x05c4 161 #define OMAPFB_DISPC_VID2_CONV_COEFF_2 0x05c8 162 #define OMAPFB_DISPC_VID2_CONV_COEFF_3 0x05cc 163 #define OMAPFB_DISPC_VID2_CONV_COEFF_4 0x05d0 164 #define OMAPFB_DISPC_VID2_FIR_COEFF_V0 0x0670 165 #define OMAPFB_DISPC_VID2_FIR_COEFF_V1 0x0674 166 #define OMAPFB_DISPC_VID2_FIR_COEFF_V2 0x0678 167 #define OMAPFB_DISPC_VID2_FIR_COEFF_V3 0x067c 168 #define OMAPFB_DISPC_VID2_FIR_COEFF_V4 0x0680 169 #define OMAPFB_DISPC_VID2_FIR_COEFF_V5 0x0684 170 #define OMAPFB_DISPC_VID2_FIR_COEFF_V6 0x0688 171 #define OMAPFB_DISPC_VID2_FIR_COEFF_V7 0x068c 172 #define OMAPFB_DISPC_VID2_PRELOAD 0x0634 173 174 /* video encoder */ 175 #define OMAPFB_VENC_REV_ID 0x0c00 176 #define OMAPFB_VENC_STATUS 0x0c04 177 #define OMAPFB_VENC_F_CONTROL 0x0c08 178 #define OMAPFB_VENC_VIDOUT_CTRL 0x0c10 179 #define OMAPFB_VENC_SYNC_CTRL 0x0c14 180 #define OMAPFB_VENC_LLEN 0x0c1c 181 #define OMAPFB_VENC_FLENS 0x0c20 182 #define OMAPFB_VENC_HFLTR_CTRL 0x0c24 183 #define OMAPFB_VENC_CC_CARR_WSS_CARR 0x0c28 184 #define OMAPFB_VENC_C_PHASE 0x0c2c 185 #define OMAPFB_VENC_GAIN_U 0x0c30 186 #define OMAPFB_VENC_GAIN_V 0x0c34 187 #define OMAPFB_VENC_GAIN_Y 0x0c38 188 #define OMAPFB_VENC_BLACK_LEVEL 0x0c3c 189 #define OMAPFB_VENC_BLANK_LEVEL 0x0c40 190 #define OMAPFB_VENC_X_COLOR 0x0c44 191 #define OMAPFB_VENC_M_CONTROL 0x0c48 192 #define OMAPFB_VENC_BSTAMP_WSS_DATA 0x0c4c 193 #define OMAPFB_VENC_S_CARR 0x0c50 194 #define OMAPFB_VENC_LINE21 0x0c54 195 #define OMAPFB_VENC_LN_SEL 0x0c58 196 #define OMAPFB_VENC_L21_WC_CTL 0x0c5c 197 #define OMAPFB_VENC_HTRIGGER_VTRIGGER 0x0c60 198 #define OMAPFB_VENC_SAVID_EAVID 0x0c64 199 #define OMAPFB_VENC_FLEN_FAL 0x0c68 200 #define OMAPFB_VENC_LAL_PHASE_RESET 0x0c6c 201 #define OMAPFB_VENC_HS_INT_START_STOP_X 0x0c70 202 #define OMAPFB_VENC_HS_EXT_START_STOP_X 0x0c74 203 #define OMAPFB_VENC_VS_INT_START 0x0c78 204 #define OMAPFB_VENC_VS_INT_STOP_X_VS_INT_START_Y 0x0c7c 205 #define OMAPFB_VENC_VS_INT_STOP_Y_VS_EXT_START_X 0x0c80 206 #define OMAPFB_VENC_VS_EXT_STOP_X_VS_EXT_START_Y 0x0c84 207 #define OMAPFB_VENC_VS_EXT_STOP_Y 0x0c88 208 #define OMAPFB_VENC_AVID_START_STOP_X 0x0c90 209 #define OMAPFB_VENC_AVID_START_STOP_Y 0x0c94 210 #define OMAPFB_VENC_FID_START_X_FID_START_Y 0x0ca0 211 #define OMAPFB_VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 0x0ca4 212 #define OMAPFB_VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 0x0ca8 213 #define OMAPFB_VENC_TVDETGP_INT_START_STOP_X 0x0cb0 214 #define OMAPFB_VENC_TVDETGP_INT_START_STOP_Y 0x0cb4 215 #define OMAPFB_VENC_GEN_CTRL 0x0cb8 216 #define OMAPFB_VENC_OUTPUT_CONTROL 0x0cc4 217 #define OMAPFB_VENC_OUTPUT_TEST 0x0cc8 218 219 /* revision registers */ 220 #define OMAP_REVISION_MINOR_MASK 0x0000000f 221 #define OMAP_REVISION_MAJOR_MASK 0x000000f0 222 223 /* sysconfig registers */ 224 #define OMAP_SYSCONF_AUTOIDLE 0x00000001 225 #define OMAP_SYSCONF_SOFTRESET 0x00000002 226 227 /* sysstatus registers */ 228 #define OMAP_SYSSTAT_RESET_DONE 0x00000001 229 230 /* OMAPFB_DSS_IRQSTATUS */ 231 #define OMAP_DSSIRQ_DISPC 0x00000001 232 #define OMAP_DSSIRQ_DSI 0x00000002 233 234 /* OMAPFB_DSS_CONTROL */ 235 #define OMAP_DSSCTRL_VENC_SVIDEO 0x00000040 /* composite otherwise */ 236 #define OMAP_DSSCTRL_POWERDN_BGZ 0x00000020 /* power-down band gap up */ 237 #define OMAP_DSSCTRL_DAC_DEMEN 0x00000010 /* dynamic element match */ 238 #define OMAP_DSSCTRL_VENC_CLOCK_4X 0x00000008 239 #define OMAP_DSSCTRL_CLOCK_MODE 0x00000004 240 #define OMAP_DSSCTRL_DSI_CLK_SWITCH 0x00000002 /* use DSI PLL */ 241 #define OMAP_DSSCTRL_DISPC_CLK_SWITCH 0x00000001 /* use DSI PLL */ 242 243 /* additional bits in OMAPFB_DISPC_SYSCONFIG */ 244 #define OMAP_DISPC_SYSC_FORCE_STANDBY 0x00000000 245 #define OMAP_DISPC_SYSC_NO_STANDBY 0x00001000 246 #define OMAP_DISPC_SYSC_SMART_STANDBY 0x00002000 247 #define OMAP_DISPC_SYSC_STANDBY_MASK 0x00003000 248 #define OMAP_DISPC_SYSC_CLOCKS_OFF 0x00000000 249 #define OMAP_DISPC_SYSC_FCLOCK_OFF 0x00000100 250 #define OMAP_DISPC_SYSC_ICLOCK_OFF 0x00000200 251 #define OMAP_DISPC_SYSC_CLOCK_ON 0x00000300 252 #define OMAP_DISPC_SYSC_CLOCK_MASK 0x00000300 253 #define OMAP_DISPC_SYSC_FORCE_IDLE 0x00000000 254 #define OMAP_DISPC_SYSC_NO_IDLE 0x00000008 255 #define OMAP_DISPC_SYSC_SMART_IDLE 0x00000010 256 #define OMAP_DISPC_SYSC_IDLE_MASK 0x00000018 257 #define OMAP_DISPC_SYSC_WAKEUP_ENABLE 0x00000004 258 259 /* OMAPFB_DISPC_GFX_ATTRIBUTES */ 260 #define OMAP_DISPC_ATTR_REFRESH_FIFO 0x00008000 /* refresh from FIFO only */ 261 #define OMAP_DISPC_ATTR_PRIORITY_HIGH 0x00004000 262 #define OMAP_DISPC_ATTR_ROT_NONE 0x00000000 263 #define OMAP_DISPC_ATTR_ROT_90 0x00001000 /* for 24bit packed only */ 264 #define OMAP_DISPC_ATTR_ROT_180 0x00002000 265 #define OMAP_DISPC_ATTR_ROT_270 0x00003000 266 #define OMAP_DISPC_ATTR_FIFO_PRELOAD 0x00000800 /* use threshold for FIFO */ 267 #define OMAP_DISPC_ATTR_BIG_ENDIAN 0x00000400 /* little endian otherwise */ 268 #define OMAP_DISPC_ATTR_NIBBLE 0x00000200 /* for < 8 bit only */ 269 #define OMAP_DISPC_ATTR_24BIT_OUT 0x00000100 /* LCD otherwise */ 270 #define OMAP_DISPC_ATTR_BURST_4x32 0x00000000 271 #define OMAP_DISPC_ATTR_BURST_8x32 0x00000040 272 #define OMAP_DISPC_ATTR_BURST_16x32 0x00000080 273 #define OMAP_DISPC_ATTR_REPLICATION 0x00000020 274 #define OMAP_DISPC_ATTR_8BIT 0x00000006 275 #define OMAP_DISPC_ATTR_RGB12 0x00000008 276 #define OMAP_DISPC_ATTR_ARGB16 0x0000000a 277 #define OMAP_DISPC_ATTR_RGB16 0x0000000c 278 #define OMAP_DISPC_ATTR_RGB24 0x00000010 /* 32bit pixels */ 279 #define OMAP_DISPC_ATTR_RGB24P 0x00000012 /* 24bit packed */ 280 #define OMAP_DISPC_ATTR_ARGB32 0x00000018 281 #define OMAP_DISPC_ATTR_RGBA32 0x0000001a 282 #define OMAP_DISPC_ATTR_RGBX 0x0000001c 283 #define OMAP_DISPC_ATTR_ENABLE 0x00000001 284 285 /* OMAPFB_DISPC_CONTROL */ 286 #define OMAP_DISPC_CTRL_LCD_ACTIVE_HIGH 0x20000000 287 #define OMAP_DISPC_CTRL_LCD_SIGNAL 0x10000000 288 #define OMAP_DISPC_CTRL_PIXEL_CLOCK 0x08000000 289 #define OMAP_DISPC_CTRL_GO_DIGITAL 0x00000040 290 #define OMAP_DISPC_CTRL_GO_LCD 0x00000020 291 #define OMAP_DISPC_CTRL_MONO_8_BYTE 0x00000010 /* 4 otherwise */ 292 #define OMAP_DISPC_CTRL_ACTIVE_MTRX 0x00000008 /* disable STN dither */ 293 #define OMAP_DISPC_CTRL_MONO 0x00000004 294 #define OMAP_DISPC_CTRL_DIGITAL_ENABLE 0x00000002 295 #define OMAP_DISPC_CTRL_LCD_ENABLE 0x00000001 296 297 /* OMAPFB_VENC_F_CONTROL */ 298 #define OMAP_VENCFCTL_RESET 0x00000100 299 #define OMAP_VENCFCTL_VID_EXTERNAL 0x00000000 300 #define OMAP_VENCFCTL_VID_COLOR_BAR 0x00000040 301 #define OMAP_VENCFCTL_VID_BACKGROUND 0x00000080 302 #define OMAP_VENCFCTL_RGBF 0x00000020 303 #define OMAP_VENCFCTL_BG_COLOR_MASK 0x0000001c 304 #define OMAP_VENCFCTL_FMT_444RGB 0x00000000 305 #define OMAP_VENCFCTL_FMT_444 0x00000001 306 #define OMAP_VENCFCTL_FMT_422 0x00000002 307 #define OMAP_VENCFCTL_FMT_ITU_422 0x00000003 308 309 /* OMAPFB_DISPC_CONFIG */ 310 #define OMAP_DISPC_CFG_TV_ALPHA_EN 0x00080000 311 #define OMAP_DISPC_CFG_LCD_ALPHA_EN 0x00040000 312 #define OMAP_DISPC_CFG_FIFO_FILL_ALL 0x00020000 /* fill all FIFOs if at least one is low */ 313 #define OMAP_DISPC_CFG_FIFOHANDCHECK 0x00010000 314 #define OMAP_DISPC_CFG_CPR 0x00008000 /* color phase rotation */ 315 #define OMAP_DISPC_CFG_FIFOMERGE 0x00004000 316 #define OMAP_DISPC_CFG_TCKDIGSELECTION 0x00002000 /* transp. color key */ 317 #define OMAP_DISPC_CFG_TCKDIGENABLE 0x00001000 318 #define OMAP_DISPC_CFG_TCKLCDSELECTION 0x00000800 /* transp. color key */ 319 #define OMAP_DISPC_CFG_TCKLCDENABLE 0x00000400 320 #define OMAP_DISPC_CFG_FUNCGATED 0x00000200 /* functional clocks */ 321 #define OMAP_DISPC_CFG_ACBIAS_GATED 0x00000100 322 #define OMAP_DISPC_CFG_VSYNC_GATED 0x00000080 323 #define OMAP_DISPC_CFG_HSYNC_GATED 0x00000040 324 #define OMAP_DISPC_CFG_PIXELCLK_GATED 0x00000020 325 #define OMAP_DISPC_CFG_PIXELDATA_GATED 0x00000010 326 #define OMAP_DISPC_CFG_PALGAMMATABLE 0x00000008 /* use LUT as gamma in >8bit */ 327 #define OMAP_DISPC_CFG_LUT_LOAD_ALWAYS 0x00000000 328 #define OMAP_DISPC_CFG_LUT_LOAD 0x00000002 329 #define OMAP_DISPC_CFG_LUT_LOAD_F_ONLY 0x00000004 /* only frame data */ 330 #define OMAP_DISPC_CFG_LUT_LOAD_ONCE 0x00000006 /* load once, then 4 */ 331 #define OMAP_DISPC_CFG_PIXEL_GATED 0x00000001 /* active matrix only */ 332 333 /* OMAPFB_DISPC_VIDn_ATTRIBUTES */ 334 #define OMAP_VID_ATTR_SELFREFRESH 0x01000000 /* no DMA, display from FIFO only */ 335 #define OMAP_VID_ATTR_HIGH_PRIORITY 0x00800000 336 #define OMAP_VID_ATTR_BUFFER_SPLIT 0x00400000 337 #define OMAP_VID_ATTR_TAP_5 0x00200000 /* resize, 3 taps otherwise */ 338 #define OMAP_VID_ATTR_DMA_OPT 0x00100000 /* for rotation */ 339 #define OMAP_VID_ATTR_FIFO_PRELOAD 0x00080000 /* use high threshold reg */ 340 #define OMAP_VID_ATTR_ROWREPEAT 0x00040000 /* for YUV */ 341 #define OMAP_VID_ATTR_BIG_ENDIAN 0x00020000 342 #define OMAP_VID_ATTR_CHANNEL_24BIT 0x00010000 /* LCD otherwise */ 343 #define OMAP_VID_ATTR_BURST_4x32 0x00000000 344 #define OMAP_VID_ATTR_BURST_8x32 0x00004000 345 #define OMAP_VID_ATTR_BURST_16x32 0x00008000 346 #define OMAP_VID_ATTR_BURST_MASK 0x0000c000 347 #define OMAP_VID_ATTR_ROT_NONE 0x00000000 348 #define OMAP_VID_ATTR_ROT_90 0x00001000 349 #define OMAP_VID_ATTR_ROT_180 0x00002000 350 #define OMAP_VID_ATTR_ROT_270 0x00003000 351 #define OMAP_VID_ATTR_ROT_MASK 0x00003000 352 #define OMAP_VID_ATTR_FULLRANGE 0x00000800 /* YUV */ 353 #define OMAP_VID_ATTR_REPLICATION 0x00000400 /* 16bit -> 24bit */ 354 #define OMAP_VID_ATTR_COLORSPACE_CONV 0x00000200 /* CbYCr -> RGB */ 355 #define OMAP_VID_ATTR_VRESIZE_UP 0x00000100 /* down otherwise */ 356 #define OMAP_VID_ATTR_HRESIZE_UP 0x00000080 357 #define OMAP_VID_ATTR_VRESIZE_ENABLE 0x00000040 358 #define OMAP_VID_ATTR_HRESIZE_ENABLE 0x00000020 359 /* VID1 doesn't support any alpha formats */ 360 #define OMAP_VID_ATTR_RGB12 0x00000008 361 #define OMAP_VID_ATTR_ARGB16 0x0000000a 362 #define OMAP_VID_ATTR_RGB16 0x0000000c 363 #define OMAP_VID_ATTR_RGB24 0x00000010 /* 32bit pixels */ 364 #define OMAP_VID_ATTR_RGB24P 0x00000012 /* 24bit packed */ 365 #define OMAP_VID_ATTR_YUV2 0x00000014 366 #define OMAP_VID_ATTR_UYVY 0x00000016 367 #define OMAP_VID_ATTR_ARGB32 0x00000018 368 #define OMAP_VID_ATTR_RGBA32 0x0000001a 369 #define OMAP_VID_ATTR_RGBX 0x0000001c 370 371 #define OMAP_VID_ATTR_ENABLE 0x00000001 372 373 #endif /* OMAP3_DSSREG_H */ 374