xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/cl5070.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: cl5070.h,v 1.2 2021/12/18 23:45:33 riastradh Exp $	*/
2 
3 /* SPDX-License-Identifier: MIT */
4 #ifndef __NVIF_CL5070_H__
5 #define __NVIF_CL5070_H__
6 
7 #define NV50_DISP_MTHD                                                     0x00
8 
9 struct nv50_disp_mthd_v0 {
10 	__u8  version;
11 #define NV50_DISP_SCANOUTPOS                                               0x00
12 	__u8  method;
13 	__u8  head;
14 	__u8  pad03[5];
15 };
16 
17 struct nv50_disp_scanoutpos_v0 {
18 	__u8  version;
19 	__u8  pad01[7];
20 	__s64 time[2];
21 	__u16 vblanks;
22 	__u16 vblanke;
23 	__u16 vtotal;
24 	__u16 vline;
25 	__u16 hblanks;
26 	__u16 hblanke;
27 	__u16 htotal;
28 	__u16 hline;
29 };
30 
31 struct nv50_disp_mthd_v1 {
32 	__u8  version;
33 #define NV50_DISP_MTHD_V1_ACQUIRE                                          0x01
34 #define NV50_DISP_MTHD_V1_RELEASE                                          0x02
35 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
36 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
37 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
38 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
39 #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK                                  0x25
40 #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI                                  0x26
41 	__u8  method;
42 	__u16 hasht;
43 	__u16 hashm;
44 	__u8  pad06[2];
45 };
46 
47 struct nv50_disp_acquire_v0 {
48 	__u8  version;
49 	__u8  or;
50 	__u8  link;
51 	__u8  pad03[5];
52 };
53 
54 struct nv50_disp_dac_load_v0 {
55 	__u8  version;
56 	__u8  load;
57 	__u8  pad02[2];
58 	__u32 data;
59 };
60 
61 struct nv50_disp_sor_hda_eld_v0 {
62 	__u8  version;
63 	__u8  pad01[7];
64 	__u8  data[];
65 };
66 
67 struct nv50_disp_sor_hdmi_pwr_v0 {
68 	__u8  version;
69 	__u8  state;
70 	__u8  max_ac_packet;
71 	__u8  rekey;
72 	__u8  avi_infoframe_length;
73 	__u8  vendor_infoframe_length;
74 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0)
75 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1)
76 	__u8  scdc;
77 	__u8  pad07[1];
78 };
79 
80 struct nv50_disp_sor_lvds_script_v0 {
81 	__u8  version;
82 	__u8  pad01[1];
83 	__u16 script;
84 	__u8  pad04[4];
85 };
86 
87 struct nv50_disp_sor_dp_mst_link_v0 {
88 	__u8  version;
89 	__u8  state;
90 	__u8  pad02[6];
91 };
92 
93 struct nv50_disp_sor_dp_mst_vcpi_v0 {
94 	__u8  version;
95 	__u8  pad01[1];
96 	__u8  start_slot;
97 	__u8  num_slots;
98 	__u16 pbn;
99 	__u16 aligned_pbn;
100 };
101 #endif
102