1 /* $NetBSD: nouveau_nvkm_subdev_bios_pll.c,v 1.4 2021/12/18 23:45:38 riastradh Exp $ */
2
3 /*
4 * Copyright 2005-2006 Erik Waling
5 * Copyright 2006 Stephane Marchesin
6 * Copyright 2007-2009 Stuart Bennett
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
23 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_bios_pll.c,v 1.4 2021/12/18 23:45:38 riastradh Exp $");
28
29 #include <subdev/bios.h>
30 #include <subdev/bios/bit.h>
31 #include <subdev/bios/bmp.h>
32 #include <subdev/bios/pll.h>
33 #include <subdev/vga.h>
34
35
36 struct pll_mapping {
37 u8 type;
38 u32 reg;
39 };
40
41 static struct pll_mapping
42 nv04_pll_mapping[] = {
43 { PLL_CORE , 0x680500 },
44 { PLL_MEMORY, 0x680504 },
45 { PLL_VPLL0 , 0x680508 },
46 { PLL_VPLL1 , 0x680520 },
47 {}
48 };
49
50 static struct pll_mapping
51 nv40_pll_mapping[] = {
52 { PLL_CORE , 0x004000 },
53 { PLL_MEMORY, 0x004020 },
54 { PLL_VPLL0 , 0x680508 },
55 { PLL_VPLL1 , 0x680520 },
56 {}
57 };
58
59 static struct pll_mapping
60 nv50_pll_mapping[] = {
61 { PLL_CORE , 0x004028 },
62 { PLL_SHADER, 0x004020 },
63 { PLL_UNK03 , 0x004000 },
64 { PLL_MEMORY, 0x004008 },
65 { PLL_UNK40 , 0x00e810 },
66 { PLL_UNK41 , 0x00e818 },
67 { PLL_UNK42 , 0x00e824 },
68 { PLL_VPLL0 , 0x614100 },
69 { PLL_VPLL1 , 0x614900 },
70 {}
71 };
72
73 static struct pll_mapping
74 g84_pll_mapping[] = {
75 { PLL_CORE , 0x004028 },
76 { PLL_SHADER, 0x004020 },
77 { PLL_MEMORY, 0x004008 },
78 { PLL_VDEC , 0x004030 },
79 { PLL_UNK41 , 0x00e818 },
80 { PLL_VPLL0 , 0x614100 },
81 { PLL_VPLL1 , 0x614900 },
82 {}
83 };
84
85 static u32
pll_limits_table(struct nvkm_bios * bios,u8 * ver,u8 * hdr,u8 * cnt,u8 * len)86 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
87 {
88 struct bit_entry bit_C;
89 u32 data = 0x0000;
90
91 if (!bit_entry(bios, 'C', &bit_C)) {
92 if (bit_C.version == 1 && bit_C.length >= 10)
93 data = nvbios_rd16(bios, bit_C.offset + 8);
94 if (bit_C.version == 2 && bit_C.length >= 4)
95 data = nvbios_rd32(bios, bit_C.offset + 0);
96 if (data) {
97 *ver = nvbios_rd08(bios, data + 0);
98 *hdr = nvbios_rd08(bios, data + 1);
99 *len = nvbios_rd08(bios, data + 2);
100 *cnt = nvbios_rd08(bios, data + 3);
101 return data;
102 }
103 }
104
105 if (bmp_version(bios) >= 0x0524) {
106 data = nvbios_rd16(bios, bios->bmp_offset + 142);
107 if (data) {
108 *ver = nvbios_rd08(bios, data + 0);
109 *hdr = 1;
110 *cnt = 1;
111 *len = 0x18;
112 return data;
113 }
114 }
115
116 *ver = 0x00;
117 return data;
118 }
119
120 static struct pll_mapping *
pll_map(struct nvkm_bios * bios)121 pll_map(struct nvkm_bios *bios)
122 {
123 struct nvkm_device *device = bios->subdev.device;
124 switch (device->card_type) {
125 case NV_04:
126 case NV_10:
127 case NV_11:
128 case NV_20:
129 case NV_30:
130 return nv04_pll_mapping;
131 break;
132 case NV_40:
133 return nv40_pll_mapping;
134 case NV_50:
135 if (device->chipset == 0x50)
136 return nv50_pll_mapping;
137 else
138 if (device->chipset < 0xa3 ||
139 device->chipset == 0xaa ||
140 device->chipset == 0xac)
141 return g84_pll_mapping;
142 /* fall through */
143 default:
144 return NULL;
145 }
146 }
147
148 static u32
pll_map_reg(struct nvkm_bios * bios,u32 reg,u32 * type,u8 * ver,u8 * len)149 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
150 {
151 struct pll_mapping *map;
152 u8 hdr, cnt;
153 u32 data;
154
155 data = pll_limits_table(bios, ver, &hdr, &cnt, len);
156 if (data && *ver >= 0x30) {
157 data += hdr;
158 while (cnt--) {
159 if (nvbios_rd32(bios, data + 3) == reg) {
160 *type = nvbios_rd08(bios, data + 0);
161 return data;
162 }
163 data += *len;
164 }
165 return 0x0000;
166 }
167
168 map = pll_map(bios);
169 while (map && map->reg) {
170 if (map->reg == reg && *ver >= 0x20) {
171 u32 addr = (data += hdr);
172 *type = map->type;
173 while (cnt--) {
174 if (nvbios_rd32(bios, data) == map->reg)
175 return data;
176 data += *len;
177 }
178 return addr;
179 } else
180 if (map->reg == reg) {
181 *type = map->type;
182 return data + 1;
183 }
184 map++;
185 }
186
187 return 0x0000;
188 }
189
190 static u32
pll_map_type(struct nvkm_bios * bios,u8 type,u32 * reg,u8 * ver,u8 * len)191 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
192 {
193 struct pll_mapping *map;
194 u8 hdr, cnt;
195 u32 data;
196
197 data = pll_limits_table(bios, ver, &hdr, &cnt, len);
198 if (data && *ver >= 0x30) {
199 data += hdr;
200 while (cnt--) {
201 if (nvbios_rd08(bios, data + 0) == type) {
202 if (*ver < 0x50)
203 *reg = nvbios_rd32(bios, data + 3);
204 else
205 *reg = 0;
206 return data;
207 }
208 data += *len;
209 }
210 return 0x0000;
211 }
212
213 map = pll_map(bios);
214 while (map && map->reg) {
215 if (map->type == type && *ver >= 0x20) {
216 u32 addr = (data += hdr);
217 *reg = map->reg;
218 while (cnt--) {
219 if (nvbios_rd32(bios, data) == map->reg)
220 return data;
221 data += *len;
222 }
223 return addr;
224 } else
225 if (map->type == type) {
226 *reg = map->reg;
227 return data + 1;
228 }
229 map++;
230 }
231
232 return 0x0000;
233 }
234
235 int
nvbios_pll_parse(struct nvkm_bios * bios,u32 type,struct nvbios_pll * info)236 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
237 {
238 struct nvkm_subdev *subdev = &bios->subdev;
239 struct nvkm_device *device = subdev->device;
240 u8 ver, len;
241 u32 reg = type;
242 u32 data;
243
244 if (type > PLL_MAX) {
245 reg = type;
246 data = pll_map_reg(bios, reg, &type, &ver, &len);
247 } else {
248 data = pll_map_type(bios, type, ®, &ver, &len);
249 }
250
251 if (ver && !data)
252 return -ENOENT;
253
254 memset(info, 0, sizeof(*info));
255 info->type = type;
256 info->reg = reg;
257
258 switch (ver) {
259 case 0x00:
260 break;
261 case 0x10:
262 case 0x11:
263 info->vco1.min_freq = nvbios_rd32(bios, data + 0);
264 info->vco1.max_freq = nvbios_rd32(bios, data + 4);
265 info->vco2.min_freq = nvbios_rd32(bios, data + 8);
266 info->vco2.max_freq = nvbios_rd32(bios, data + 12);
267 info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16);
268 info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20);
269 info->vco1.max_inputfreq = INT_MAX;
270 info->vco2.max_inputfreq = INT_MAX;
271
272 info->max_p = 0x7;
273 info->max_p_usable = 0x6;
274
275 /* these values taken from nv30/31/36 */
276 switch (bios->version.chip) {
277 case 0x36:
278 info->vco1.min_n = 0x5;
279 break;
280 default:
281 info->vco1.min_n = 0x1;
282 break;
283 }
284 info->vco1.max_n = 0xff;
285 info->vco1.min_m = 0x1;
286 info->vco1.max_m = 0xd;
287
288 /*
289 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
290 * table version (apart from nv35)), N2 is compared to
291 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
292 * save a comparison
293 */
294 info->vco2.min_n = 0x4;
295 switch (bios->version.chip) {
296 case 0x30:
297 case 0x35:
298 info->vco2.max_n = 0x1f;
299 break;
300 default:
301 info->vco2.max_n = 0x28;
302 break;
303 }
304 info->vco2.min_m = 0x1;
305 info->vco2.max_m = 0x4;
306 break;
307 case 0x20:
308 case 0x21:
309 info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000;
310 info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000;
311 info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000;
312 info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000;
313 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
314 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
315 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000;
316 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000;
317 info->vco1.min_n = nvbios_rd08(bios, data + 20);
318 info->vco1.max_n = nvbios_rd08(bios, data + 21);
319 info->vco1.min_m = nvbios_rd08(bios, data + 22);
320 info->vco1.max_m = nvbios_rd08(bios, data + 23);
321 info->vco2.min_n = nvbios_rd08(bios, data + 24);
322 info->vco2.max_n = nvbios_rd08(bios, data + 25);
323 info->vco2.min_m = nvbios_rd08(bios, data + 26);
324 info->vco2.max_m = nvbios_rd08(bios, data + 27);
325
326 info->max_p = nvbios_rd08(bios, data + 29);
327 info->max_p_usable = info->max_p;
328 if (bios->version.chip < 0x60)
329 info->max_p_usable = 0x6;
330 info->bias_p = nvbios_rd08(bios, data + 30);
331
332 if (len > 0x22)
333 info->refclk = nvbios_rd32(bios, data + 31);
334 break;
335 case 0x30:
336 data = nvbios_rd16(bios, data + 1);
337
338 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
339 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
340 info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000;
341 info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000;
342 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000;
343 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000;
344 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
345 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
346 info->vco1.min_n = nvbios_rd08(bios, data + 16);
347 info->vco1.max_n = nvbios_rd08(bios, data + 17);
348 info->vco1.min_m = nvbios_rd08(bios, data + 18);
349 info->vco1.max_m = nvbios_rd08(bios, data + 19);
350 info->vco2.min_n = nvbios_rd08(bios, data + 20);
351 info->vco2.max_n = nvbios_rd08(bios, data + 21);
352 info->vco2.min_m = nvbios_rd08(bios, data + 22);
353 info->vco2.max_m = nvbios_rd08(bios, data + 23);
354 info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25);
355 info->bias_p = nvbios_rd08(bios, data + 27);
356 info->refclk = nvbios_rd32(bios, data + 28);
357 break;
358 case 0x40:
359 info->refclk = nvbios_rd16(bios, data + 9) * 1000;
360 data = nvbios_rd16(bios, data + 1);
361
362 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
363 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
364 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000;
365 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000;
366 info->vco1.min_m = nvbios_rd08(bios, data + 8);
367 info->vco1.max_m = nvbios_rd08(bios, data + 9);
368 info->vco1.min_n = nvbios_rd08(bios, data + 10);
369 info->vco1.max_n = nvbios_rd08(bios, data + 11);
370 info->min_p = nvbios_rd08(bios, data + 12);
371 info->max_p = nvbios_rd08(bios, data + 13);
372 break;
373 case 0x50:
374 info->refclk = nvbios_rd16(bios, data + 1) * 1000;
375 /* info->refclk_alt = nvbios_rd16(bios, data + 3) * 1000; */
376 info->vco1.min_freq = nvbios_rd16(bios, data + 5) * 1000;
377 info->vco1.max_freq = nvbios_rd16(bios, data + 7) * 1000;
378 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 9) * 1000;
379 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 11) * 1000;
380 info->vco1.min_m = nvbios_rd08(bios, data + 13);
381 info->vco1.max_m = nvbios_rd08(bios, data + 14);
382 info->vco1.min_n = nvbios_rd08(bios, data + 15);
383 info->vco1.max_n = nvbios_rd08(bios, data + 16);
384 info->min_p = nvbios_rd08(bios, data + 17);
385 info->max_p = nvbios_rd08(bios, data + 18);
386 break;
387 default:
388 nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver);
389 return -EINVAL;
390 }
391
392 if (!info->refclk) {
393 info->refclk = device->crystal;
394 if (bios->version.chip == 0x51) {
395 u32 sel_clk = nvkm_rd32(device, 0x680524);
396 if ((info->reg == 0x680508 && sel_clk & 0x20) ||
397 (info->reg == 0x680520 && sel_clk & 0x80)) {
398 if (nvkm_rdvgac(device, 0, 0x27) < 0xa3)
399 info->refclk = 200000;
400 else
401 info->refclk = 25000;
402 }
403 }
404 }
405
406 /*
407 * By now any valid limit table ought to have set a max frequency for
408 * vco1, so if it's zero it's either a pre limit table bios, or one
409 * with an empty limit table (seen on nv18)
410 */
411 if (!info->vco1.max_freq) {
412 info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67);
413 info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71);
414 if (bmp_version(bios) < 0x0506) {
415 info->vco1.max_freq = 256000;
416 info->vco1.min_freq = 128000;
417 }
418
419 info->vco1.min_inputfreq = 0;
420 info->vco1.max_inputfreq = INT_MAX;
421 info->vco1.min_n = 0x1;
422 info->vco1.max_n = 0xff;
423 info->vco1.min_m = 0x1;
424
425 if (device->crystal == 13500) {
426 /* nv05 does this, nv11 doesn't, nv10 unknown */
427 if (bios->version.chip < 0x11)
428 info->vco1.min_m = 0x7;
429 info->vco1.max_m = 0xd;
430 } else {
431 if (bios->version.chip < 0x11)
432 info->vco1.min_m = 0x8;
433 info->vco1.max_m = 0xe;
434 }
435
436 if (bios->version.chip < 0x17 ||
437 bios->version.chip == 0x1a ||
438 bios->version.chip == 0x20)
439 info->max_p = 4;
440 else
441 info->max_p = 5;
442 info->max_p_usable = info->max_p;
443 }
444
445 return 0;
446 }
447