1 /* $NetBSD: nouveau_nvkm_engine_gr_gp10b.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gp10b.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
27
28 #include "gf100.h"
29 #include "ctxgf100.h"
30
31 #include <subdev/acr.h>
32
33 #include <nvif/class.h>
34
35 #include <nvfw/flcn.h>
36
37 static const struct nvkm_acr_lsf_func
38 gp10b_gr_gpccs_acr = {
39 .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
40 .bld_size = sizeof(struct flcn_bl_dmem_desc),
41 .bld_write = gm20b_gr_acr_bld_write,
42 .bld_patch = gm20b_gr_acr_bld_patch,
43 };
44
45 static const struct gf100_gr_func
46 gp10b_gr = {
47 .oneinit_tiles = gm200_gr_oneinit_tiles,
48 .oneinit_sm_id = gm200_gr_oneinit_sm_id,
49 .init = gf100_gr_init,
50 .init_gpc_mmu = gm200_gr_init_gpc_mmu,
51 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
52 .init_zcull = gf117_gr_init_zcull,
53 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
54 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
55 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
56 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
57 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
58 .init_419cc0 = gf100_gr_init_419cc0,
59 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
60 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
61 .init_504430 = gm107_gr_init_504430,
62 .init_shader_exceptions = gp100_gr_init_shader_exceptions,
63 .trap_mp = gf100_gr_trap_mp,
64 .rops = gm200_gr_rops,
65 .gpc_nr = 1,
66 .tpc_nr = 2,
67 .ppc_nr = 1,
68 .grctx = &gp100_grctx,
69 .zbc = &gp100_gr_zbc,
70 .sclass = {
71 { -1, -1, FERMI_TWOD_A },
72 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
73 { -1, -1, PASCAL_A, &gf100_fermi },
74 { -1, -1, PASCAL_COMPUTE_A },
75 {}
76 }
77 };
78
79 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
80 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin");
81 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin");
82 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin");
83 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin");
84 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin");
85 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin");
86 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin");
87 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin");
88 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin");
89 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin");
90 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin");
91 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin");
92 #endif
93
94 static const struct gf100_gr_fwif
95 gp10b_gr_fwif[] = {
96 { 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr },
97 {}
98 };
99
100 int
gp10b_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)101 gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
102 {
103 return gf100_gr_new_(gp10b_gr_fwif, device, index, pgr);
104 }
105