1 /* $NetBSD: nouveau_nvkm_engine_disp_coregv100.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_coregv100.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $");
26
27 #include "channv50.h"
28
29 #include <subdev/timer.h>
30
31 const struct nv50_disp_mthd_list
32 gv100_disp_core_mthd_base = {
33 .mthd = 0x0000,
34 .addr = 0x000000,
35 .data = {
36 { 0x0200, 0x680200 },
37 { 0x0208, 0x680208 },
38 { 0x020c, 0x68020c },
39 { 0x0210, 0x680210 },
40 { 0x0214, 0x680214 },
41 { 0x0218, 0x680218 },
42 { 0x021c, 0x68021c },
43 {}
44 }
45 };
46
47 const struct nv50_disp_mthd_list
48 gv100_disp_core_mthd_sor = {
49 .mthd = 0x0020,
50 .addr = 0x000020,
51 .data = {
52 { 0x0300, 0x680300 },
53 { 0x0304, 0x680304 },
54 { 0x0308, 0x680308 },
55 { 0x030c, 0x68030c },
56 {}
57 }
58 };
59
60 static const struct nv50_disp_mthd_list
61 gv100_disp_core_mthd_wndw = {
62 .mthd = 0x0080,
63 .addr = 0x000080,
64 .data = {
65 { 0x1000, 0x681000 },
66 { 0x1004, 0x681004 },
67 { 0x1008, 0x681008 },
68 { 0x100c, 0x68100c },
69 { 0x1010, 0x681010 },
70 {}
71 }
72 };
73
74 static const struct nv50_disp_mthd_list
75 gv100_disp_core_mthd_head = {
76 .mthd = 0x0400,
77 .addr = 0x000400,
78 .data = {
79 { 0x2000, 0x682000 },
80 { 0x2004, 0x682004 },
81 { 0x2008, 0x682008 },
82 { 0x200c, 0x68200c },
83 { 0x2014, 0x682014 },
84 { 0x2018, 0x682018 },
85 { 0x201c, 0x68201c },
86 { 0x2020, 0x682020 },
87 { 0x2028, 0x682028 },
88 { 0x202c, 0x68202c },
89 { 0x2030, 0x682030 },
90 { 0x2038, 0x682038 },
91 { 0x203c, 0x68203c },
92 { 0x2048, 0x682048 },
93 { 0x204c, 0x68204c },
94 { 0x2050, 0x682050 },
95 { 0x2054, 0x682054 },
96 { 0x2058, 0x682058 },
97 { 0x205c, 0x68205c },
98 { 0x2060, 0x682060 },
99 { 0x2064, 0x682064 },
100 { 0x2068, 0x682068 },
101 { 0x206c, 0x68206c },
102 { 0x2070, 0x682070 },
103 { 0x2074, 0x682074 },
104 { 0x2078, 0x682078 },
105 { 0x207c, 0x68207c },
106 { 0x2080, 0x682080 },
107 { 0x2088, 0x682088 },
108 { 0x2090, 0x682090 },
109 { 0x209c, 0x68209c },
110 { 0x20a0, 0x6820a0 },
111 { 0x20a4, 0x6820a4 },
112 { 0x20a8, 0x6820a8 },
113 { 0x20ac, 0x6820ac },
114 { 0x218c, 0x68218c },
115 { 0x2194, 0x682194 },
116 { 0x2198, 0x682198 },
117 { 0x219c, 0x68219c },
118 { 0x21a0, 0x6821a0 },
119 { 0x21a4, 0x6821a4 },
120 { 0x2214, 0x682214 },
121 { 0x2218, 0x682218 },
122 {}
123 }
124 };
125
126 static const struct nv50_disp_chan_mthd
127 gv100_disp_core_mthd = {
128 .name = "Core",
129 .addr = 0x000000,
130 .prev = 0x008000,
131 .data = {
132 { "Global", 1, &gv100_disp_core_mthd_base },
133 { "SOR", 4, &gv100_disp_core_mthd_sor },
134 { "WINDOW", 8, &gv100_disp_core_mthd_wndw },
135 { "HEAD", 4, &gv100_disp_core_mthd_head },
136 {}
137 }
138 };
139
140 static int
gv100_disp_core_idle(struct nv50_disp_chan * chan)141 gv100_disp_core_idle(struct nv50_disp_chan *chan)
142 {
143 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
144 nvkm_msec(device, 2000,
145 u32 stat = nvkm_rd32(device, 0x610630);
146 if ((stat & 0x001f0000) == 0x000b0000)
147 return 0;
148 );
149 return -EBUSY;
150 }
151
152 static u64
gv100_disp_core_user(struct nv50_disp_chan * chan,u64 * psize)153 gv100_disp_core_user(struct nv50_disp_chan *chan, u64 *psize)
154 {
155 *psize = 0x10000;
156 return 0x680000;
157 }
158
159 static void
gv100_disp_core_intr(struct nv50_disp_chan * chan,bool en)160 gv100_disp_core_intr(struct nv50_disp_chan *chan, bool en)
161 {
162 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
163 const u32 mask = 0x00000001;
164 const u32 data = en ? mask : 0;
165 nvkm_mask(device, 0x611dac, mask, data);
166 }
167
168 static void
gv100_disp_core_fini(struct nv50_disp_chan * chan)169 gv100_disp_core_fini(struct nv50_disp_chan *chan)
170 {
171 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
172 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000);
173 gv100_disp_core_idle(chan);
174 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000);
175 }
176
177 static int
gv100_disp_core_init(struct nv50_disp_chan * chan)178 gv100_disp_core_init(struct nv50_disp_chan *chan)
179 {
180 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
181 struct nvkm_device *device = subdev->device;
182
183 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push));
184 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push));
185 nvkm_wr32(device, 0x610b28, 0x00000001);
186 nvkm_wr32(device, 0x610b2c, 0x00000040);
187
188 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010);
189 nvkm_wr32(device, 0x680000, 0x00000000);
190 nvkm_wr32(device, 0x6104e0, 0x00000013);
191 return gv100_disp_core_idle(chan);
192 }
193
194 static const struct nv50_disp_chan_func
195 gv100_disp_core = {
196 .init = gv100_disp_core_init,
197 .fini = gv100_disp_core_fini,
198 .intr = gv100_disp_core_intr,
199 .user = gv100_disp_core_user,
200 .bind = gv100_disp_dmac_bind,
201 };
202
203 int
gv100_disp_core_new(const struct nvkm_oclass * oclass,void * argv,u32 argc,struct nv50_disp * disp,struct nvkm_object ** pobject)204 gv100_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
205 struct nv50_disp *disp, struct nvkm_object **pobject)
206 {
207 return nv50_disp_core_new_(&gv100_disp_core, &gv100_disp_core_mthd,
208 disp, 0, oclass, argv, argc, pobject);
209 }
210