xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/nouveau_nvkm_engine_disp_coregp102.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: nouveau_nvkm_engine_disp_coregp102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2016 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Ben Skeggs <bskeggs@redhat.com>
25  */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_coregp102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $");
28 
29 #include "channv50.h"
30 
31 #include <subdev/timer.h>
32 
33 static int
gp102_disp_core_init(struct nv50_disp_chan * chan)34 gp102_disp_core_init(struct nv50_disp_chan *chan)
35 {
36 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
37 	struct nvkm_device *device = subdev->device;
38 
39 	/* initialise channel for dma command submission */
40 	nvkm_wr32(device, 0x611494, chan->push);
41 	nvkm_wr32(device, 0x611498, 0x00010000);
42 	nvkm_wr32(device, 0x61149c, 0x00000001);
43 	nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
44 	nvkm_wr32(device, 0x640000, 0x00000000);
45 	nvkm_wr32(device, 0x610490, 0x01000013);
46 
47 	/* wait for it to go inactive */
48 	if (nvkm_msec(device, 2000,
49 		if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
50 			break;
51 	) < 0) {
52 		nvkm_error(subdev, "core init: %08x\n",
53 			   nvkm_rd32(device, 0x610490));
54 		return -EBUSY;
55 	}
56 
57 	return 0;
58 }
59 
60 static const struct nv50_disp_chan_func
61 gp102_disp_core_func = {
62 	.init = gp102_disp_core_init,
63 	.fini = gf119_disp_core_fini,
64 	.intr = gf119_disp_chan_intr,
65 	.user = nv50_disp_chan_user,
66 	.bind = gf119_disp_dmac_bind,
67 };
68 
69 int
gp102_disp_core_new(const struct nvkm_oclass * oclass,void * argv,u32 argc,struct nv50_disp * disp,struct nvkm_object ** pobject)70 gp102_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
71 		    struct nv50_disp *disp, struct nvkm_object **pobject)
72 {
73 	return nv50_disp_core_new_(&gp102_disp_core_func, &gk104_disp_core_mthd,
74 				   disp, 0, oclass, argv, argc, pobject);
75 }
76