1 /* $NetBSD: nbio_6_1_smn.h,v 1.2 2021/12/18 23:45:19 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _nbio_6_1_SMN_HEADER 25 #define _nbio_6_1_SMN_HEADER 26 27 28 #define smnCPM_CONTROL 0x11180460 29 #define smnPCIE_CNTL2 0x11180070 30 #define smnPCIE_CONFIG_CNTL 0x11180044 31 #define smnPCIE_CI_CNTL 0x11180080 32 33 34 #define smnPCIE_PERF_COUNT_CNTL 0x11180200 35 #define smnPCIE_PERF_CNTL_TXCLK 0x11180204 36 #define smnPCIE_PERF_COUNT0_TXCLK 0x11180208 37 #define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c 38 #define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210 39 #define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214 40 #define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218 41 #define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c 42 #define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220 43 #define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224 44 #define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228 45 #define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c 46 #define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230 47 #define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234 48 #define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238 49 #define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c 50 #define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240 51 #define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244 52 #define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248 53 #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c 54 #define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250 55 #define smnPCIE_PERF_CNTL_TXCLK2 0x11180254 56 #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258 57 #define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c 58 59 #define smnPCIE_RX_NUM_NAK 0x11180038 60 #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c 61 62 #endif // _nbio_6_1_SMN_HEADER 63 64