1 /* $NetBSD: mt8192-resets.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2020 MediaTek Inc. 6 * Author: Yong Liang <yong.liang@mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 10 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 11 12 #define MT8192_TOPRGU_MM_SW_RST 1 13 #define MT8192_TOPRGU_MFG_SW_RST 2 14 #define MT8192_TOPRGU_VENC_SW_RST 3 15 #define MT8192_TOPRGU_VDEC_SW_RST 4 16 #define MT8192_TOPRGU_IMG_SW_RST 5 17 #define MT8192_TOPRGU_MD_SW_RST 7 18 #define MT8192_TOPRGU_CONN_SW_RST 9 19 #define MT8192_TOPRGU_CONN_MCU_SW_RST 12 20 #define MT8192_TOPRGU_IPU0_SW_RST 14 21 #define MT8192_TOPRGU_IPU1_SW_RST 15 22 #define MT8192_TOPRGU_AUDIO_SW_RST 17 23 #define MT8192_TOPRGU_CAMSYS_SW_RST 18 24 #define MT8192_TOPRGU_MJC_SW_RST 19 25 #define MT8192_TOPRGU_C2K_S2_SW_RST 20 26 #define MT8192_TOPRGU_C2K_SW_RST 21 27 #define MT8192_TOPRGU_PERI_SW_RST 22 28 #define MT8192_TOPRGU_PERI_AO_SW_RST 23 29 30 #define MT8192_TOPRGU_SW_RST_NUM 23 31 32 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ 33