1 /* $NetBSD: mp_9_0_sh_mask.h,v 1.2 2021/12/18 23:45:17 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _mp_9_0_SH_MASK_HEADER 24 #define _mp_9_0_SH_MASK_HEADER 25 26 27 // addressBlock: mp_SmuMp0_SmnDec 28 //MP0_SMN_C2PMSG_32 29 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 30 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 31 //MP0_SMN_C2PMSG_33 32 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 33 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 34 //MP0_SMN_C2PMSG_34 35 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 36 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 37 //MP0_SMN_C2PMSG_35 38 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 39 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 40 //MP0_SMN_C2PMSG_36 41 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 42 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 43 //MP0_SMN_C2PMSG_37 44 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 45 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 46 //MP0_SMN_C2PMSG_38 47 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 48 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 49 //MP0_SMN_C2PMSG_39 50 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 51 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 52 //MP0_SMN_C2PMSG_40 53 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 54 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 55 //MP0_SMN_C2PMSG_41 56 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 57 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 58 //MP0_SMN_C2PMSG_42 59 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 60 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 61 //MP0_SMN_C2PMSG_43 62 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 63 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 64 //MP0_SMN_C2PMSG_44 65 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 66 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 67 //MP0_SMN_C2PMSG_45 68 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 69 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 70 //MP0_SMN_C2PMSG_46 71 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 72 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 73 //MP0_SMN_C2PMSG_47 74 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 75 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 76 //MP0_SMN_C2PMSG_48 77 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 78 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 79 //MP0_SMN_C2PMSG_49 80 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 81 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 82 //MP0_SMN_C2PMSG_50 83 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 84 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 85 //MP0_SMN_C2PMSG_51 86 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 87 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 88 //MP0_SMN_C2PMSG_52 89 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 90 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 91 //MP0_SMN_C2PMSG_53 92 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 93 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 94 //MP0_SMN_C2PMSG_54 95 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 96 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 97 //MP0_SMN_C2PMSG_55 98 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 99 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 100 //MP0_SMN_C2PMSG_56 101 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 102 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 103 //MP0_SMN_C2PMSG_57 104 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 105 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 106 //MP0_SMN_C2PMSG_58 107 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 108 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 109 //MP0_SMN_C2PMSG_59 110 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 111 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 112 //MP0_SMN_C2PMSG_60 113 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 114 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 115 //MP0_SMN_C2PMSG_61 116 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 117 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 118 //MP0_SMN_C2PMSG_62 119 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 120 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 121 //MP0_SMN_C2PMSG_63 122 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 123 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 124 //MP0_SMN_C2PMSG_64 125 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 126 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 127 //MP0_SMN_C2PMSG_65 128 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 129 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 130 //MP0_SMN_C2PMSG_66 131 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 132 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 133 //MP0_SMN_C2PMSG_67 134 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 135 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 136 //MP0_SMN_C2PMSG_68 137 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 138 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 139 //MP0_SMN_C2PMSG_69 140 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 141 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 142 //MP0_SMN_C2PMSG_70 143 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 144 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 145 //MP0_SMN_C2PMSG_71 146 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 147 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 148 //MP0_SMN_C2PMSG_72 149 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 150 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 151 //MP0_SMN_C2PMSG_73 152 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 153 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 154 //MP0_SMN_C2PMSG_74 155 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 156 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 157 //MP0_SMN_C2PMSG_75 158 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 159 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 160 //MP0_SMN_C2PMSG_76 161 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 162 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 163 //MP0_SMN_C2PMSG_77 164 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 165 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 166 //MP0_SMN_C2PMSG_78 167 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 168 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 169 //MP0_SMN_C2PMSG_79 170 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 171 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 172 //MP0_SMN_C2PMSG_80 173 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 174 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 175 //MP0_SMN_C2PMSG_81 176 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 177 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 178 //MP0_SMN_C2PMSG_82 179 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 180 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 181 //MP0_SMN_C2PMSG_83 182 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 183 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 184 //MP0_SMN_C2PMSG_84 185 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 186 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 187 //MP0_SMN_C2PMSG_85 188 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 189 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 190 //MP0_SMN_C2PMSG_86 191 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 192 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 193 //MP0_SMN_C2PMSG_87 194 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 195 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 196 //MP0_SMN_C2PMSG_88 197 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 198 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 199 //MP0_SMN_C2PMSG_89 200 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 201 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 202 //MP0_SMN_C2PMSG_90 203 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 204 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 205 //MP0_SMN_C2PMSG_91 206 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 207 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 208 //MP0_SMN_C2PMSG_92 209 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 210 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 211 //MP0_SMN_C2PMSG_93 212 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 213 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 214 //MP0_SMN_C2PMSG_94 215 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 216 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 217 //MP0_SMN_C2PMSG_95 218 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 219 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 220 //MP0_SMN_C2PMSG_96 221 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 222 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 223 //MP0_SMN_C2PMSG_97 224 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 225 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 226 //MP0_SMN_C2PMSG_98 227 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 228 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 229 //MP0_SMN_C2PMSG_99 230 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 231 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 232 //MP0_SMN_C2PMSG_100 233 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 234 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 235 //MP0_SMN_C2PMSG_101 236 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 237 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 238 //MP0_SMN_C2PMSG_102 239 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 240 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 241 //MP0_SMN_C2PMSG_103 242 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 243 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 244 //MP0_SMN_ACTIVE_FCN_ID 245 #define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 246 #define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f 247 #define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 248 #define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L 249 //MP0_SMN_IH_CREDIT 250 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 251 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 252 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 253 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 254 //MP0_SMN_IH_SW_INT 255 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 256 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 257 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L 258 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL 259 //MP0_SMN_IH_SW_INT_CTRL 260 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 261 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 262 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L 263 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L 264 265 266 // addressBlock: mp_SmuMp1_SmnDec 267 //MP1_SMN_ACP2MP_RESP 268 #define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 269 #define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 270 //MP1_SMN_DC2MP_RESP 271 #define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 272 #define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 273 //MP1_SMN_UVD2MP_RESP 274 #define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 275 #define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 276 //MP1_SMN_VCE2MP_RESP 277 #define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 278 #define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 279 //MP1_SMN_RLC2MP_RESP 280 #define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 281 #define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 282 //MP1_SMN_C2PMSG_32 283 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 284 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 285 //MP1_SMN_C2PMSG_33 286 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 287 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 288 //MP1_SMN_C2PMSG_34 289 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 290 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 291 //MP1_SMN_C2PMSG_35 292 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 293 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 294 //MP1_SMN_C2PMSG_36 295 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 296 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 297 //MP1_SMN_C2PMSG_37 298 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 299 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 300 //MP1_SMN_C2PMSG_38 301 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 302 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 303 //MP1_SMN_C2PMSG_39 304 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 305 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 306 //MP1_SMN_C2PMSG_40 307 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 308 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 309 //MP1_SMN_C2PMSG_41 310 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 311 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 312 //MP1_SMN_C2PMSG_42 313 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 314 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 315 //MP1_SMN_C2PMSG_43 316 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 317 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 318 //MP1_SMN_C2PMSG_44 319 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 320 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 321 //MP1_SMN_C2PMSG_45 322 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 323 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 324 //MP1_SMN_C2PMSG_46 325 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 326 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 327 //MP1_SMN_C2PMSG_47 328 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 329 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 330 //MP1_SMN_C2PMSG_48 331 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 332 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 333 //MP1_SMN_C2PMSG_49 334 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 335 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 336 //MP1_SMN_C2PMSG_50 337 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 338 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 339 //MP1_SMN_C2PMSG_51 340 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 341 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 342 //MP1_SMN_C2PMSG_52 343 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 344 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 345 //MP1_SMN_C2PMSG_53 346 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 347 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 348 //MP1_SMN_C2PMSG_54 349 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 350 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 351 //MP1_SMN_C2PMSG_55 352 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 353 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 354 //MP1_SMN_C2PMSG_56 355 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 356 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 357 //MP1_SMN_C2PMSG_57 358 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 359 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 360 //MP1_SMN_C2PMSG_58 361 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 362 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 363 //MP1_SMN_C2PMSG_59 364 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 365 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 366 //MP1_SMN_C2PMSG_60 367 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 368 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 369 //MP1_SMN_C2PMSG_61 370 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 371 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 372 //MP1_SMN_C2PMSG_62 373 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 374 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 375 //MP1_SMN_C2PMSG_63 376 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 377 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 378 //MP1_SMN_C2PMSG_64 379 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 380 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 381 //MP1_SMN_C2PMSG_65 382 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 383 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 384 //MP1_SMN_C2PMSG_66 385 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 386 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 387 //MP1_SMN_C2PMSG_67 388 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 389 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 390 //MP1_SMN_C2PMSG_68 391 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 392 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 393 //MP1_SMN_C2PMSG_69 394 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 395 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 396 //MP1_SMN_C2PMSG_70 397 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 398 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 399 //MP1_SMN_C2PMSG_71 400 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 401 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 402 //MP1_SMN_C2PMSG_72 403 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 404 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 405 //MP1_SMN_C2PMSG_73 406 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 407 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 408 //MP1_SMN_C2PMSG_74 409 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 410 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 411 //MP1_SMN_C2PMSG_75 412 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 413 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 414 //MP1_SMN_C2PMSG_76 415 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 416 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 417 //MP1_SMN_C2PMSG_77 418 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 419 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 420 //MP1_SMN_C2PMSG_78 421 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 422 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 423 //MP1_SMN_C2PMSG_79 424 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 425 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 426 //MP1_SMN_C2PMSG_80 427 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 428 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 429 //MP1_SMN_C2PMSG_81 430 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 431 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 432 //MP1_SMN_C2PMSG_82 433 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 434 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 435 //MP1_SMN_C2PMSG_83 436 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 437 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 438 //MP1_SMN_C2PMSG_84 439 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 440 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 441 //MP1_SMN_C2PMSG_85 442 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 443 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 444 //MP1_SMN_C2PMSG_86 445 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 446 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 447 //MP1_SMN_C2PMSG_87 448 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 449 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 450 //MP1_SMN_C2PMSG_88 451 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 452 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 453 //MP1_SMN_C2PMSG_89 454 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 455 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 456 //MP1_SMN_C2PMSG_90 457 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 458 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 459 //MP1_SMN_C2PMSG_91 460 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 461 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 462 //MP1_SMN_C2PMSG_92 463 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 464 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 465 //MP1_SMN_C2PMSG_93 466 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 467 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 468 //MP1_SMN_C2PMSG_94 469 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 470 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 471 //MP1_SMN_C2PMSG_95 472 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 473 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 474 //MP1_SMN_C2PMSG_96 475 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 476 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 477 //MP1_SMN_C2PMSG_97 478 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 479 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 480 //MP1_SMN_C2PMSG_98 481 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 482 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 483 //MP1_SMN_C2PMSG_99 484 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 485 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 486 //MP1_SMN_C2PMSG_100 487 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 488 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 489 //MP1_SMN_C2PMSG_101 490 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 491 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 492 //MP1_SMN_C2PMSG_102 493 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 494 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 495 //MP1_SMN_C2PMSG_103 496 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 497 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 498 //MP1_SMN_ACTIVE_FCN_ID 499 #define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 500 #define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f 501 #define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 502 #define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L 503 //MP1_SMN_IH_CREDIT 504 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 505 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 506 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 507 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 508 //MP1_SMN_IH_SW_INT 509 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 510 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 511 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L 512 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL 513 //MP1_SMN_IH_SW_INT_CTRL 514 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 515 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 516 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L 517 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L 518 //MP1_SMN_FPS_CNT 519 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 520 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 521 //MP1_SMN_EXT_SCRATCH0 522 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 523 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 524 //MP1_SMN_EXT_SCRATCH1 525 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 526 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 527 //MP1_SMN_EXT_SCRATCH2 528 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 529 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 530 //MP1_SMN_EXT_SCRATCH3 531 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 532 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 533 //MP1_SMN_EXT_SCRATCH4 534 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 535 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 536 //MP1_SMN_EXT_SCRATCH5 537 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 538 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 539 //MP1_SMN_EXT_SCRATCH6 540 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 541 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 542 //MP1_SMN_EXT_SCRATCH7 543 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 544 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 545 //MP1_SMN_EXT_SCRATCH8 546 #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 547 #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 548 549 550 551 552 // addressBlock: mp_SmuMp0Pub_CruDec 553 //MP0_SOC_INFO 554 #define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 555 #define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 556 #define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L 557 #define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL 558 //MP0_PUB_SCRATCH0 559 #define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 560 #define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL 561 //MP0_PUB_SCRATCH1 562 #define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 563 #define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL 564 //MP0_PUB_SCRATCH2 565 #define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 566 #define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL 567 //MP0_PUB_SCRATCH3 568 #define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 569 #define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL 570 //MP0_FW_INTF 571 #define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 572 #define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L 573 //MP0_C2PMSG_0 574 #define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 575 #define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 576 //MP0_C2PMSG_1 577 #define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 578 #define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 579 //MP0_C2PMSG_2 580 #define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 581 #define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 582 //MP0_C2PMSG_3 583 #define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 584 #define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 585 //MP0_C2PMSG_4 586 #define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 587 #define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 588 //MP0_C2PMSG_5 589 #define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 590 #define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 591 //MP0_C2PMSG_6 592 #define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 593 #define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 594 //MP0_C2PMSG_7 595 #define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 596 #define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 597 //MP0_C2PMSG_8 598 #define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 599 #define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 600 //MP0_C2PMSG_9 601 #define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 602 #define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 603 //MP0_C2PMSG_10 604 #define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 605 #define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 606 //MP0_C2PMSG_11 607 #define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 608 #define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 609 //MP0_C2PMSG_12 610 #define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 611 #define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 612 //MP0_C2PMSG_13 613 #define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 614 #define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 615 //MP0_C2PMSG_14 616 #define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 617 #define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 618 //MP0_C2PMSG_15 619 #define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 620 #define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 621 //MP0_C2PMSG_16 622 #define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 623 #define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 624 //MP0_C2PMSG_17 625 #define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 626 #define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 627 //MP0_C2PMSG_18 628 #define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 629 #define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 630 //MP0_C2PMSG_19 631 #define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 632 #define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 633 //MP0_C2PMSG_20 634 #define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 635 #define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 636 //MP0_C2PMSG_21 637 #define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 638 #define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 639 //MP0_C2PMSG_22 640 #define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 641 #define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 642 //MP0_C2PMSG_23 643 #define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 644 #define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 645 //MP0_C2PMSG_24 646 #define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 647 #define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 648 //MP0_C2PMSG_25 649 #define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 650 #define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 651 //MP0_C2PMSG_26 652 #define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 653 #define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 654 //MP0_C2PMSG_27 655 #define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 656 #define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 657 //MP0_C2PMSG_28 658 #define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 659 #define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 660 //MP0_C2PMSG_29 661 #define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 662 #define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 663 //MP0_C2PMSG_30 664 #define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 665 #define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 666 //MP0_C2PMSG_31 667 #define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 668 #define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 669 //MP0_P2CMSG_0 670 #define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 671 #define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL 672 //MP0_P2CMSG_1 673 #define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 674 #define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL 675 //MP0_P2CMSG_2 676 #define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 677 #define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL 678 //MP0_P2CMSG_3 679 #define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 680 #define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL 681 //MP0_P2CMSG_INTEN 682 #define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 683 #define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL 684 //MP0_P2CMSG_INTSTS 685 #define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 686 #define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 687 #define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 688 #define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 689 #define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L 690 #define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L 691 #define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L 692 #define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L 693 //MP0_C2PMSG_ATTR_0 694 #define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 695 #define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL 696 //MP0_C2PMSG_ATTR_1 697 #define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 698 #define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL 699 //MP0_C2PMSG_ATTR_2 700 #define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 701 #define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL 702 //MP0_C2PMSG_ATTR_3 703 #define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 704 #define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL 705 //MP0_C2PMSG_ATTR_4 706 #define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 707 #define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL 708 //MP0_C2PMSG_ATTR_5 709 #define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 710 #define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL 711 //MP0_C2PMSG_ATTR_6 712 #define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 713 #define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL 714 //MP0_P2CMSG_ATTR 715 #define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 716 #define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL 717 //MP0_P2SMSG_0 718 #define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 719 #define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL 720 //MP0_P2SMSG_1 721 #define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 722 #define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL 723 //MP0_P2SMSG_2 724 #define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 725 #define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL 726 //MP0_P2SMSG_3 727 #define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 728 #define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL 729 //MP0_P2SMSG_ATTR 730 #define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 731 #define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL 732 //MP0_S2PMSG_ATTR 733 #define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 734 #define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L 735 //MP0_P2SMSG_INTSTS 736 #define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 737 #define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 738 #define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 739 #define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 740 #define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L 741 #define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L 742 #define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L 743 #define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L 744 //MP0_S2PMSG_0 745 #define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 746 #define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 747 //MP0_C2PMSG_32 748 #define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 749 #define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 750 //MP0_C2PMSG_33 751 #define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 752 #define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 753 //MP0_C2PMSG_34 754 #define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 755 #define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 756 //MP0_C2PMSG_35 757 #define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 758 #define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 759 //MP0_C2PMSG_36 760 #define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 761 #define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 762 //MP0_C2PMSG_37 763 #define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 764 #define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 765 //MP0_C2PMSG_38 766 #define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 767 #define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 768 //MP0_C2PMSG_39 769 #define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 770 #define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 771 //MP0_C2PMSG_40 772 #define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 773 #define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 774 //MP0_C2PMSG_41 775 #define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 776 #define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 777 //MP0_C2PMSG_42 778 #define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 779 #define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 780 //MP0_C2PMSG_43 781 #define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 782 #define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 783 //MP0_C2PMSG_44 784 #define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 785 #define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 786 //MP0_C2PMSG_45 787 #define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 788 #define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 789 //MP0_C2PMSG_46 790 #define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 791 #define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 792 //MP0_C2PMSG_47 793 #define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 794 #define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 795 //MP0_C2PMSG_48 796 #define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 797 #define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 798 //MP0_C2PMSG_49 799 #define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 800 #define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 801 //MP0_C2PMSG_50 802 #define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 803 #define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 804 //MP0_C2PMSG_51 805 #define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 806 #define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 807 //MP0_C2PMSG_52 808 #define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 809 #define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 810 //MP0_C2PMSG_53 811 #define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 812 #define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 813 //MP0_C2PMSG_54 814 #define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 815 #define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 816 //MP0_C2PMSG_55 817 #define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 818 #define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 819 //MP0_C2PMSG_56 820 #define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 821 #define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 822 //MP0_C2PMSG_57 823 #define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 824 #define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 825 //MP0_C2PMSG_58 826 #define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 827 #define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 828 //MP0_C2PMSG_59 829 #define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 830 #define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 831 //MP0_C2PMSG_60 832 #define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 833 #define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 834 //MP0_C2PMSG_61 835 #define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 836 #define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 837 //MP0_C2PMSG_62 838 #define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 839 #define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 840 //MP0_C2PMSG_63 841 #define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 842 #define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 843 //MP0_C2PMSG_64 844 #define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 845 #define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 846 //MP0_C2PMSG_65 847 #define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 848 #define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 849 //MP0_C2PMSG_66 850 #define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 851 #define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 852 //MP0_C2PMSG_67 853 #define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 854 #define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 855 //MP0_C2PMSG_68 856 #define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 857 #define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 858 //MP0_C2PMSG_69 859 #define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 860 #define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 861 //MP0_C2PMSG_70 862 #define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 863 #define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 864 //MP0_C2PMSG_71 865 #define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 866 #define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 867 //MP0_C2PMSG_72 868 #define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 869 #define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 870 //MP0_C2PMSG_73 871 #define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 872 #define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 873 //MP0_C2PMSG_74 874 #define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 875 #define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 876 //MP0_C2PMSG_75 877 #define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 878 #define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 879 //MP0_C2PMSG_76 880 #define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 881 #define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 882 //MP0_C2PMSG_77 883 #define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 884 #define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 885 //MP0_C2PMSG_78 886 #define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 887 #define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 888 //MP0_C2PMSG_79 889 #define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 890 #define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 891 //MP0_C2PMSG_80 892 #define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 893 #define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 894 //MP0_C2PMSG_81 895 #define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 896 #define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 897 //MP0_C2PMSG_82 898 #define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 899 #define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 900 //MP0_C2PMSG_83 901 #define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 902 #define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 903 //MP0_C2PMSG_84 904 #define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 905 #define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 906 //MP0_C2PMSG_85 907 #define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 908 #define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 909 //MP0_C2PMSG_86 910 #define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 911 #define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 912 //MP0_C2PMSG_87 913 #define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 914 #define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 915 //MP0_C2PMSG_88 916 #define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 917 #define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 918 //MP0_C2PMSG_89 919 #define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 920 #define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 921 //MP0_C2PMSG_90 922 #define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 923 #define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 924 //MP0_C2PMSG_91 925 #define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 926 #define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 927 //MP0_C2PMSG_92 928 #define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 929 #define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 930 //MP0_C2PMSG_93 931 #define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 932 #define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 933 //MP0_C2PMSG_94 934 #define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 935 #define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 936 //MP0_C2PMSG_95 937 #define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 938 #define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 939 //MP0_C2PMSG_96 940 #define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 941 #define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 942 //MP0_C2PMSG_97 943 #define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 944 #define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 945 //MP0_C2PMSG_98 946 #define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 947 #define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 948 //MP0_C2PMSG_99 949 #define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 950 #define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 951 //MP0_C2PMSG_100 952 #define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 953 #define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 954 //MP0_C2PMSG_101 955 #define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 956 #define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 957 //MP0_C2PMSG_102 958 #define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 959 #define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 960 //MP0_C2PMSG_103 961 #define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 962 #define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 963 //MP0_ACTIVE_FCN_ID 964 #define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 965 #define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 966 #define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 967 #define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 968 //MP0_IH_CREDIT 969 #define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 970 #define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 971 #define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 972 #define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 973 //MP0_IH_SW_INT 974 #define MP0_IH_SW_INT__ID__SHIFT 0x0 975 #define MP0_IH_SW_INT__VALID__SHIFT 0x8 976 #define MP0_IH_SW_INT__ID_MASK 0x000000FFL 977 #define MP0_IH_SW_INT__VALID_MASK 0x00000100L 978 //MP0_IH_SW_INT_CTRL 979 #define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 980 #define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 981 #define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 982 #define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 983 984 985 //CGTT_DRM_CLK_CTRL0 986 #define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 987 #define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 988 #define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc 989 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 990 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 991 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 992 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 993 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a 994 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b 995 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c 996 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 997 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 998 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 999 #define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 1000 #define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 1001 #define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L 1002 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L 1003 #define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L 1004 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L 1005 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L 1006 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L 1007 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L 1008 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L 1009 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L 1010 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 1011 #define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 1012 //DRM_LIGHT_SLEEP_CTRL 1013 #define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 1014 #define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L 1015 1016 1017 // addressBlock: mp_SmuMp1Pub_CruDec 1018 //MP1_SMN_PUB_CTRL 1019 #define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 1020 #define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L 1021 //MP1_FIRMWARE_FLAGS 1022 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 1023 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 1024 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 1025 #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 1026 //MP1_PUB_SCRATCH0 1027 #define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 1028 #define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL 1029 //MP1_PUB_SCRATCH1 1030 #define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 1031 #define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL 1032 //MP1_PUB_SCRATCH2 1033 #define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 1034 #define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL 1035 //MP1_PUB_SCRATCH3 1036 #define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 1037 #define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL 1038 //MP1_C2PMSG_0 1039 #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 1040 #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 1041 //MP1_C2PMSG_1 1042 #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 1043 #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 1044 //MP1_C2PMSG_2 1045 #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 1046 #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 1047 //MP1_C2PMSG_3 1048 #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 1049 #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 1050 //MP1_C2PMSG_4 1051 #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 1052 #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 1053 //MP1_C2PMSG_5 1054 #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 1055 #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 1056 //MP1_C2PMSG_6 1057 #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 1058 #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 1059 //MP1_C2PMSG_7 1060 #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 1061 #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 1062 //MP1_C2PMSG_8 1063 #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 1064 #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 1065 //MP1_C2PMSG_9 1066 #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 1067 #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 1068 //MP1_C2PMSG_10 1069 #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 1070 #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 1071 //MP1_C2PMSG_11 1072 #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 1073 #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 1074 //MP1_C2PMSG_12 1075 #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 1076 #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 1077 //MP1_C2PMSG_13 1078 #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 1079 #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 1080 //MP1_C2PMSG_14 1081 #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 1082 #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 1083 //MP1_C2PMSG_15 1084 #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 1085 #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 1086 //MP1_C2PMSG_16 1087 #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 1088 #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 1089 //MP1_C2PMSG_17 1090 #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 1091 #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 1092 //MP1_C2PMSG_18 1093 #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 1094 #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 1095 //MP1_C2PMSG_19 1096 #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 1097 #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 1098 //MP1_C2PMSG_20 1099 #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 1100 #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 1101 //MP1_C2PMSG_21 1102 #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 1103 #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 1104 //MP1_C2PMSG_22 1105 #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 1106 #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 1107 //MP1_C2PMSG_23 1108 #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 1109 #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 1110 //MP1_C2PMSG_24 1111 #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 1112 #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 1113 //MP1_C2PMSG_25 1114 #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 1115 #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 1116 //MP1_C2PMSG_26 1117 #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 1118 #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 1119 //MP1_C2PMSG_27 1120 #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 1121 #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 1122 //MP1_C2PMSG_28 1123 #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 1124 #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 1125 //MP1_C2PMSG_29 1126 #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 1127 #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 1128 //MP1_C2PMSG_30 1129 #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 1130 #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 1131 //MP1_C2PMSG_31 1132 #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 1133 #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 1134 //MP1_P2CMSG_0 1135 #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 1136 #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL 1137 //MP1_P2CMSG_1 1138 #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 1139 #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL 1140 //MP1_P2CMSG_2 1141 #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 1142 #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL 1143 //MP1_P2CMSG_3 1144 #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 1145 #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL 1146 //MP1_P2CMSG_INTEN 1147 #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 1148 #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL 1149 //MP1_P2CMSG_INTSTS 1150 #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 1151 #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 1152 #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 1153 #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 1154 #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L 1155 #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L 1156 #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L 1157 #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L 1158 //MP1_P2SMSG_0 1159 #define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 1160 #define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL 1161 //MP1_P2SMSG_1 1162 #define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 1163 #define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL 1164 //MP1_P2SMSG_2 1165 #define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 1166 #define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL 1167 //MP1_P2SMSG_3 1168 #define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 1169 #define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL 1170 //MP1_P2SMSG_INTSTS 1171 #define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 1172 #define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 1173 #define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 1174 #define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 1175 #define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L 1176 #define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L 1177 #define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L 1178 #define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L 1179 //MP1_S2PMSG_0 1180 #define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 1181 #define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 1182 //MP1_ACP2MP_RESP 1183 #define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 1184 #define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 1185 //MP1_DC2MP_RESP 1186 #define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 1187 #define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 1188 //MP1_UVD2MP_RESP 1189 #define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 1190 #define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 1191 //MP1_VCE2MP_RESP 1192 #define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 1193 #define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 1194 //MP1_RLC2MP_RESP 1195 #define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 1196 #define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL 1197 //MP1_C2PMSG_32 1198 #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 1199 #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 1200 //MP1_C2PMSG_33 1201 #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 1202 #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 1203 //MP1_C2PMSG_34 1204 #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 1205 #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 1206 //MP1_C2PMSG_35 1207 #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 1208 #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 1209 //MP1_C2PMSG_36 1210 #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 1211 #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 1212 //MP1_C2PMSG_37 1213 #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 1214 #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 1215 //MP1_C2PMSG_38 1216 #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 1217 #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 1218 //MP1_C2PMSG_39 1219 #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 1220 #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 1221 //MP1_C2PMSG_40 1222 #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 1223 #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 1224 //MP1_C2PMSG_41 1225 #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 1226 #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 1227 //MP1_C2PMSG_42 1228 #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 1229 #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 1230 //MP1_C2PMSG_43 1231 #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 1232 #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 1233 //MP1_C2PMSG_44 1234 #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 1235 #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 1236 //MP1_C2PMSG_45 1237 #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 1238 #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 1239 //MP1_C2PMSG_46 1240 #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 1241 #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 1242 //MP1_C2PMSG_47 1243 #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 1244 #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 1245 //MP1_C2PMSG_48 1246 #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 1247 #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 1248 //MP1_C2PMSG_49 1249 #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 1250 #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 1251 //MP1_C2PMSG_50 1252 #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 1253 #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 1254 //MP1_C2PMSG_51 1255 #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 1256 #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 1257 //MP1_C2PMSG_52 1258 #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 1259 #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 1260 //MP1_C2PMSG_53 1261 #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 1262 #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 1263 //MP1_C2PMSG_54 1264 #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 1265 #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 1266 //MP1_C2PMSG_55 1267 #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 1268 #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 1269 //MP1_C2PMSG_56 1270 #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 1271 #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 1272 //MP1_C2PMSG_57 1273 #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 1274 #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 1275 //MP1_C2PMSG_58 1276 #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 1277 #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 1278 //MP1_C2PMSG_59 1279 #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 1280 #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 1281 //MP1_C2PMSG_60 1282 #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 1283 #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 1284 //MP1_C2PMSG_61 1285 #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 1286 #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 1287 //MP1_C2PMSG_62 1288 #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 1289 #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 1290 //MP1_C2PMSG_63 1291 #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 1292 #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 1293 //MP1_C2PMSG_64 1294 #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 1295 #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 1296 //MP1_C2PMSG_65 1297 #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 1298 #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 1299 //MP1_C2PMSG_66 1300 #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 1301 #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 1302 //MP1_C2PMSG_67 1303 #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 1304 #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 1305 //MP1_C2PMSG_68 1306 #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 1307 #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 1308 //MP1_C2PMSG_69 1309 #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 1310 #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 1311 //MP1_C2PMSG_70 1312 #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 1313 #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 1314 //MP1_C2PMSG_71 1315 #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 1316 #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 1317 //MP1_C2PMSG_72 1318 #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 1319 #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 1320 //MP1_C2PMSG_73 1321 #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 1322 #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 1323 //MP1_C2PMSG_74 1324 #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 1325 #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 1326 //MP1_C2PMSG_75 1327 #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 1328 #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 1329 //MP1_C2PMSG_76 1330 #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 1331 #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 1332 //MP1_C2PMSG_77 1333 #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 1334 #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 1335 //MP1_C2PMSG_78 1336 #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 1337 #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 1338 //MP1_C2PMSG_79 1339 #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 1340 #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 1341 //MP1_C2PMSG_80 1342 #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 1343 #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 1344 //MP1_C2PMSG_81 1345 #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 1346 #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 1347 //MP1_C2PMSG_82 1348 #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 1349 #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 1350 //MP1_C2PMSG_83 1351 #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 1352 #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 1353 //MP1_C2PMSG_84 1354 #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 1355 #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 1356 //MP1_C2PMSG_85 1357 #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 1358 #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 1359 //MP1_C2PMSG_86 1360 #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 1361 #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 1362 //MP1_C2PMSG_87 1363 #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 1364 #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 1365 //MP1_C2PMSG_88 1366 #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 1367 #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 1368 //MP1_C2PMSG_89 1369 #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 1370 #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 1371 //MP1_C2PMSG_90 1372 #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 1373 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 1374 //MP1_C2PMSG_91 1375 #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 1376 #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 1377 //MP1_C2PMSG_92 1378 #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 1379 #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 1380 //MP1_C2PMSG_93 1381 #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 1382 #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 1383 //MP1_C2PMSG_94 1384 #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 1385 #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 1386 //MP1_C2PMSG_95 1387 #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 1388 #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 1389 //MP1_C2PMSG_96 1390 #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 1391 #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 1392 //MP1_C2PMSG_97 1393 #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 1394 #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 1395 //MP1_C2PMSG_98 1396 #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 1397 #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 1398 //MP1_C2PMSG_99 1399 #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 1400 #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 1401 //MP1_C2PMSG_100 1402 #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 1403 #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 1404 //MP1_C2PMSG_101 1405 #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 1406 #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 1407 //MP1_C2PMSG_102 1408 #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 1409 #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 1410 //MP1_C2PMSG_103 1411 #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 1412 #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 1413 //MP1_ACTIVE_FCN_ID 1414 #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1415 #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1416 #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 1417 #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 1418 //MP1_IH_CREDIT 1419 #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 1420 #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 1421 #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 1422 #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 1423 //MP1_IH_SW_INT 1424 #define MP1_IH_SW_INT__ID__SHIFT 0x0 1425 #define MP1_IH_SW_INT__VALID__SHIFT 0x8 1426 #define MP1_IH_SW_INT__ID_MASK 0x000000FFL 1427 #define MP1_IH_SW_INT__VALID_MASK 0x00000100L 1428 //MP1_IH_SW_INT_CTRL 1429 #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 1430 #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 1431 #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 1432 #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 1433 //MP1_FPS_CNT 1434 #define MP1_FPS_CNT__COUNT__SHIFT 0x0 1435 #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 1436 //MP1_PUB_CTRL 1437 #define MP1_PUB_CTRL__RESET__SHIFT 0x0 1438 #define MP1_PUB_CTRL__RESET_MASK 0x00000001L 1439 //MP1_EXT_SCRATCH0 1440 #define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 1441 #define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 1442 //MP1_EXT_SCRATCH1 1443 #define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 1444 #define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 1445 //MP1_EXT_SCRATCH2 1446 #define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 1447 #define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 1448 //MP1_EXT_SCRATCH3 1449 #define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 1450 #define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 1451 //MP1_EXT_SCRATCH4 1452 #define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 1453 #define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 1454 //MP1_EXT_SCRATCH5 1455 #define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 1456 #define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 1457 //MP1_EXT_SCRATCH6 1458 #define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 1459 #define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 1460 //MP1_EXT_SCRATCH7 1461 #define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 1462 #define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 1463 1464 1465 #endif 1466