1 /* Subroutines for insn-output.c for Matsushita MN10200 series
2 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "rtl.h"
26 #include "tree.h"
27 #include "regs.h"
28 #include "hard-reg-set.h"
29 #include "real.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "output.h"
33 #include "insn-attr.h"
34 #include "flags.h"
35 #include "recog.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "obstack.h"
39 #include "ggc.h"
40 #include "toplev.h"
41 #include "tm_p.h"
42 #include "target.h"
43 #include "target-def.h"
44
45 /* Global registers known to hold the value zero.
46
47 Normally we'd depend on CSE and combine to put zero into a
48 register and re-use it.
49
50 However, on the mn10x00 processors we implicitly use the constant
51 zero in tst instructions, so we might be able to do better by
52 loading the value into a register in the prologue, then re-useing
53 that register throughout the function.
54
55 We could perform similar optimizations for other constants, but with
56 gcse due soon, it doesn't seem worth the effort.
57
58 These variables hold a rtx for a register known to hold the value
59 zero throughout the entire function, or NULL if no register of
60 the appropriate class has such a value throughout the life of the
61 function. */
62 rtx zero_dreg;
63 rtx zero_areg;
64
65 static void count_tst_insns PARAMS ((int *));
66
67 /* Note whether or not we need an out of line epilogue. */
68 static int out_of_line_epilogue;
69
70 /* Initialize the GCC target structure. */
71 #undef TARGET_ASM_ALIGNED_HI_OP
72 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
73
74 struct gcc_target targetm = TARGET_INITIALIZER;
75
76 /* Indicate this file was compiled by gcc and what optimization
77 level was used. */
78 void
asm_file_start(file)79 asm_file_start (file)
80 FILE *file;
81 {
82 fprintf (file, "#\tGCC For the Matsushita MN10200\n");
83 if (optimize)
84 fprintf (file, "# -O%d\n", optimize);
85 else
86 fprintf (file, "\n\n");
87 output_file_directive (file, main_input_filename);
88 }
89
90 /* Print operand X using operand code CODE to assembly language output file
91 FILE. */
92
93 void
print_operand(file,x,code)94 print_operand (file, x, code)
95 FILE *file;
96 rtx x;
97 int code;
98 {
99 switch (code)
100 {
101 case 'b':
102 case 'B':
103 /* These are normal and reversed branches. */
104 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
105 {
106 case NE:
107 fprintf (file, "ne");
108 break;
109 case EQ:
110 fprintf (file, "eq");
111 break;
112 case GE:
113 fprintf (file, "ge");
114 break;
115 case GT:
116 fprintf (file, "gt");
117 break;
118 case LE:
119 fprintf (file, "le");
120 break;
121 case LT:
122 fprintf (file, "lt");
123 break;
124 case GEU:
125 fprintf (file, "cc");
126 break;
127 case GTU:
128 fprintf (file, "hi");
129 break;
130 case LEU:
131 fprintf (file, "ls");
132 break;
133 case LTU:
134 fprintf (file, "cs");
135 break;
136 default:
137 abort ();
138 }
139 break;
140 case 'C':
141 /* This is used for the operand to a call instruction;
142 if it's a REG, enclose it in parens, else output
143 the operand normally. */
144 if (GET_CODE (x) == REG)
145 {
146 fputc ('(', file);
147 print_operand (file, x, 0);
148 fputc (')', file);
149 }
150 else
151 print_operand (file, x, 0);
152 break;
153
154 /* These are the least significant word in a 32bit value.
155 'o' allows us to sign extend a constant if doing so
156 makes for more compact code. */
157 case 'L':
158 case 'o':
159 switch (GET_CODE (x))
160 {
161 case MEM:
162 fputc ('(', file);
163 output_address (XEXP (x, 0));
164 fputc (')', file);
165 break;
166
167 case REG:
168 fprintf (file, "%s", reg_names[REGNO (x)]);
169 break;
170
171 case SUBREG:
172 fprintf (file, "%s", reg_names[subreg_regno (x)]);
173 break;
174
175 case CONST_DOUBLE:
176 if (code == 'L')
177 {
178 long val;
179 REAL_VALUE_TYPE rv;
180
181 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
182 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
183 print_operand_address (file, GEN_INT (val & 0xffff));
184 }
185 else
186 {
187 long val;
188 REAL_VALUE_TYPE rv;
189
190 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
191 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
192
193 val &= 0xffff;
194 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
195 print_operand_address (file, GEN_INT (val));
196 }
197 break;
198
199 case CONST_INT:
200 if (code == 'L')
201 print_operand_address (file, GEN_INT ((INTVAL (x) & 0xffff)));
202 else
203 {
204 unsigned int val = INTVAL (x) & 0xffff;
205 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
206 print_operand_address (file, GEN_INT (val));
207 }
208 break;
209 default:
210 abort ();
211 }
212 break;
213
214 /* Similarly, but for the most significant word. */
215 case 'H':
216 case 'h':
217 switch (GET_CODE (x))
218 {
219 case MEM:
220 fputc ('(', file);
221 x = adjust_address (x, HImode, 2);
222 output_address (XEXP (x, 0));
223 fputc (')', file);
224 break;
225
226 case REG:
227 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
228 break;
229
230 case SUBREG:
231 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
232 break;
233
234 case CONST_DOUBLE:
235 if (code == 'H')
236 {
237 long val;
238 REAL_VALUE_TYPE rv;
239
240 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
241 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
242
243 print_operand_address (file, GEN_INT ((val >> 16) & 0xffff));
244 }
245 else
246 {
247 long val;
248 REAL_VALUE_TYPE rv;
249
250 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
251 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
252
253 val = (val >> 16) & 0xffff;
254 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
255
256 print_operand_address (file, GEN_INT (val));
257 }
258 break;
259
260 case CONST_INT:
261 if (code == 'H')
262 print_operand_address (file,
263 GEN_INT ((INTVAL (x) >> 16) & 0xffff));
264 else
265 {
266 unsigned int val = (INTVAL (x) >> 16) & 0xffff;
267 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
268
269 print_operand_address (file, GEN_INT (val));
270 }
271 break;
272 default:
273 abort ();
274 }
275 break;
276
277 /* Output ~CONST_INT. */
278 case 'N':
279 if (GET_CODE (x) != CONST_INT)
280 abort ();
281 fprintf (file, "%d", ~INTVAL (x));
282 break;
283
284 /* An address which can not be register indirect, if it is
285 register indirect, then turn it into reg + disp. */
286 case 'A':
287 if (GET_CODE (x) != MEM)
288 abort ();
289 if (GET_CODE (XEXP (x, 0)) == REG)
290 x = gen_rtx_PLUS (PSImode, XEXP (x, 0), GEN_INT (0));
291 else
292 x = XEXP (x, 0);
293 fputc ('(', file);
294 output_address (x);
295 fputc (')', file);
296 break;
297
298 case 'Z':
299 print_operand (file, XEXP (x, 1), 0);
300 break;
301
302 /* More cases where we can sign-extend a CONST_INT if it
303 results in more compact code. */
304 case 's':
305 case 'S':
306 if (GET_CODE (x) == CONST_INT)
307 {
308 int val = INTVAL (x);
309
310 if (code == 's')
311 x = GEN_INT (((val & 0xffff) ^ (~0x7fff)) + 0x8000);
312 else
313 x = GEN_INT (((val & 0xff) ^ (~0x7f)) + 0x80);
314 }
315 /* FALL THROUGH */
316 default:
317 switch (GET_CODE (x))
318 {
319 case MEM:
320 fputc ('(', file);
321 output_address (XEXP (x, 0));
322 fputc (')', file);
323 break;
324
325 case REG:
326 fprintf (file, "%s", reg_names[REGNO (x)]);
327 break;
328
329 case SUBREG:
330 fprintf (file, "%s", reg_names[subreg_regno (x)]);
331 break;
332
333 case CONST_INT:
334 case CONST_DOUBLE:
335 case SYMBOL_REF:
336 case CONST:
337 case LABEL_REF:
338 case CODE_LABEL:
339 print_operand_address (file, x);
340 break;
341 default:
342 abort ();
343 }
344 break;
345 }
346 }
347
348 /* Output assembly language output for the address ADDR to FILE. */
349
350 void
print_operand_address(file,addr)351 print_operand_address (file, addr)
352 FILE *file;
353 rtx addr;
354 {
355 switch (GET_CODE (addr))
356 {
357 case REG:
358 print_operand (file, addr, 0);
359 break;
360 case PLUS:
361 {
362 rtx base, index;
363 /* The base and index could be in any order, so we have
364 to figure out which is the base and which is the index.
365 Uses the same code as GO_IF_LEGITIMATE_ADDRESS. */
366 if (REG_P (XEXP (addr, 0))
367 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
368 base = XEXP (addr, 0), index = XEXP (addr, 1);
369 else if (REG_P (XEXP (addr, 1))
370 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
371 base = XEXP (addr, 1), index = XEXP (addr, 0);
372 else
373 abort ();
374 print_operand (file, index, 0);
375 fputc (',', file);
376 print_operand (file, base, 0);;
377 break;
378 }
379 case SYMBOL_REF:
380 output_addr_const (file, addr);
381 break;
382 default:
383 output_addr_const (file, addr);
384 break;
385 }
386 }
387
388 /* Count the number of tst insns which compare an address register
389 with zero. */
390 static void
count_tst_insns(areg_countp)391 count_tst_insns (areg_countp)
392 int *areg_countp;
393 {
394 rtx insn;
395
396 /* Assume no tst insns exist. */
397 *areg_countp = 0;
398
399 /* If not optimizing, then quit now. */
400 if (!optimize)
401 return;
402
403 /* Walk through all the insns. */
404 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
405 {
406 rtx pat;
407
408 /* Ignore anything that is not a normal INSN. */
409 if (GET_CODE (insn) != INSN)
410 continue;
411
412 /* Ignore anything that isn't a SET. */
413 pat = PATTERN (insn);
414 if (GET_CODE (pat) != SET)
415 continue;
416
417 /* Check for a tst insn. */
418 if (SET_DEST (pat) == cc0_rtx
419 && GET_CODE (SET_SRC (pat)) == REG
420 && REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS)
421 (*areg_countp)++;
422 }
423 }
424
425 /* Return the total size (in bytes) of the current function's frame.
426 This is the size of the register save area + the size of locals,
427 spills, etc. */
428 int
total_frame_size()429 total_frame_size ()
430 {
431 unsigned int size = get_frame_size ();
432 unsigned int outgoing_args_size = current_function_outgoing_args_size;
433 int i;
434
435 /* First figure out if we're going to use an out of line
436 prologue, if so we have to make space for all the
437 registers, even if we don't use them. */
438 if (optimize && !current_function_needs_context && !frame_pointer_needed)
439 {
440 int inline_count, outline_count;
441
442 /* Compute how many bytes an inline prologue would take.
443
444 Each address register store takes two bytes, each data register
445 store takes three bytes. */
446 inline_count = 0;
447 if (regs_ever_live[5])
448 inline_count += 2;
449 if (regs_ever_live[6])
450 inline_count += 2;
451 if (regs_ever_live[2])
452 inline_count += 3;
453 if (regs_ever_live[3])
454 inline_count += 3;
455
456 /* If this function has any stack, then the stack adjustment
457 will take two (or more) bytes. */
458 if (size || outgoing_args_size
459 || regs_ever_live[5] || regs_ever_live[6]
460 || regs_ever_live[2] || regs_ever_live[3])
461 inline_count += 2;
462
463 /* Multiply the current count by two and add one to account for the
464 epilogue insns. */
465 inline_count = inline_count * 2 + 1;
466
467 /* Now compute how many bytes an out of line sequence would take. */
468 /* A relaxed jsr will be three bytes. */
469 outline_count = 3;
470
471 /* If there are outgoing arguments, then we will need a stack
472 pointer adjustment after the call to the prologue, two
473 more bytes. */
474 outline_count += (outgoing_args_size == 0 ? 0 : 2);
475
476 /* If there is some local frame to allocate, it will need to be
477 done before the call to the prologue, two more bytes. */
478 if (get_frame_size () != 0)
479 outline_count += 2;
480
481 /* Now account for the epilogue, multiply the base count by two,
482 then deal with optimizing away the rts instruction. */
483 outline_count = outline_count * 2 + 1;
484
485 if (get_frame_size () == 0 && outgoing_args_size == 0)
486 outline_count -= 1;
487
488 /* If an out of line prologue is smaller, use it. */
489 if (inline_count > outline_count)
490 return size + outgoing_args_size + 16;
491 }
492
493
494 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
495 {
496 if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i])
497 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
498 size += 4;
499 }
500
501 return (size + outgoing_args_size);
502 }
503
504 /* Expand the prologue into RTL. */
505 void
expand_prologue()506 expand_prologue ()
507 {
508 unsigned int size = total_frame_size ();
509 unsigned int outgoing_args_size = current_function_outgoing_args_size;
510 int offset, i;
511
512 zero_areg = NULL_RTX;
513 zero_dreg = NULL_RTX;
514
515 /* If optimizing, see if we should do an out of line prologue/epilogue
516 sequence.
517
518 We don't support out of line prologues if the current function
519 needs a context or frame pointer. */
520 if (optimize && !current_function_needs_context && !frame_pointer_needed)
521 {
522 int inline_count, outline_count, areg_count;
523
524 /* We need to end the current sequence so that count_tst_insns can
525 look at all the insns in this function. Normally this would be
526 unsafe, but it's OK in the prologue/epilogue expanders. */
527 end_sequence ();
528
529 /* Get a count of the number of tst insns which use address
530 registers (it's not profitable to try and improve tst insns
531 which use data registers). */
532 count_tst_insns (&areg_count);
533
534 /* Now start a new sequence. */
535 start_sequence ();
536
537 /* Compute how many bytes an inline prologue would take.
538
539 Each address register store takes two bytes, each data register
540 store takes three bytes. */
541 inline_count = 0;
542 if (regs_ever_live[5])
543 inline_count += 2;
544 if (regs_ever_live[6])
545 inline_count += 2;
546 if (regs_ever_live[2])
547 inline_count += 3;
548 if (regs_ever_live[3])
549 inline_count += 3;
550
551 /* If this function has any stack, then the stack adjustment
552 will take two (or more) bytes. */
553 if (size || outgoing_args_size
554 || regs_ever_live[5] || regs_ever_live[6]
555 || regs_ever_live[2] || regs_ever_live[3])
556 inline_count += 2;
557
558 /* Multiply the current count by two and add one to account for the
559 epilogue insns. */
560 inline_count = inline_count * 2 + 1;
561
562 /* Now compute how many bytes an out of line sequence would take. */
563 /* A relaxed jsr will be three bytes. */
564 outline_count = 3;
565
566 /* If there are outgoing arguments, then we will need a stack
567 pointer adjustment after the call to the prologue, two
568 more bytes. */
569 outline_count += (outgoing_args_size == 0 ? 0 : 2);
570
571 /* If there is some local frame to allocate, it will need to be
572 done before the call to the prologue, two more bytes. */
573 if (get_frame_size () != 0)
574 outline_count += 2;
575
576 /* Now account for the epilogue, multiply the base count by two,
577 then deal with optimizing away the rts instruction. */
578 outline_count = outline_count * 2 + 1;
579
580 if (get_frame_size () == 0 && outgoing_args_size == 0)
581 outline_count -= 1;
582
583 /* If an out of line prologue is smaller, use it. */
584 if (inline_count > outline_count)
585 {
586 if (get_frame_size () != 0)
587 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
588 GEN_INT (-size + outgoing_args_size + 16)));
589 emit_insn (gen_outline_prologue_call ());
590
591 if (outgoing_args_size)
592 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
593 GEN_INT (-outgoing_args_size)));
594
595 out_of_line_epilogue = 1;
596
597 /* Determine if it is profitable to put the value zero into a register
598 for the entire function. If so, set ZERO_DREG and ZERO_AREG. */
599
600 /* First see if we could load the value into a data register
601 since that's the most efficient way. */
602 if (areg_count > 1
603 && (!regs_ever_live[2] || !regs_ever_live[3]))
604 {
605 if (!regs_ever_live[2])
606 {
607 regs_ever_live[2] = 1;
608 zero_dreg = gen_rtx_REG (HImode, 2);
609 }
610 if (!regs_ever_live[3])
611 {
612 regs_ever_live[3] = 1;
613 zero_dreg = gen_rtx_REG (HImode, 3);
614 }
615 }
616
617 /* Now see if we could load the value into an address register. */
618 if (zero_dreg == NULL_RTX
619 && areg_count > 2
620 && (!regs_ever_live[5] || !regs_ever_live[6]))
621 {
622 if (!regs_ever_live[5])
623 {
624 regs_ever_live[5] = 1;
625 zero_areg = gen_rtx_REG (HImode, 5);
626 }
627 if (!regs_ever_live[6])
628 {
629 regs_ever_live[6] = 1;
630 zero_areg = gen_rtx_REG (HImode, 6);
631 }
632 }
633
634 if (zero_dreg)
635 emit_move_insn (zero_dreg, const0_rtx);
636
637 if (zero_areg)
638 emit_move_insn (zero_areg, const0_rtx);
639
640 return;
641 }
642 }
643
644 out_of_line_epilogue = 0;
645
646 /* Temporarily stuff the static chain onto the stack so we can
647 use a0 as a scratch register during the prologue. */
648 if (current_function_needs_context)
649 {
650 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
651 GEN_INT (-4)));
652 emit_move_insn (gen_rtx_MEM (PSImode, stack_pointer_rtx),
653 gen_rtx_REG (PSImode, STATIC_CHAIN_REGNUM));
654 }
655
656 if (frame_pointer_needed)
657 {
658 /* Store a2 into a0 temporarily. */
659 emit_move_insn (gen_rtx_REG (PSImode, 4), frame_pointer_rtx);
660
661 /* Set up the frame pointer. */
662 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
663 }
664
665 /* Make any necessary space for the saved registers and local frame. */
666 if (size)
667 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
668 GEN_INT (-size)));
669
670 /* Save the callee saved registers. They're saved into the top
671 of the frame, using the stack pointer. */
672 for (i = 0, offset = outgoing_args_size;
673 i < FIRST_PSEUDO_REGISTER; i++)
674 {
675 if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i])
676 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
677 {
678 int regno;
679
680 /* If we're saving the frame pointer, then it will be found in
681 register 4 (a0). */
682 regno = (i == FRAME_POINTER_REGNUM && frame_pointer_needed) ? 4 : i;
683
684 emit_move_insn (gen_rtx_MEM (PSImode,
685 plus_constant (stack_pointer_rtx,
686 offset)),
687 gen_rtx_REG (PSImode, regno));
688 offset += 4;
689 }
690 }
691
692 /* Now put the static chain back where the rest of the function
693 expects to find it.
694
695 Note that we may eliminate all references to this later, so we
696 mark the static chain as maybe dead. */
697 if (current_function_needs_context)
698 {
699 rtx insn;
700
701 insn = emit_move_insn (gen_rtx_REG (PSImode, STATIC_CHAIN_REGNUM),
702 gen_rtx (MEM, PSImode,
703 gen_rtx_PLUS (PSImode,
704 stack_pointer_rtx,
705 GEN_INT (size))));
706 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
707 const0_rtx,
708 REG_NOTES (insn));
709
710 }
711 }
712
713 /* Expand the epilogue into RTL. */
714 void
expand_epilogue()715 expand_epilogue ()
716 {
717 unsigned int size;
718 unsigned int outgoing_args_size = current_function_outgoing_args_size;
719 int offset, i, temp_regno;
720 rtx basereg;
721
722 size = total_frame_size ();
723
724 if (DECL_RESULT (current_function_decl)
725 && POINTER_TYPE_P (TREE_TYPE (DECL_RESULT (current_function_decl))))
726 temp_regno = 0;
727 else
728 temp_regno = 4;
729
730 /* Emit an out of line epilogue sequence if it's profitable to do so. */
731 if (out_of_line_epilogue)
732 {
733 /* If there were no outgoing arguments and no local frame, then
734 we will be able to omit the rts at the end of this function,
735 so just jump to the epilogue_noreturn routine. */
736 if (get_frame_size () == 0 && outgoing_args_size == 0)
737 {
738 emit_jump_insn (gen_outline_epilogue_jump ());
739 return;
740 }
741
742 if (outgoing_args_size)
743 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
744 GEN_INT (outgoing_args_size)));
745
746 if (temp_regno == 0)
747 emit_insn (gen_outline_epilogue_call_d0 ());
748 else if (temp_regno == 4)
749 emit_insn (gen_outline_epilogue_call_a0 ());
750
751 if (get_frame_size () != 0)
752 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
753 GEN_INT (size - outgoing_args_size - 16)));
754 emit_jump_insn (gen_return_internal ());
755 return;
756 }
757
758 /* Registers are restored from the frame pointer if we have one,
759 else they're restored from the stack pointer. Figure out
760 the appropriate offset to the register save area for both cases. */
761 if (frame_pointer_needed)
762 {
763 basereg = frame_pointer_rtx;
764 offset = -(size - outgoing_args_size);
765 }
766 else
767 {
768 basereg = stack_pointer_rtx;
769 offset = outgoing_args_size;
770 }
771
772 /* Restore each register. */
773 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
774 {
775 if ((regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i])
776 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
777 {
778 int regno;
779
780 /* Restore the frame pointer (if it exists) into a temporary
781 register. */
782 regno = ((i == FRAME_POINTER_REGNUM && frame_pointer_needed)
783 ? temp_regno : i);
784
785 emit_move_insn (gen_rtx_REG (PSImode, regno),
786 gen_rtx_MEM (PSImode,
787 plus_constant (basereg, offset)));
788 offset += 4;
789 }
790 }
791
792 if (frame_pointer_needed)
793 {
794 /* Deallocate this frame's stack. */
795 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
796 /* Restore the old frame pointer. */
797 emit_move_insn (frame_pointer_rtx, gen_rtx_REG (PSImode, temp_regno));
798 }
799 else if (size)
800 {
801 /* Deallocate this function's stack. */
802 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
803 GEN_INT (size)));
804 }
805
806 /* If we had to allocate a slot to save the context pointer,
807 then it must be deallocated here. */
808 if (current_function_needs_context)
809 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (4)));
810
811 /* Emit the return insn, if this function had no stack, then we
812 can use the standard return (which allows more optimizations),
813 else we have to use the special one which inhibits optimizations. */
814 if (size == 0 && !current_function_needs_context)
815 emit_jump_insn (gen_return ());
816 else
817 emit_jump_insn (gen_return_internal ());
818 }
819
820 /* Update the condition code from the insn. */
821
822 void
notice_update_cc(body,insn)823 notice_update_cc (body, insn)
824 rtx body;
825 rtx insn;
826 {
827 switch (get_attr_cc (insn))
828 {
829 case CC_NONE:
830 /* Insn does not affect CC at all. */
831 break;
832
833 case CC_NONE_0HIT:
834 /* Insn does not change CC, but the 0'th operand has been changed. */
835 if (cc_status.value1 != 0
836 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
837 cc_status.value1 = 0;
838 break;
839
840 case CC_SET_ZN:
841 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
842 V,C is in an unusable state. */
843 CC_STATUS_INIT;
844 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
845 cc_status.value1 = recog_data.operand[0];
846 break;
847
848 case CC_SET_ZNV:
849 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
850 C is in an unusable state. */
851 CC_STATUS_INIT;
852 cc_status.flags |= CC_NO_CARRY;
853 cc_status.value1 = recog_data.operand[0];
854 break;
855
856 case CC_COMPARE:
857 /* The insn is a compare instruction. */
858 CC_STATUS_INIT;
859 cc_status.value1 = SET_SRC (body);
860 break;
861
862 case CC_CLOBBER:
863 /* Insn doesn't leave CC in a usable state. */
864 CC_STATUS_INIT;
865 break;
866
867 default:
868 CC_STATUS_INIT;
869 break;
870 }
871 }
872
873 /* Return true if OP is a valid call operand. Valid call operands
874 are SYMBOL_REFs and REGs. */
875 int
call_address_operand(op,mode)876 call_address_operand (op, mode)
877 rtx op;
878 enum machine_mode mode ATTRIBUTE_UNUSED;
879 {
880 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
881 }
882
883 /* Return true if OP is a memory operand with a constant address.
884 A special PSImode move pattern uses this predicate. */
885 int
constant_memory_operand(op,mode)886 constant_memory_operand (op, mode)
887 rtx op;
888 enum machine_mode mode ATTRIBUTE_UNUSED;
889 {
890 return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0));
891 }
892
893 /* Return true if OP is valid for a psi mode truncation operand.
894 It must either be a memory operand which is valid for a PSImode
895 address, or if it is not a memory operand at all. */
896 int
psimode_truncation_operand(op,mode)897 psimode_truncation_operand (op, mode)
898 rtx op;
899 enum machine_mode mode;
900 {
901 return (general_operand (op, mode)
902 && (GET_CODE (op) != MEM
903 || memory_address_p (PSImode, XEXP (op, 0))));
904 }
905
906 /* What (if any) secondary registers are needed to move IN with mode
907 MODE into a register from in register class CLASS.
908
909 We might be able to simplify this. */
910 enum reg_class
secondary_reload_class(class,mode,in,input)911 secondary_reload_class (class, mode, in, input)
912 enum reg_class class;
913 enum machine_mode mode;
914 rtx in;
915 int input;
916 {
917 /* Memory loads less than a full word wide can't have an
918 address or stack pointer destination. They must use
919 a data register as an intermediate register. */
920 if (input
921 && GET_CODE (in) == MEM
922 && (mode == QImode)
923 && class == ADDRESS_REGS)
924 return DATA_REGS;
925
926 /* Address register stores which are not PSImode need a scratch register. */
927 if (! input
928 && GET_CODE (in) == MEM
929 && (mode != PSImode)
930 && class == ADDRESS_REGS)
931 return DATA_REGS;
932
933 /* Otherwise assume no secondary reloads are needed. */
934 return NO_REGS;
935 }
936
937
938 /* Shifts.
939
940 We devote a fair bit of code to getting efficient shifts since we can only
941 shift one bit at a time, and each single bit shift may take multiple
942 instructions.
943
944 The basic shift methods:
945
946 * loop shifts -- emit a loop using one (or two on H8S) bit shifts;
947 this is the default. SHIFT_LOOP
948
949 * inlined shifts -- emit straight line code for the shift; this is
950 used when a straight line shift is about the same size or smaller
951 than a loop. We allow the inline version to be slightly longer in
952 some cases as it saves a register. SHIFT_INLINE
953
954 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
955
956
957 HImode shifts:
958
959 1-4 do them inline
960
961 5-7 If ashift, then multiply, else loop.
962
963 8-14 - If ashift, then multiply, if lshiftrt, then divide, else loop.
964 15 - rotate the bit we want into the carry, clear the destination,
965 (use mov 0,dst, not sub as sub will clobber the carry), then
966 move bit into place.
967
968 Don't Panic, it's not nearly as bad as the H8 shifting code!!! */
969
970 int
nshift_operator(x,mode)971 nshift_operator (x, mode)
972 rtx x;
973 enum machine_mode mode ATTRIBUTE_UNUSED;
974 {
975 switch (GET_CODE (x))
976 {
977 case ASHIFTRT:
978 case LSHIFTRT:
979 case ASHIFT:
980 return 1;
981
982 default:
983 return 0;
984 }
985 }
986
987 /* Called from the .md file to emit code to do shifts.
988 Returns a boolean indicating success
989 (currently this is always TRUE). */
990
991 int
expand_a_shift(mode,code,operands)992 expand_a_shift (mode, code, operands)
993 enum machine_mode mode;
994 int code;
995 rtx operands[];
996 {
997 emit_move_insn (operands[0], operands[1]);
998
999 /* need a loop to get all the bits we want - we generate the
1000 code at emit time, but need to allocate a scratch reg now */
1001
1002 emit_insn (gen_rtx_PARALLEL
1003 (VOIDmode,
1004 gen_rtvec (2,
1005 gen_rtx_SET (VOIDmode, operands[0],
1006 gen_rtx (code, mode,
1007 operands[0], operands[2])),
1008 gen_rtx_CLOBBER (VOIDmode,
1009 gen_rtx_SCRATCH (HImode)))));
1010
1011 return 1;
1012 }
1013
1014 /* Shift algorithm determination.
1015
1016 There are various ways of doing a shift:
1017 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1018 shifts as we need.
1019 SHIFT_SPECIAL: Hand crafted assembler.
1020 SHIFT_LOOP: If the above methods fail, just loop. */
1021
1022 enum shift_alg
1023 {
1024 SHIFT_INLINE,
1025 SHIFT_SPECIAL,
1026 SHIFT_LOOP,
1027 SHIFT_MAX
1028 };
1029
1030 /* Symbols of the various shifts which can be used as indices. */
1031
1032 enum shift_type
1033 {
1034 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1035 };
1036
1037 /* Symbols of the various modes which can be used as indices. */
1038
1039 enum shift_mode
1040 {
1041 HIshift
1042 };
1043
1044 /* For single bit shift insns, record assembler and what bits of the
1045 condition code are valid afterwards (represented as various CC_FOO
1046 bits, 0 means CC isn't left in a usable state). */
1047
1048 struct shift_insn
1049 {
1050 const char *assembler;
1051 int cc_valid;
1052 };
1053
1054 /* Assembler instruction shift table.
1055
1056 These tables are used to look up the basic shifts.
1057 They are indexed by cpu, shift_type, and mode.
1058 */
1059
1060 static const struct shift_insn shift_one[3][3] =
1061 {
1062 {
1063 /* SHIFT_ASHIFT */
1064 { "add\t%0,%0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1065 },
1066 /* SHIFT_LSHIFTRT */
1067 {
1068 { "lsr\t%0", CC_NO_CARRY },
1069 },
1070 /* SHIFT_ASHIFTRT */
1071 {
1072 { "asr\t%0", CC_NO_CARRY },
1073 },
1074 };
1075
1076 static enum shift_alg get_shift_alg PARAMS ((enum shift_type,
1077 enum machine_mode, int,
1078 const char **, int *));
1079
1080 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1081 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1082 We don't achieve maximum efficiency in all cases, but the hooks are here
1083 to do so.
1084
1085 For now we just use lots of switch statements. Since we don't even come
1086 close to supporting all the cases, this is simplest. If this function ever
1087 gets too big, perhaps resort to a more table based lookup. Of course,
1088 at this point you may just wish to do it all in rtl. */
1089
1090 static enum shift_alg
get_shift_alg(shift_type,mode,count,assembler_p,cc_valid_p)1091 get_shift_alg (shift_type, mode, count, assembler_p, cc_valid_p)
1092 enum shift_type shift_type;
1093 enum machine_mode mode;
1094 int count;
1095 const char **assembler_p;
1096 int *cc_valid_p;
1097 {
1098 /* The default is to loop. */
1099 enum shift_alg alg = SHIFT_LOOP;
1100 enum shift_mode shift_mode;
1101
1102 /* We don't handle negative shifts or shifts greater than the word size,
1103 they should have been handled already. */
1104
1105 if (count < 0 || count > GET_MODE_BITSIZE (mode))
1106 abort ();
1107
1108 switch (mode)
1109 {
1110 case HImode:
1111 shift_mode = HIshift;
1112 break;
1113 default:
1114 abort ();
1115 }
1116
1117 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1118 It is up to the caller to know that looping clobbers cc. */
1119 *assembler_p = shift_one[shift_type][shift_mode].assembler;
1120 *cc_valid_p = shift_one[shift_type][shift_mode].cc_valid;
1121
1122 /* Now look for cases we want to optimize. */
1123
1124 switch (shift_mode)
1125 {
1126 case HIshift:
1127 if (count <= 4)
1128 return SHIFT_INLINE;
1129 else if (count < 15 && shift_type != SHIFT_ASHIFTRT)
1130 {
1131 switch (count)
1132 {
1133 case 5:
1134 if (shift_type == SHIFT_ASHIFT)
1135 *assembler_p = "mov 32,%4\n\tmul %4,%0";
1136 else if (shift_type == SHIFT_LSHIFTRT)
1137 *assembler_p
1138 = "sub %4,%4\n\tmov %4,mdr\n\tmov 32,%4\n\tdivu %4,%0";
1139 *cc_valid_p = CC_NO_CARRY;
1140 return SHIFT_SPECIAL;
1141 case 6:
1142 if (shift_type == SHIFT_ASHIFT)
1143 *assembler_p = "mov 64,%4\n\tmul %4,%0";
1144 else if (shift_type == SHIFT_LSHIFTRT)
1145 *assembler_p
1146 = "sub %4,%4\n\tmov %4,mdr\n\tmov 64,%4\n\tdivu %4,%0";
1147 *cc_valid_p = CC_NO_CARRY;
1148 return SHIFT_SPECIAL;
1149 case 7:
1150 if (shift_type == SHIFT_ASHIFT)
1151 *assembler_p = "mov 128,%4\n\tmul %4,%0";
1152 else if (shift_type == SHIFT_LSHIFTRT)
1153 *assembler_p
1154 = "sub %4,%4\n\tmov %4,mdr\n\tmov 128,%4\n\tdivu %4,%0";
1155 *cc_valid_p = CC_NO_CARRY;
1156 return SHIFT_SPECIAL;
1157 case 8:
1158 if (shift_type == SHIFT_ASHIFT)
1159 *assembler_p = "mov 256,%4\n\tmul %4,%0";
1160 else if (shift_type == SHIFT_LSHIFTRT)
1161 *assembler_p
1162 = "sub %4,%4\n\tmov %4,mdr\n\tmov 256,%4\n\tdivu %4,%0";
1163 *cc_valid_p = CC_NO_CARRY;
1164 return SHIFT_SPECIAL;
1165 case 9:
1166 if (shift_type == SHIFT_ASHIFT)
1167 *assembler_p = "mov 512,%4\n\tmul %4,%0";
1168 else if (shift_type == SHIFT_LSHIFTRT)
1169 *assembler_p
1170 = "sub %4,%4\n\tmov %4,mdr\n\tmov 512,%4\n\tdivu %4,%0";
1171 *cc_valid_p = CC_NO_CARRY;
1172 return SHIFT_SPECIAL;
1173 case 10:
1174 if (shift_type == SHIFT_ASHIFT)
1175 *assembler_p = "mov 1024,%4\n\tmul %4,%0";
1176 else if (shift_type == SHIFT_LSHIFTRT)
1177 *assembler_p
1178 = "sub %4,%4\n\tmov %4,mdr\n\tmov 1024,%4\n\tdivu %4,%0";
1179 *cc_valid_p = CC_NO_CARRY;
1180 return SHIFT_SPECIAL;
1181 case 11:
1182 if (shift_type == SHIFT_ASHIFT)
1183 *assembler_p = "mov 2048,%4\n\tmul %4,%0";
1184 else if (shift_type == SHIFT_LSHIFTRT)
1185 *assembler_p
1186 = "sub %4,%4\n\tmov %4,mdr\n\tmov 2048,%4\n\tdivu %4,%0";
1187 *cc_valid_p = CC_NO_CARRY;
1188 return SHIFT_SPECIAL;
1189 case 12:
1190 if (shift_type == SHIFT_ASHIFT)
1191 *assembler_p = "mov 4096,%4\n\tmul %4,%0";
1192 else if (shift_type == SHIFT_LSHIFTRT)
1193 *assembler_p
1194 = "sub %4,%4\n\tmov %4,mdr\n\tmov 4096,%4\n\tdivu %4,%0";
1195 *cc_valid_p = CC_NO_CARRY;
1196 return SHIFT_SPECIAL;
1197 case 13:
1198 if (shift_type == SHIFT_ASHIFT)
1199 *assembler_p = "mov 8192,%4\n\tmul %4,%0";
1200 else if (shift_type == SHIFT_LSHIFTRT)
1201 *assembler_p
1202 = "sub %4,%4\n\tmov %4,mdr\n\tmov 8192,%4\n\tdivu %4,%0";
1203 *cc_valid_p = CC_NO_CARRY;
1204 return SHIFT_SPECIAL;
1205 case 14:
1206 if (shift_type == SHIFT_ASHIFT)
1207 *assembler_p = "mov 16384,%4\n\tmul %4,%0";
1208 else if (shift_type == SHIFT_LSHIFTRT)
1209 *assembler_p
1210 = "sub %4,%4\n\tmov %4,mdr\n\tmov 16384,%4\n\tdivu %4,%0";
1211 *cc_valid_p = CC_NO_CARRY;
1212 return SHIFT_SPECIAL;
1213 }
1214 }
1215 else if (count == 15)
1216 {
1217 if (shift_type == SHIFT_ASHIFTRT)
1218 {
1219 *assembler_p = "add\t%0,%0\n\tsubc\t%0,%0\n";
1220 *cc_valid_p = CC_NO_CARRY;
1221 return SHIFT_SPECIAL;
1222 }
1223 if (shift_type == SHIFT_LSHIFTRT)
1224 {
1225 *assembler_p = "add\t%0,%0\n\tmov 0,%0\n\trol %0\n";
1226 *cc_valid_p = CC_NO_CARRY;
1227 return SHIFT_SPECIAL;
1228 }
1229 if (shift_type == SHIFT_ASHIFT)
1230 {
1231 *assembler_p = "ror\t%0\n\tmov 0,%0\n\tror %0\n";
1232 *cc_valid_p = CC_NO_CARRY;
1233 return SHIFT_SPECIAL;
1234 }
1235 }
1236 break;
1237
1238 default:
1239 abort ();
1240 }
1241
1242 return alg;
1243 }
1244
1245 /* Emit the assembler code for doing shifts. */
1246
1247 const char *
emit_a_shift(insn,operands)1248 emit_a_shift (insn, operands)
1249 rtx insn ATTRIBUTE_UNUSED;
1250 rtx *operands;
1251 {
1252 static int loopend_lab;
1253 const char *assembler;
1254 int cc_valid;
1255 rtx shift = operands[3];
1256 enum machine_mode mode = GET_MODE (shift);
1257 enum rtx_code code = GET_CODE (shift);
1258 enum shift_type shift_type;
1259 enum shift_mode shift_mode;
1260
1261 loopend_lab++;
1262
1263 switch (mode)
1264 {
1265 case HImode:
1266 shift_mode = HIshift;
1267 break;
1268 default:
1269 abort ();
1270 }
1271
1272 switch (code)
1273 {
1274 case ASHIFTRT:
1275 shift_type = SHIFT_ASHIFTRT;
1276 break;
1277 case LSHIFTRT:
1278 shift_type = SHIFT_LSHIFTRT;
1279 break;
1280 case ASHIFT:
1281 shift_type = SHIFT_ASHIFT;
1282 break;
1283 default:
1284 abort ();
1285 }
1286
1287 if (GET_CODE (operands[2]) != CONST_INT)
1288 {
1289 /* Indexing by reg, so have to loop and test at top */
1290 output_asm_insn ("mov %2,%4", operands);
1291 output_asm_insn ("cmp 0,%4", operands);
1292 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
1293
1294 /* Get the assembler code to do one shift. */
1295 get_shift_alg (shift_type, mode, 1, &assembler, &cc_valid);
1296 }
1297 else
1298 {
1299 int n = INTVAL (operands[2]);
1300 enum shift_alg alg;
1301
1302 /* If the count is negative, make it 0. */
1303 if (n < 0)
1304 n = 0;
1305 /* If the count is too big, truncate it.
1306 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
1307 do the intuitive thing. */
1308 else if (n > GET_MODE_BITSIZE (mode))
1309 n = GET_MODE_BITSIZE (mode);
1310
1311 alg = get_shift_alg (shift_type, mode, n, &assembler, &cc_valid);
1312
1313
1314 switch (alg)
1315 {
1316 case SHIFT_INLINE:
1317 /* Emit one bit shifts. */
1318 while (n > 0)
1319 {
1320 output_asm_insn (assembler, operands);
1321 n -= 1;
1322 }
1323
1324 /* Keep track of CC. */
1325 if (cc_valid)
1326 {
1327 cc_status.value1 = operands[0];
1328 cc_status.flags |= cc_valid;
1329 }
1330 return "";
1331
1332 case SHIFT_SPECIAL:
1333 output_asm_insn (assembler, operands);
1334
1335 /* Keep track of CC. */
1336 if (cc_valid)
1337 {
1338 cc_status.value1 = operands[0];
1339 cc_status.flags |= cc_valid;
1340 }
1341 return "";
1342 }
1343
1344 {
1345 fprintf (asm_out_file, "\tmov %d,%s\n", n,
1346 reg_names[REGNO (operands[4])]);
1347 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
1348 output_asm_insn (assembler, operands);
1349 output_asm_insn ("add -1,%4", operands);
1350 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
1351 return "";
1352 }
1353 }
1354
1355 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
1356 output_asm_insn (assembler, operands);
1357 output_asm_insn ("add -1,%4", operands);
1358 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
1359 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
1360
1361 return "";
1362 }
1363
1364 /* Return an RTX to represent where a value with mode MODE will be returned
1365 from a function. If the result is 0, the argument is pushed. */
1366
1367 rtx
function_arg(cum,mode,type,named)1368 function_arg (cum, mode, type, named)
1369 CUMULATIVE_ARGS *cum;
1370 enum machine_mode mode;
1371 tree type;
1372 int named;
1373 {
1374 rtx result = 0;
1375 int size, align;
1376
1377 /* We only support using 2 data registers as argument registers. */
1378 int nregs = 2;
1379
1380 /* Only pass named arguments in registers. */
1381 if (!named)
1382 return NULL_RTX;
1383
1384 /* Figure out the size of the object to be passed. We lie and claim
1385 PSImode values are only two bytes since they fit in a single
1386 register. */
1387 if (mode == BLKmode)
1388 size = int_size_in_bytes (type);
1389 else if (mode == PSImode)
1390 size = 2;
1391 else
1392 size = GET_MODE_SIZE (mode);
1393
1394 /* Figure out the alignment of the object to be passed. */
1395 align = size;
1396
1397 cum->nbytes = (cum->nbytes + 1) & ~1;
1398
1399 /* Don't pass this arg via a register if all the argument registers
1400 are used up. */
1401 if (cum->nbytes + size > nregs * UNITS_PER_WORD)
1402 return 0;
1403
1404 switch (cum->nbytes / UNITS_PER_WORD)
1405 {
1406 case 0:
1407 result = gen_rtx_REG (mode, 0);
1408 break;
1409 case 1:
1410 result = gen_rtx_REG (mode, 1);
1411 break;
1412 default:
1413 result = 0;
1414 }
1415
1416 return result;
1417 }
1418
1419 /* Return the number of registers to use for an argument passed partially
1420 in registers and partially in memory. */
1421
1422 int
function_arg_partial_nregs(cum,mode,type,named)1423 function_arg_partial_nregs (cum, mode, type, named)
1424 CUMULATIVE_ARGS *cum;
1425 enum machine_mode mode;
1426 tree type;
1427 int named;
1428 {
1429 int size, align;
1430
1431 /* We only support using 2 data registers as argument registers. */
1432 int nregs = 2;
1433
1434 return 0;
1435 /* Only pass named arguments in registers. */
1436 if (!named)
1437 return 0;
1438
1439 /* Figure out the size of the object to be passed. */
1440 if (mode == BLKmode)
1441 size = int_size_in_bytes (type);
1442 else if (mode == PSImode)
1443 size = 2;
1444 else
1445 size = GET_MODE_SIZE (mode);
1446
1447 /* Figure out the alignment of the object to be passed. */
1448 align = size;
1449
1450 cum->nbytes = (cum->nbytes + 1) & ~1;
1451
1452 /* Don't pass this arg via a register if all the argument registers
1453 are used up. */
1454 if (cum->nbytes > nregs * UNITS_PER_WORD)
1455 return 0;
1456
1457 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1458 return 0;
1459
1460 /* Don't pass this arg via a register if it would be split between
1461 registers and memory. */
1462 if (type == NULL_TREE
1463 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1464 return 0;
1465
1466 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1467 }
1468
1469 rtx
mn10200_va_arg(valist,type)1470 mn10200_va_arg (valist, type)
1471 tree valist, type;
1472 {
1473 HOST_WIDE_INT align, rsize;
1474 tree t, ptr, pptr;
1475
1476 /* Compute the rounded size of the type. */
1477 align = PARM_BOUNDARY / BITS_PER_UNIT;
1478 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
1479
1480 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
1481 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
1482 TREE_SIDE_EFFECTS (t) = 1;
1483
1484 ptr = build_pointer_type (type);
1485
1486 /* "Large" types are passed by reference. */
1487 if (rsize > 8)
1488 {
1489 pptr = build_pointer_type (ptr);
1490 t = build1 (NOP_EXPR, pptr, t);
1491 TREE_SIDE_EFFECTS (t) = 1;
1492
1493 t = build1 (INDIRECT_REF, ptr, t);
1494 TREE_SIDE_EFFECTS (t) = 1;
1495 }
1496 else
1497 {
1498 t = build1 (NOP_EXPR, ptr, t);
1499 TREE_SIDE_EFFECTS (t) = 1;
1500 }
1501
1502 /* Calculate! */
1503 return force_reg (Pmode, expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL));
1504 }
1505
1506 const char *
output_tst(operand,insn)1507 output_tst (operand, insn)
1508 rtx operand, insn;
1509 {
1510
1511 rtx temp;
1512 int past_call = 0;
1513
1514 /* Only tst insns using address registers can be optimized. */
1515 if (REGNO_REG_CLASS (REGNO (operand)) != ADDRESS_REGS)
1516 return "cmp 0,%0";
1517
1518 /* If testing an address register against zero, we can do better if
1519 we know there's a register already holding the value zero. First
1520 see if a global register has been set to zero, else we do a search
1521 for a register holding zero, if both of those fail, then we use a
1522 compare against zero. */
1523 if (zero_dreg || zero_areg)
1524 {
1525 rtx xoperands[2];
1526 xoperands[0] = operand;
1527 xoperands[1] = zero_dreg ? zero_dreg : zero_areg;
1528
1529 output_asm_insn ("cmp %1,%0", xoperands);
1530 return "";
1531 }
1532
1533 /* We can save a byte if we can find a register which has the value
1534 zero in it. */
1535 temp = PREV_INSN (insn);
1536 while (temp)
1537 {
1538 rtx set;
1539
1540 /* We allow the search to go through call insns. We record
1541 the fact that we've past a CALL_INSN and reject matches which
1542 use call clobbered registers. */
1543 if (GET_CODE (temp) == CODE_LABEL
1544 || GET_CODE (temp) == JUMP_INSN
1545 || GET_CODE (temp) == BARRIER)
1546 break;
1547
1548 if (GET_CODE (temp) == CALL_INSN)
1549 past_call = 1;
1550
1551 if (GET_CODE (temp) == NOTE)
1552 {
1553 temp = PREV_INSN (temp);
1554 continue;
1555 }
1556
1557 /* It must be an insn, see if it is a simple set. */
1558 set = single_set (temp);
1559 if (!set)
1560 {
1561 temp = PREV_INSN (temp);
1562 continue;
1563 }
1564
1565 /* Are we setting a register to zero?
1566
1567 If it's a call clobbered register, have we past a call? */
1568 if (REG_P (SET_DEST (set))
1569 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1570 && !reg_set_between_p (SET_DEST (set), temp, insn)
1571 && (!past_call
1572 || !call_used_regs[REGNO (SET_DEST (set))]))
1573 {
1574 rtx xoperands[2];
1575 xoperands[0] = operand;
1576 xoperands[1] = SET_DEST (set);
1577
1578 output_asm_insn ("cmp %1,%0", xoperands);
1579 return "";
1580 }
1581 temp = PREV_INSN (temp);
1582 }
1583 return "cmp 0,%0";
1584 }
1585
1586 /* Return nonzero if OP is a valid operand for a {zero,sign}_extendpsisi
1587 instruction.
1588
1589 It accepts anything that is a general operand or the sum of the
1590 stack pointer and a general operand. */
1591 int
extendpsi_operand(op,mode)1592 extendpsi_operand (op, mode)
1593 rtx op;
1594 enum machine_mode mode;
1595 {
1596 return (general_operand (op, mode)
1597 || (GET_CODE (op) == PLUS
1598 && XEXP (op, 0) == stack_pointer_rtx
1599 && general_operand (XEXP (op, 1), VOIDmode)));
1600 }
1601