1 /* $NetBSD: mmc_pwrseq_simple.c,v 1.3 2021/01/27 03:10:21 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mmc_pwrseq_simple.c,v 1.3 2021/01/27 03:10:21 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/device.h>
35 #include <sys/systm.h>
36 #include <sys/proc.h>
37 #include <sys/gpio.h>
38
39 #include <dev/fdt/fdtvar.h>
40
41 #define MMCPWRSEQ_MAX_PINS 32
42
43 static const struct device_compatible_entry compat_data[] = {
44 { .compat = "mmc-pwrseq-simple" },
45 DEVICE_COMPAT_EOL
46 };
47
48 struct mmcpwrseq_simple_softc {
49 device_t sc_dev;
50 int sc_phandle;
51 struct clk *sc_clk;
52 struct fdtbus_gpio_pin *sc_pins[MMCPWRSEQ_MAX_PINS];
53 u_int sc_npins;
54 u_int sc_post_power_on_delay_ms;
55 u_int sc_power_off_delay_us;
56 };
57
58 static void
mmcpwrseq_simple_pre_power_on(device_t dev)59 mmcpwrseq_simple_pre_power_on(device_t dev)
60 {
61 struct mmcpwrseq_simple_softc * const sc = device_private(dev);
62 int error;
63
64 if (sc->sc_clk) {
65 error = clk_enable(sc->sc_clk);
66 if (error != 0) {
67 aprint_error_dev(dev, "failed to enable clock: %d\n",
68 error);
69 }
70 }
71
72 for (u_int n = 0; n < sc->sc_npins; n++)
73 fdtbus_gpio_write(sc->sc_pins[n], 1);
74 }
75
76 static void
mmcpwrseq_simple_post_power_on(device_t dev)77 mmcpwrseq_simple_post_power_on(device_t dev)
78 {
79 struct mmcpwrseq_simple_softc * const sc = device_private(dev);
80
81 for (u_int n = 0; n < sc->sc_npins; n++)
82 fdtbus_gpio_write(sc->sc_pins[n], 0);
83
84 if (sc->sc_post_power_on_delay_ms > 0)
85 kpause("mmcpwrseq", false,
86 mstohz(sc->sc_post_power_on_delay_ms), NULL);
87 }
88
89 static void
mmcpwrseq_simple_power_off(device_t dev)90 mmcpwrseq_simple_power_off(device_t dev)
91 {
92 struct mmcpwrseq_simple_softc * const sc = device_private(dev);
93
94 for (u_int n = 0; n < sc->sc_npins; n++)
95 fdtbus_gpio_write(sc->sc_pins[n], 1);
96
97 if (sc->sc_power_off_delay_us > 0)
98 delay(sc->sc_power_off_delay_us);
99 }
100
101 static const struct fdtbus_mmc_pwrseq_func mmcpwrseq_simple_funcs = {
102 .pre_power_on = mmcpwrseq_simple_pre_power_on,
103 .post_power_on = mmcpwrseq_simple_post_power_on,
104 .power_off = mmcpwrseq_simple_power_off,
105 };
106
107 static int
mmcpwrseq_simple_match(device_t parent,cfdata_t cf,void * aux)108 mmcpwrseq_simple_match(device_t parent, cfdata_t cf, void *aux)
109 {
110 struct fdt_attach_args * const faa = aux;
111
112 return of_compatible_match(faa->faa_phandle, compat_data);
113 }
114
115 static void
mmcpwrseq_simple_attach(device_t parent,device_t self,void * aux)116 mmcpwrseq_simple_attach(device_t parent, device_t self, void *aux)
117 {
118 struct mmcpwrseq_simple_softc * const sc = device_private(self);
119 struct fdt_attach_args * const faa = aux;
120 const int phandle = faa->faa_phandle;
121
122 sc->sc_dev = self;
123 sc->sc_phandle = phandle;
124
125 /* Optional external clock provider */
126 if (of_hasprop(phandle, "clocks")) {
127 sc->sc_clk = fdtbus_clock_get(phandle, "ext_clock");
128 if (sc->sc_clk == NULL) {
129 aprint_error(": couldn't acquire ext_clock\n");
130 return;
131 }
132 }
133
134 /* Optional reset GPIOs */
135 if (of_hasprop(phandle, "reset-gpios")) {
136 for (sc->sc_npins = 0;
137 sc->sc_npins < MMCPWRSEQ_MAX_PINS;
138 sc->sc_npins++) {
139 sc->sc_pins[sc->sc_npins] =
140 fdtbus_gpio_acquire_index(phandle,
141 "reset-gpios", sc->sc_npins, GPIO_PIN_OUTPUT);
142 if (sc->sc_pins[sc->sc_npins] == NULL)
143 break;
144 }
145 if (sc->sc_npins == 0) {
146 aprint_error(": couldn't get reset GPIOs\n");
147 return;
148 }
149 }
150
151 /* Delay in ms after powering the card and de-asserting reset GPIOs */
152 of_getprop_uint32(phandle, "post-power-on-delay-ms",
153 &sc->sc_post_power_on_delay_ms);
154 /* Delay in us after asserting the reset GPIOs during power off */
155 of_getprop_uint32(phandle, "power-off-delay-us",
156 &sc->sc_power_off_delay_us);
157
158 aprint_naive("\n");
159 aprint_normal(": Simple MMC power sequence provider\n");
160
161 fdtbus_register_mmc_pwrseq(self, phandle, &mmcpwrseq_simple_funcs);
162 }
163
164 CFATTACH_DECL_NEW(mmcpwrseq_simple, sizeof(struct mmcpwrseq_simple_softc),
165 mmcpwrseq_simple_match, mmcpwrseq_simple_attach, NULL, NULL);
166