1 #ifndef __MINIX_PADCONF_H 2 #define __MINIX_PADCONF_H 3 4 /* Define the start address of the padconf registers and the size of the block. 5 * The base must be page aligned, so we round down and the kernel adds the 6 * offset. The size must be a multiple of ARM_PAGE_SIZE, so we round up to 4KB. 7 */ 8 #define PADCONF_AM335X_REGISTERS_BASE 0x44E10000 9 #define PADCONF_AM335X_REGISTERS_OFFSET 0x0000 10 #define PADCONF_AM335X_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */ 11 #define PADCONF_DM37XX_REGISTERS_BASE 0x48002000 12 #define PADCONF_DM37XX_REGISTERS_OFFSET 0x0030 13 #define PADCONF_DM37XX_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */ 14 15 #define PADCONF_MUXMODE(X) (X & 0x7) /* mode 1 til 7 [2:0] */ 16 #define PADCONF_PULL_MODE(X) ((X & 0x3) << 3) /* 2 bits[4:3] */ 17 #define PADCONF_PULL_MODE_PD_DIS PADCONF_PULL_MODE(0) /* pull down disabled */ 18 #define PADCONF_PULL_MODE_PD_EN PADCONF_PULL_MODE(1) /* pull down enabled */ 19 #define PADCONF_PULL_MODE_PU_DIS PADCONF_PULL_MODE(2) /* pull up disabled */ 20 #define PADCONF_PULL_MODE_PU_EN PADCONF_PULL_MODE(3) /* pull up enabled */ 21 #define PADCONF_INPUT_ENABLE(X) ((X & 0x1) << 8) /* 1 bits[8] */ 22 #define PADCONF_OFF_MODE(X) ((X & 0xFE) << 9) /* 5 bits[13:9] */ 23 24 /* padconf pin definitions */ 25 #define CONTROL_PADCONF_SDRC_D0 (0x00000000) 26 #define CONTROL_PADCONF_SDRC_D2 (0x00000004) 27 #define CONTROL_PADCONF_SDRC_D4 (0x00000008) 28 #define CONTROL_PADCONF_SDRC_D6 (0x0000000C) 29 #define CONTROL_PADCONF_SDRC_D8 (0x00000010) 30 #define CONTROL_PADCONF_SDRC_D10 (0x00000014) 31 #define CONTROL_PADCONF_SDRC_D12 (0x00000018) 32 #define CONTROL_PADCONF_SDRC_D14 (0x0000001C) 33 #define CONTROL_PADCONF_SDRC_D16 (0x00000020) 34 #define CONTROL_PADCONF_SDRC_D18 (0x00000024) 35 #define CONTROL_PADCONF_SDRC_D20 (0x00000028) 36 #define CONTROL_PADCONF_SDRC_D22 (0x0000002C) 37 #define CONTROL_PADCONF_SDRC_D24 (0x00000030) 38 #define CONTROL_PADCONF_SDRC_D26 (0x00000034) 39 #define CONTROL_PADCONF_SDRC_D28 (0x00000038) 40 #define CONTROL_PADCONF_SDRC_D30 (0x0000003C) 41 #define CONTROL_PADCONF_SDRC_CLK (0x00000040) 42 #define CONTROL_PADCONF_SDRC_DQS1 (0x00000044) 43 #define CONTROL_PADCONF_SDRC_DQS3 (0x00000048) 44 #define CONTROL_PADCONF_GPMC_A2 (0x0000004C) 45 #define CONTROL_PADCONF_GPMC_A4 (0x00000050) 46 #define CONTROL_PADCONF_GPMC_A6 (0x00000054) 47 #define CONTROL_PADCONF_GPMC_A8 (0x00000058) 48 #define CONTROL_PADCONF_GPMC_A10 (0x0000005C) 49 #define CONTROL_PADCONF_GPMC_D1 (0x00000060) 50 #define CONTROL_PADCONF_GPMC_D3 (0x00000064) 51 #define CONTROL_PADCONF_GPMC_D5 (0x00000068) 52 #define CONTROL_PADCONF_GPMC_D7 (0x0000006C) 53 #define CONTROL_PADCONF_GPMC_D9 (0x00000070) 54 #define CONTROL_PADCONF_GPMC_D11 (0x00000074) 55 #define CONTROL_PADCONF_GPMC_D13 (0x00000078) 56 #define CONTROL_PADCONF_GPMC_D15 (0x0000007C) 57 #define CONTROL_PADCONF_GPMC_NCS1 (0x00000080) 58 #define CONTROL_PADCONF_GPMC_NCS3 (0x00000084) 59 #define CONTROL_PADCONF_GPMC_NCS5 (0x00000088) 60 #define CONTROL_PADCONF_GPMC_NCS7 (0x0000008C) 61 #define CONTROL_PADCONF_GPMC_NADV_ALE (0x00000090) 62 #define CONTROL_PADCONF_GPMC_NWE (0x00000094) 63 #define CONTROL_PADCONF_GPMC_NBE1 (0x00000098) 64 #define CONTROL_PADCONF_GPMC_WAIT0 (0x0000009C) 65 #define CONTROL_PADCONF_GPMC_WAIT2 (0x000000A0) 66 #define CONTROL_PADCONF_DSS_PCLK (0x000000A4) 67 #define CONTROL_PADCONF_DSS_VSYNC (0x000000A8) 68 #define CONTROL_PADCONF_DSS_DATA0 (0x000000AC) 69 #define CONTROL_PADCONF_DSS_DATA2 (0x000000B0) 70 #define CONTROL_PADCONF_DSS_DATA4 (0x000000B4) 71 #define CONTROL_PADCONF_DSS_DATA6 (0x000000B8) 72 #define CONTROL_PADCONF_DSS_DATA8 (0x000000BC) 73 #define CONTROL_PADCONF_DSS_DATA10 (0x000000C0) 74 #define CONTROL_PADCONF_DSS_DATA12 (0x000000C4) 75 #define CONTROL_PADCONF_DSS_DATA14 (0x000000C8) 76 #define CONTROL_PADCONF_DSS_DATA16 (0x000000CC) 77 #define CONTROL_PADCONF_DSS_DATA18 (0x000000D0) 78 #define CONTROL_PADCONF_DSS_DATA20 (0x000000D4) 79 #define CONTROL_PADCONF_DSS_DATA22 (0x000000D8) 80 #define CONTROL_PADCONF_CAM_HS (0x000000DC) 81 #define CONTROL_PADCONF_CAM_XCLKA (0x000000E0) 82 #define CONTROL_PADCONF_CAM_FLD (0x000000E4) 83 #define CONTROL_PADCONF_CAM_D1 (0x000000E8) 84 #define CONTROL_PADCONF_CAM_D3 (0x000000EC) 85 #define CONTROL_PADCONF_CAM_D5 (0x000000F0) 86 #define CONTROL_PADCONF_CAM_D7 (0x000000F4) 87 #define CONTROL_PADCONF_CAM_D9 (0x000000F8) 88 #define CONTROL_PADCONF_CAM_D11 (0x000000FC) 89 #define CONTROL_PADCONF_CAM_WEN (0x00000100) 90 #define CONTROL_PADCONF_CSI2_DX0 (0x00000104) 91 #define CONTROL_PADCONF_CSI2_DX1 (0x00000108) 92 #define CONTROL_PADCONF_MCBSP2_FSX (0x0000010C) 93 #define CONTROL_PADCONF_MCBSP2_DR (0x00000110) 94 #define CONTROL_PADCONF_MMC1_CLK (0x00000114) 95 #define CONTROL_PADCONF_MMC1_DAT0 (0x00000118) 96 #define CONTROL_PADCONF_MMC1_DAT2 (0x0000011C) 97 #define CONTROL_PADCONF_MMC2_CLK (0x00000128) 98 #define CONTROL_PADCONF_MMC2_DAT0 (0x0000012C) 99 #define CONTROL_PADCONF_MMC2_DAT2 (0x00000130) 100 #define CONTROL_PADCONF_MMC2_DAT4 (0x00000134) 101 #define CONTROL_PADCONF_MMC2_DAT6 (0x00000138) 102 #define CONTROL_PADCONF_MCBSP3_DX (0x0000013C) 103 #define CONTROL_PADCONF_MCBSP3_CLKX (0x00000140) 104 #define CONTROL_PADCONF_UART2_CTS (0x00000144) 105 #define CONTROL_PADCONF_UART2_TX (0x00000148) 106 #define CONTROL_PADCONF_UART1_TX (0x0000014C) 107 #define CONTROL_PADCONF_UART1_CTS (0x00000150) 108 #define CONTROL_PADCONF_MCBSP4_CLKX (0x00000154) 109 #define CONTROL_PADCONF_MCBSP4_DX (0x00000158) 110 #define CONTROL_PADCONF_MCBSP1_CLKR (0x0000015C) 111 #define CONTROL_PADCONF_MCBSP1_DX (0x00000160) 112 #define CONTROL_PADCONF_MCBSP_CLKS (0x00000164) 113 #define CONTROL_PADCONF_MCBSP1_CLKX (0x00000168) 114 #define CONTROL_PADCONF_UART3_RTS_SD (0x0000016C) 115 #define CONTROL_PADCONF_UART3_TX_IRTX (0x00000170) 116 #define CONTROL_PADCONF_HSUSB0_STP (0x00000174) 117 #define CONTROL_PADCONF_HSUSB0_NXT (0x00000178) 118 #define CONTROL_PADCONF_HSUSB0_DATA1 (0x0000017C) 119 #define CONTROL_PADCONF_HSUSB0_DATA3 (0x00000180) 120 #define CONTROL_PADCONF_HSUSB0_DATA5 (0x00000184) 121 #define CONTROL_PADCONF_HSUSB0_DATA7 (0x00000188) 122 #define CONTROL_PADCONF_I2C1_SDA (0x0000018C) 123 #define CONTROL_PADCONF_I2C2_SDA (0x00000190) 124 #define CONTROL_PADCONF_I2C3_SDA (0x00000194) 125 #define CONTROL_PADCONF_MCSPI1_CLK (0x00000198) 126 #define CONTROL_PADCONF_MCSPI1_SOMI (0x0000019C) 127 #define CONTROL_PADCONF_MCSPI1_CS1 (0x000001A0) 128 #define CONTROL_PADCONF_MCSPI1_CS3 (0x000001A4) 129 #define CONTROL_PADCONF_MCSPI2_SIMO (0x000001A8) 130 #define CONTROL_PADCONF_MCSPI2_CS0 (0x000001AC) 131 #define CONTROL_PADCONF_SYS_NIRQ (0x000001B0) 132 #define CONTROL_PADCONF_SAD2D_MCAD0 (0x000001B4) 133 #define CONTROL_PADCONF_SAD2D_MCAD2 (0x000001B8) 134 #define CONTROL_PADCONF_SAD2D_MCAD4 (0x000001BC) 135 #define CONTROL_PADCONF_SAD2D_MCAD6 (0x000001C0) 136 #define CONTROL_PADCONF_SAD2D_MCAD8 (0x000001C4) 137 #define CONTROL_PADCONF_SAD2D_MCAD10 (0x000001C8) 138 #define CONTROL_PADCONF_SAD2D_MCAD12 (0x000001CC) 139 #define CONTROL_PADCONF_SAD2D_MCAD14 (0x000001D0) 140 #define CONTROL_PADCONF_SAD2D_MCAD16 (0x000001D4) 141 #define CONTROL_PADCONF_SAD2D_MCAD18 (0x000001D8) 142 #define CONTROL_PADCONF_SAD2D_MCAD20 (0x000001DC) 143 #define CONTROL_PADCONF_SAD2D_MCAD22 (0x000001E0) 144 #define CONTROL_PADCONF_SAD2D_MCAD24 (0x000001E4) 145 #define CONTROL_PADCONF_SAD2D_MCAD26 (0x000001E8) 146 #define CONTROL_PADCONF_SAD2D_MCAD28 (0x000001EC) 147 #define CONTROL_PADCONF_SAD2D_MCAD30 (0x000001F0) 148 #define CONTROL_PADCONF_SAD2D_MCAD32 (0x000001F4) 149 #define CONTROL_PADCONF_SAD2D_MCAD34 (0x000001F8) 150 #define CONTROL_PADCONF_SAD2D_MCAD36 (0x000001FC) 151 #define CONTROL_PADCONF_SAD2D_NRESPWRON (0x00000200) 152 #define CONTROL_PADCONF_SAD2D_ARMNIRQ (0x00000204) 153 #define CONTROL_PADCONF_SAD2D_SPINT (0x00000208) 154 #define CONTROL_PADCONF_SAD2D_DMAREQ0 (0x0000020C) 155 #define CONTROL_PADCONF_SAD2D_DMAREQ2 (0x00000210) 156 #define CONTROL_PADCONF_SAD2D_NTRST (0x00000214) 157 #define CONTROL_PADCONF_SAD2D_TDO (0x00000218) 158 #define CONTROL_PADCONF_SAD2D_TCK (0x0000021C) 159 #define CONTROL_PADCONF_SAD2D_MSTDBY (0x00000220) 160 #define CONTROL_PADCONF_SAD2D_IDLEACK (0x00000224) 161 #define CONTROL_PADCONF_SAD2D_SWRITE (0x00000228) 162 #define CONTROL_PADCONF_SAD2D_SREAD (0x0000022C) 163 #define CONTROL_PADCONF_SAD2D_SBUSFLAG (0x00000230) 164 #define CONTROL_PADCONF_SDRC_CKE1 (0x00000234) 165 #define CONTROL_PADCONF_SDRC_BA0 (0x00000570) 166 #define CONTROL_PADCONF_SDRC_A0 (0x00000574) 167 #define CONTROL_PADCONF_SDRC_A2 (0x00000578) 168 #define CONTROL_PADCONF_SDRC_A4 (0x0000057C) 169 #define CONTROL_PADCONF_SDRC_A6 (0x00000580) 170 #define CONTROL_PADCONF_SDRC_A8 (0x00000584) 171 #define CONTROL_PADCONF_SDRC_A10 (0x00000588) 172 #define CONTROL_PADCONF_SDRC_A12 (0x0000058C) 173 #define CONTROL_PADCONF_SDRC_A14 (0x00000590) 174 #define CONTROL_PADCONF_SDRC_NCS1 (0x00000594) 175 #define CONTROL_PADCONF_SDRC_NRAS (0x00000598) 176 #define CONTROL_PADCONF_SDRC_NWE (0x0000059C) 177 #define CONTROL_PADCONF_SDRC_DM1 (0x000005A0) 178 #define CONTROL_PADCONF_SDRC_DM3 (0x000005A4) 179 #define CONTROL_PADCONF_ETK_CLK (0x000005A8) 180 #define CONTROL_PADCONF_ETK_D0 (0x000005AC) 181 #define CONTROL_PADCONF_ETK_D2 (0x000005B0) 182 #define CONTROL_PADCONF_ETK_D4 (0x000005B4) 183 #define CONTROL_PADCONF_ETK_D6 (0x000005B8) 184 #define CONTROL_PADCONF_ETK_D8 (0x000005BC) 185 #define CONTROL_PADCONF_ETK_D10 (0x000005C0) 186 #define CONTROL_PADCONF_ETK_D12 (0x000005C4) 187 #define CONTROL_PADCONF_ETK_D14 (0x000005C8) 188 189 /* conf pin descriptions (am335x) */ 190 #define CONTROL_CONF_GPMC_AD0 (0x00000800) 191 #define CONTROL_CONF_GPMC_AD1 (0x00000804) 192 #define CONTROL_CONF_GPMC_AD2 (0x00000808) 193 #define CONTROL_CONF_GPMC_AD3 (0x0000080C) 194 #define CONTROL_CONF_GPMC_AD4 (0x00000810) 195 #define CONTROL_CONF_GPMC_AD5 (0x00000814) 196 #define CONTROL_CONF_GPMC_AD6 (0x00000818) 197 #define CONTROL_CONF_GPMC_AD7 (0x0000081C) 198 #define CONTROL_CONF_GPMC_AD8 (0x00000820) 199 #define CONTROL_CONF_GPMC_AD9 (0x00000824) 200 #define CONTROL_CONF_GPMC_AD10 (0x00000828) 201 #define CONTROL_CONF_GPMC_AD11 (0x0000082C) 202 #define CONTROL_CONF_GPMC_AD12 (0x00000830) 203 #define CONTROL_CONF_GPMC_AD13 (0x00000834) 204 #define CONTROL_CONF_GPMC_AD14 (0x00000838) 205 #define CONTROL_CONF_GPMC_AD15 (0x0000083C) 206 #define CONTROL_CONF_GPMC_A0 (0x00000840) 207 #define CONTROL_CONF_GPMC_A1 (0x00000844) 208 #define CONTROL_CONF_GPMC_A2 (0x00000848) 209 #define CONTROL_CONF_GPMC_A3 (0x0000084C) 210 #define CONTROL_CONF_GPMC_A4 (0x00000850) 211 #define CONTROL_CONF_GPMC_A5 (0x00000854) 212 #define CONTROL_CONF_GPMC_A6 (0x00000858) 213 #define CONTROL_CONF_GPMC_A7 (0x0000085C) 214 #define CONTROL_CONF_GPMC_A8 (0x00000860) 215 #define CONTROL_CONF_GPMC_A9 (0x00000864) 216 #define CONTROL_CONF_GPMC_A10 (0x00000868) 217 #define CONTROL_CONF_GPMC_A11 (0x0000086C) 218 #define CONTROL_CONF_GPMC_WAIT0 (0x00000870) 219 #define CONTROL_CONF_GPMC_WPN (0x00000874) 220 #define CONTROL_CONF_GPMC_BEN1 (0x00000878) 221 #define CONTROL_CONF_GPMC_CSN0 (0x0000087C) 222 #define CONTROL_CONF_GPMC_CSN1 (0x00000880) 223 #define CONTROL_CONF_GPMC_CSN2 (0x00000884) 224 #define CONTROL_CONF_GPMC_CSN3 (0x00000888) 225 #define CONTROL_CONF_GPMC_CLK (0x0000088C) 226 #define CONTROL_CONF_GPMC_ADVN_ALE (0x00000890) 227 #define CONTROL_CONF_GPMC_OEN_REN (0x00000894) 228 #define CONTROL_CONF_GPMC_WEN (0x00000898) 229 #define CONTROL_CONF_GPMC_BEN0_CLE (0x0000089C) 230 #define CONTROL_CONF_LCD_DATA0 (0x000008A0) 231 #define CONTROL_CONF_LCD_DATA1 (0x000008A4) 232 #define CONTROL_CONF_LCD_DATA2 (0x000008A8) 233 #define CONTROL_CONF_LCD_DATA3 (0x000008AC) 234 #define CONTROL_CONF_LCD_DATA4 (0x000008B0) 235 #define CONTROL_CONF_LCD_DATA5 (0x000008B4) 236 #define CONTROL_CONF_LCD_DATA6 (0x000008B8) 237 #define CONTROL_CONF_LCD_DATA7 (0x000008BC) 238 #define CONTROL_CONF_LCD_DATA8 (0x000008C0) 239 #define CONTROL_CONF_LCD_DATA9 (0x000008C4) 240 #define CONTROL_CONF_LCD_DATA10 (0x000008C8) 241 #define CONTROL_CONF_LCD_DATA11 (0x000008CC) 242 #define CONTROL_CONF_LCD_DATA12 (0x000008D0) 243 #define CONTROL_CONF_LCD_DATA13 (0x000008D4) 244 #define CONTROL_CONF_LCD_DATA14 (0x000008D8) 245 #define CONTROL_CONF_LCD_DATA15 (0x000008DC) 246 #define CONTROL_CONF_LCD_VSYNC (0x000008E0) 247 #define CONTROL_CONF_LCD_HSYNC (0x000008E4) 248 #define CONTROL_CONF_LCD_PCLK (0x000008E8) 249 #define CONTROL_CONF_LCD_AC_BIAS_EN (0x000008EC) 250 #define CONTROL_CONF_MMC0_DAT3 (0x000008F0) 251 #define CONTROL_CONF_MMC0_DAT2 (0x000008F4) 252 #define CONTROL_CONF_MMC0_DAT1 (0x000008F8) 253 #define CONTROL_CONF_MMC0_DAT0 (0x000008FC) 254 #define CONTROL_CONF_MMC0_CLK (0x00000900) 255 #define CONTROL_CONF_MMC0_CMD (0x00000904) 256 #define CONTROL_CONF_MII1_COL (0x00000908) 257 #define CONTROL_CONF_MII1_CRS (0x0000090C) 258 #define CONTROL_CONF_MII1_RX_ER (0x00000910) 259 #define CONTROL_CONF_MII1_TX_EN (0x00000914) 260 #define CONTROL_CONF_MII1_RX_DV (0x00000918) 261 #define CONTROL_CONF_MII1_TXD3 (0x0000091C) 262 #define CONTROL_CONF_MII1_TXD2 (0x00000920) 263 #define CONTROL_CONF_MII1_TXD1 (0x00000924) 264 #define CONTROL_CONF_MII1_TXD0 (0x00000928) 265 #define CONTROL_CONF_MII1_TX_CLK (0x0000092C) 266 #define CONTROL_CONF_MII1_RX_CLK (0x00000930) 267 #define CONTROL_CONF_MII1_RXD3 (0x00000934) 268 #define CONTROL_CONF_MII1_RXD2 (0x00000938) 269 #define CONTROL_CONF_MII1_RXD1 (0x0000093C) 270 #define CONTROL_CONF_MII1_RXD0 (0x00000940) 271 #define CONTROL_CONF_RMII1_REF_CLK (0x00000944) 272 #define CONTROL_CONF_MDIO (0x00000948) 273 #define CONTROL_CONF_MDC (0x0000094C) 274 #define CONTROL_CONF_SPI0_SCLK (0x00000950) 275 #define CONTROL_CONF_SPI0_D0 (0x00000954) 276 #define CONTROL_CONF_SPI0_D1 (0x00000958) 277 #define CONTROL_CONF_SPI0_CS0 (0x0000095C) 278 #define CONTROL_CONF_SPI0_CS1 (0x00000960) 279 #define CONTROL_CONF_ECAP0_IN_PWM0_OUT (0x00000964) 280 #define CONTROL_CONF_UART0_CTSN (0x00000968) 281 #define CONTROL_CONF_UART0_RTSN (0x0000096C) 282 #define CONTROL_CONF_UART0_RXD (0x00000970) 283 #define CONTROL_CONF_UART0_TXD (0x00000974) 284 #define CONTROL_CONF_UART1_CTSN (0x00000978) 285 #define CONTROL_CONF_UART1_RTSN (0x0000097C) 286 #define CONTROL_CONF_UART1_RXD (0x00000980) 287 #define CONTROL_CONF_UART1_TXD (0x00000984) 288 #define CONTROL_CONF_I2C0_SDA (0x00000988) 289 #define CONTROL_CONF_I2C0_SCL (0x0000098C) 290 #define CONTROL_CONF_MCASP0_ACLKX (0x00000990) 291 #define CONTROL_CONF_MCASP0_FSX (0x00000994) 292 #define CONTROL_CONF_MCASP0_AXR0 (0x00000998) 293 #define CONTROL_CONF_MCASP0_AHCLKR (0x0000099C) 294 #define CONTROL_CONF_MCASP0_ACLKR (0x000009A0) 295 #define CONTROL_CONF_MCASP0_FSR (0x000009A4) 296 #define CONTROL_CONF_MCASP0_AXR1 (0x000009A8) 297 #define CONTROL_CONF_MCASP0_AHCLKX (0x000009AC) 298 #define CONTROL_CONF_XDMA_EVENT_INTR0 (0x000009B0) 299 #define CONTROL_CONF_XDMA_EVENT_INTR1 (0x000009B4) 300 #define CONTROL_CONF_WARMRSTN (0x000009B8) 301 #define CONTROL_CONF_NNMI (0x000009C0) 302 #define CONTROL_CONF_TMS (0x000009D0) 303 #define CONTROL_CONF_TDI (0x000009D4) 304 #define CONTROL_CONF_TDO (0x000009D8) 305 #define CONTROL_CONF_TCK (0x000009DC) 306 #define CONTROL_CONF_TRSTN (0x000009E0) 307 #define CONTROL_CONF_EMU0 (0x000009E4) 308 #define CONTROL_CONF_EMU1 (0x000009E8) 309 #define CONTROL_CONF_RTC_PWRONRSTN (0x000009F8) 310 #define CONTROL_CONF_PMIC_POWER_EN (0x000009FC) 311 #define CONTROL_CONF_EXT_WAKEUP (0x00000A00) 312 #define CONTROL_CONF_RTC_KALDO_ENN (0x00000A04) 313 #define CONTROL_CONF_USB0_DRVVBUS (0x00000A1C) 314 #define CONTROL_CONF_USB1_DRVVBUS (0x00000A34) 315 316 #define CONTROL_CONF_SLEWCTRL (1<<6) 317 #define CONTROL_CONF_RXACTIVE (1<<5) 318 #define CONTROL_CONF_PUTYPESEL (1<<4) 319 #define CONTROL_CONF_PUDEN (1<<3) 320 #define CONTROL_CONF_MUXMODE(X) (X&0x7) 321 322 #endif /* __MINIX_PADCONF_H */ 323