1 /* $NetBSD: mesongx_mmc.c,v 1.16 2021/08/07 16:18:43 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.16 2021/08/07 16:18:43 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/bitops.h>
39 #include <sys/gpio.h>
40
41 #include <dev/sdmmc/sdmmcvar.h>
42 #include <dev/sdmmc/sdmmcchip.h>
43 #include <dev/sdmmc/sdmmc_ioreg.h>
44
45 #include <dev/fdt/fdtvar.h>
46
47 #define SD_EMMC_CLOCK 0x00
48 #define CLOCK_CFG_V2_IRQ_SDIO_SLEEP __BIT(25)
49 #define CLOCK_CFG_V2_ALWAYS_ON __BIT(24)
50 #define CLOCK_CFG_V2_RX_DELAY __BITS(23,20)
51 #define CLOCK_CFG_V2_TX_DELAY __BITS(19,16)
52 #define CLOCK_CFG_V3_IRQ_SDIO_SLEEP __BIT(29)
53 #define CLOCK_CFG_V3_ALWAYS_ON __BIT(28)
54 #define CLOCK_CFG_V3_RX_DELAY __BITS(27,22)
55 #define CLOCK_CFG_V3_TX_DELAY __BITS(21,16)
56 #define CLOCK_CFG_SRAM_PD __BITS(15,14)
57 #define CLOCK_CFG_RX_PHASE __BITS(13,12)
58 #define CLOCK_CFG_TX_PHASE __BITS(11,10)
59 #define CLOCK_CFG_CO_PHASE __BITS(9,8)
60 #define CLOCK_CFG_SRC __BITS(7,6)
61 #define CLOCK_CFG_DIV __BITS(5,0)
62 #define SD_EMMC_DELAY 0x04
63 #define SD_EMMC_ADJUST 0x08 /* V2 */
64 #define ADJUST_ADJ_DELAY __BITS(21,16)
65 #define ADJUST_CALI_RISE __BIT(14)
66 #define ADJUST_ADJ_ENABLE __BIT(13)
67 #define ADJUST_CALI_ENABLE __BIT(12)
68 #define ADJUST_CALI_SEL __BITS(11,8)
69 #define SD_EMMC_CALOUT 0x10
70 #define CALOUT_CALI_SETUP __BITS(15,8)
71 #define CALOUT_CALI_VLD __BIT(7)
72 #define CALOUT_CALI_IDX __BITS(5,0)
73 #define SD_EMMC_V3_ADJUST 0x0c
74 #define SD_EMMC_START 0x40
75 #define START_DESC_ADDR __BITS(31,2)
76 #define START_DESC_BUSY __BIT(1)
77 #define START_DESC_INT __BIT(0)
78 #define SD_EMMC_CFG 0x44
79 #define CFG_IP_TXD_ADJ __BITS(31,28)
80 #define CFG_ERR_ABORT __BIT(27)
81 #define CFG_IRQ_DS __BIT(26)
82 #define CFG_TXD_RETRY __BIT(25)
83 #define CFG_TXD_ADD_ERR __BIT(24)
84 #define CFG_AUTO_CLK __BIT(23)
85 #define CFG_STOP_CLK __BIT(22)
86 #define CFG_CMD_LOW __BIT(21)
87 #define CFG_CHK_DS __BIT(20)
88 #define CFG_IGNORE_OWNER __BIT(19)
89 #define CFG_SDCLK_ALWAYS_ON __BIT(18)
90 #define CFG_BLK_GAP_IP __BIT(17)
91 #define CFG_OUT_FALL __BIT(16)
92 #define CFG_RC_CC __BITS(15,12)
93 #define CFG_RESP_TIMEOUT __BIT(11,8)
94 #define CFG_BL_LEN __BITS(7,4)
95 #define CFG_DC_UGT __BIT(3)
96 #define CFG_DDR __BIT(2)
97 #define CFG_BUS_WIDTH __BITS(1,0)
98 #define CFG_BUS_WIDTH_1 0
99 #define CFG_BUS_WIDTH_4 1
100 #define CFG_BUS_WIDTH_8 2
101 #define SD_EMMC_STATUS 0x48
102 #define STATUS_CORE_BUSY __BIT(31)
103 #define STATUS_DESC_BUSY __BIT(30)
104 #define STATUS_BUS_FSM __BIT(29,26)
105 #define STATUS_DS __BIT(25)
106 #define STATUS_CMD_I __BIT(24)
107 #define STATUS_DAT_I __BITS(23,16)
108 #define STATUS_IRQ_SDIO __BIT(15)
109 #define STATUS_RESP_STATUS __BIT(14)
110 #define STATUS_END_OF_CHAIN __BIT(13)
111 #define STATUS_DESC_TIMEOUT __BIT(12)
112 #define STATUS_RESP_TIMEOUT __BIT(11)
113 #define STATUS_RESP_ERR __BIT(10)
114 #define STATUS_DESC_ERR __BIT(9)
115 #define STATUS_TXD_ERR __BIT(8)
116 #define STATUS_RXD_ERR __BITS(7,0)
117 #define STATUS_TIMEOUT (STATUS_DESC_TIMEOUT | STATUS_RESP_TIMEOUT)
118 #define STATUS_ERROR (STATUS_RESP_ERR | STATUS_DESC_ERR | STATUS_RXD_ERR | STATUS_TXD_ERR)
119 #define SD_EMMC_IRQ_EN 0x4c
120 #define IRQ_EN_CFG_SECURE __BIT(16)
121 #define IRQ_EN_IRQ_SDIO __BIT(15)
122 #define IRQ_EN_RESP_STATUS __BIT(14)
123 #define IRQ_EN_END_OF_CHAIN __BIT(13)
124 #define IRQ_EN_DESC_TIMEOUT __BIT(12)
125 #define IRQ_EN_RESP_TIMEOUT __BIT(11)
126 #define IRQ_EN_RESP_ERR __BIT(10)
127 #define IRQ_EN_DESC_ERR __BIT(9)
128 #define IRQ_EN_TXD_ERR __BIT(8)
129 #define IRQ_EN_RXD_ERR __BITS(7,0)
130 #define SD_EMMC_CMD_CFG 0x50
131 #define SD_EMMC_CMD_ARG 0x54
132 #define SD_EMMC_CMD_DAT 0x58
133 #define SD_EMMC_CMD_RSP 0x5c
134 #define SD_EMMC_CMD_RSP1 0x60
135 #define SD_EMMC_CMD_RSP2 0x64
136 #define SD_EMMC_CMD_RSP3 0x68
137
138 struct mesongx_mmc_desc {
139 uint32_t flags;
140 #define MESONGX_MMC_FLAGS_OWNER __BIT(31)
141 #define MESONGX_MMC_FLAGS_ERROR __BIT(30)
142 #define MESONGX_MMC_FLAGS_CMD_INDEX __BITS(29,24)
143 #define MESONGX_MMC_FLAGS_DATA_NUM __BIT(23)
144 #define MESONGX_MMC_FLAGS_RESP_NUM __BIT(22)
145 #define MESONGX_MMC_FLAGS_RESP_128 __BIT(21)
146 #define MESONGX_MMC_FLAGS_RESP_NOCRC __BIT(20)
147 #define MESONGX_MMC_FLAGS_DATA_WR __BIT(19)
148 #define MESONGX_MMC_FLAGS_DATA_IO __BIT(18)
149 #define MESONGX_MMC_FLAGS_NO_CMD __BIT(17)
150 #define MESONGX_MMC_FLAGS_NO_RESP __BIT(16)
151 #define MESONGX_MMC_FLAGS_TIMEOUT __BITS(15,12)
152 #define MESONGX_MMC_FLAGS_END_OF_CHAIN __BIT(11)
153 #define MESONGX_MMC_FLAGS_R1B __BIT(10)
154 #define MESONGX_MMC_FLAGS_BLOCK_MODE __BIT(9)
155 #define MESONGX_MMC_FLAGS_LENGTH __BITS(8,0)
156 uint32_t arg;
157 uint32_t data;
158 #define MESONGX_MMC_DATA_BIG_ENDIAN __BIT(1)
159 #define MESONGX_MMC_DATA_SRAM __BIT(0)
160 uint32_t resp;
161 #define MESONGX_MMC_RESP_SRAM __BIT(0)
162 } __packed;
163
164 #define MESONGX_MMC_NDESC 256
165
166 struct mesongx_mmc_softc;
167
168 static int mesongx_mmc_match(device_t, cfdata_t, void *);
169 static void mesongx_mmc_attach(device_t, device_t, void *);
170 static void mesongx_mmc_attach_i(device_t);
171
172 static int mesongx_mmc_intr(void *);
173 static int mesongx_mmc_dma_setup(struct mesongx_mmc_softc *);
174 static int mesongx_mmc_dmabounce_setup(struct mesongx_mmc_softc *);
175
176 static int mesongx_mmc_host_reset(sdmmc_chipset_handle_t);
177 static uint32_t mesongx_mmc_host_ocr(sdmmc_chipset_handle_t);
178 static int mesongx_mmc_host_maxblklen(sdmmc_chipset_handle_t);
179 static int mesongx_mmc_card_detect(sdmmc_chipset_handle_t);
180 static int mesongx_mmc_write_protect(sdmmc_chipset_handle_t);
181 static int mesongx_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
182 static int mesongx_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool);
183 static int mesongx_mmc_bus_width(sdmmc_chipset_handle_t, int);
184 static int mesongx_mmc_bus_rod(sdmmc_chipset_handle_t, int);
185 static int mesongx_mmc_signal_voltage(sdmmc_chipset_handle_t, int);
186 static int mesongx_mmc_execute_tuning(sdmmc_chipset_handle_t, int);
187 static void mesongx_mmc_exec_command(sdmmc_chipset_handle_t,
188 struct sdmmc_command *);
189 static void mesongx_mmc_card_enable_intr(sdmmc_chipset_handle_t, int);
190 static void mesongx_mmc_card_intr_ack(sdmmc_chipset_handle_t);
191
192 static struct sdmmc_chip_functions mesongx_mmc_chip_functions = {
193 .host_reset = mesongx_mmc_host_reset,
194 .host_ocr = mesongx_mmc_host_ocr,
195 .host_maxblklen = mesongx_mmc_host_maxblklen,
196 .card_detect = mesongx_mmc_card_detect,
197 .write_protect = mesongx_mmc_write_protect,
198 .bus_power = mesongx_mmc_bus_power,
199 .bus_clock_ddr = mesongx_mmc_bus_clock,
200 .bus_width = mesongx_mmc_bus_width,
201 .bus_rod = mesongx_mmc_bus_rod,
202 .signal_voltage = mesongx_mmc_signal_voltage,
203 .execute_tuning = mesongx_mmc_execute_tuning,
204 .exec_command = mesongx_mmc_exec_command,
205 .card_enable_intr = mesongx_mmc_card_enable_intr,
206 .card_intr_ack = mesongx_mmc_card_intr_ack,
207 };
208
209 struct mesongx_mmc_softc {
210 device_t sc_dev;
211 bus_space_tag_t sc_bst;
212 bus_space_handle_t sc_bsh;
213 bus_dma_tag_t sc_dmat;
214 int sc_phandle;
215
216 void *sc_ih;
217 kmutex_t sc_intr_lock;
218 kcondvar_t sc_intr_cv;
219
220 device_t sc_sdmmc_dev;
221 uint32_t sc_host_ocr;
222 int sc_hwtype;
223
224 struct sdmmc_command *sc_cmd;
225
226 bus_dma_segment_t sc_desc_segs[1];
227 int sc_desc_nsegs;
228 bus_size_t sc_desc_size;
229 bus_dmamap_t sc_desc_map;
230 int sc_desc_ndesc;
231 void *sc_desc_desc;
232
233 bus_dmamap_t sc_dmabounce_map;
234 void *sc_dmabounce_buf;
235 size_t sc_dmabounce_buflen;
236
237 struct clk *sc_clk_core;
238 struct clk *sc_clk_clkin[2];
239
240 struct fdtbus_reset *sc_rst;
241
242 struct fdtbus_gpio_pin *sc_gpio_cd;
243 int sc_gpio_cd_inverted;
244 struct fdtbus_gpio_pin *sc_gpio_wp;
245 int sc_gpio_wp_inverted;
246
247 struct fdtbus_regulator *sc_reg_vmmc;
248 struct fdtbus_regulator *sc_reg_vqmmc;
249
250 struct fdtbus_mmc_pwrseq *sc_pwrseq;
251
252 u_int sc_max_frequency;
253 bool sc_non_removable;
254 bool sc_broken_cd;
255 };
256
257 CFATTACH_DECL_NEW(mesongx_mmc, sizeof(struct mesongx_mmc_softc),
258 mesongx_mmc_match, mesongx_mmc_attach, NULL, NULL);
259
260 #define MMC_WRITE(sc, reg, val) \
261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
262 #define MMC_READ(sc, reg) \
263 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
264
265 enum {
266 MESONGX_MMC_V2 = 2,
267 MESONGX_MMC_V3 = 3,
268 };
269
270 static const struct device_compatible_entry compat_data[] = {
271 { .compat = "amlogic,meson-gx-mmc", .value = MESONGX_MMC_V2 },
272 { .compat = "amlogic,meson-gxbb-mmc", .value = MESONGX_MMC_V2 },
273 { .compat = "amlogic,meson-axg-mmc", .value = MESONGX_MMC_V3 },
274 DEVICE_COMPAT_EOL
275 };
276
277 static int
mesongx_mmc_match(device_t parent,cfdata_t cf,void * aux)278 mesongx_mmc_match(device_t parent, cfdata_t cf, void *aux)
279 {
280 struct fdt_attach_args * const faa = aux;
281
282 return of_compatible_match(faa->faa_phandle, compat_data);
283 }
284
285 static void
mesongx_mmc_attach(device_t parent,device_t self,void * aux)286 mesongx_mmc_attach(device_t parent, device_t self, void *aux)
287 {
288 struct mesongx_mmc_softc * const sc = device_private(self);
289 struct fdt_attach_args * const faa = aux;
290 const int phandle = faa->faa_phandle;
291 char intrstr[128];
292 bus_addr_t addr;
293 bus_size_t size;
294
295 sc->sc_hwtype = of_compatible_lookup(phandle, compat_data)->value;
296
297 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
298 aprint_error(": couldn't get registers\n");
299 return;
300 }
301
302 sc->sc_clk_core = fdtbus_clock_get(phandle, "core");
303 sc->sc_clk_clkin[0] = fdtbus_clock_get(phandle, "clkin0");
304 sc->sc_clk_clkin[1] = fdtbus_clock_get(phandle, "clkin1");
305
306 if (sc->sc_clk_core == NULL || sc->sc_clk_clkin[0] == NULL ||
307 sc->sc_clk_clkin[1] == NULL) {
308 aprint_error(": couldn't get clocks\n");
309 return;
310 }
311
312 sc->sc_rst = fdtbus_reset_get_index(phandle, 0);
313 if (sc->sc_rst == NULL) {
314 aprint_error(": couldn't get reset\n");
315 return;
316 }
317
318 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle);
319
320 if (clk_enable(sc->sc_clk_core) != 0) {
321 aprint_error(": couldn't enable core clock\n");
322 return;
323 }
324 if (clk_enable(sc->sc_clk_clkin[0]) != 0 ||
325 clk_enable(sc->sc_clk_clkin[1]) != 0) {
326 aprint_error(": couldn't enable clkin clocks\n");
327 return;
328 }
329
330 if (fdtbus_reset_deassert(sc->sc_rst) != 0) {
331 aprint_error(": couldn't de-assert reset\n");
332 return;
333 }
334
335 sc->sc_dev = self;
336 sc->sc_phandle = phandle;
337 sc->sc_bst = faa->faa_bst;
338 sc->sc_dmat = faa->faa_dmat;
339 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
340 cv_init(&sc->sc_intr_cv, "gxmmcirq");
341
342 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
343 aprint_error(": couldn't map registers\n");
344 return;
345 }
346
347 aprint_naive("\n");
348 aprint_normal(": eMMC/SD/SDIO controller\n");
349
350 sc->sc_reg_vmmc = fdtbus_regulator_acquire(phandle, "vmmc-supply");
351 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply");
352
353 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios",
354 GPIO_PIN_INPUT);
355 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios",
356 GPIO_PIN_INPUT);
357
358 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 1 : 0;
359 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 1 : 0;
360
361 sc->sc_non_removable = of_hasprop(phandle, "non-removable");
362 sc->sc_broken_cd = of_hasprop(phandle, "broken-cd");
363
364 if (of_getprop_uint32(phandle, "max-frequency", &sc->sc_max_frequency))
365 sc->sc_max_frequency = 52000000;
366
367 if (mesongx_mmc_dma_setup(sc) != 0 ||
368 mesongx_mmc_dmabounce_setup(sc) != 0) {
369 aprint_error_dev(self, "failed to setup DMA\n");
370 return;
371 }
372
373 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
374 aprint_error_dev(self, "failed to decode interrupt\n");
375 return;
376 }
377
378 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_BIO,
379 FDT_INTR_MPSAFE, mesongx_mmc_intr, sc, device_xname(self));
380 if (sc->sc_ih == NULL) {
381 aprint_error_dev(self, "failed to establish interrupt on %s\n",
382 intrstr);
383 return;
384 }
385 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
386
387 if (sc->sc_pwrseq)
388 fdtbus_mmc_pwrseq_reset(sc->sc_pwrseq);
389
390 config_interrupts(self, mesongx_mmc_attach_i);
391 }
392
393 static int
mesongx_mmc_dma_setup(struct mesongx_mmc_softc * sc)394 mesongx_mmc_dma_setup(struct mesongx_mmc_softc *sc)
395 {
396 int error;
397
398 sc->sc_desc_ndesc = MESONGX_MMC_NDESC;
399 sc->sc_desc_size = sizeof(struct mesongx_mmc_desc) *
400 sc->sc_desc_ndesc;
401 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_desc_size,
402 sizeof(struct mesongx_mmc_desc),
403 sc->sc_desc_size, sc->sc_desc_segs, 1,
404 &sc->sc_desc_nsegs, BUS_DMA_WAITOK);
405 if (error)
406 return error;
407 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs,
408 sc->sc_desc_nsegs, sc->sc_desc_size,
409 &sc->sc_desc_desc, BUS_DMA_WAITOK);
410 if (error)
411 goto free;
412 error = bus_dmamap_create(sc->sc_dmat, sc->sc_desc_size, 1,
413 sc->sc_desc_size, 0, BUS_DMA_WAITOK, &sc->sc_desc_map);
414 if (error)
415 goto unmap;
416 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map,
417 sc->sc_desc_desc, sc->sc_desc_size, NULL, BUS_DMA_WAITOK);
418 if (error)
419 goto destroy;
420 return 0;
421
422 destroy:
423 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map);
424 unmap:
425 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc_desc, sc->sc_desc_size);
426 free:
427 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, sc->sc_desc_nsegs);
428 return error;
429 }
430
431 static int
mesongx_mmc_dmabounce_setup(struct mesongx_mmc_softc * sc)432 mesongx_mmc_dmabounce_setup(struct mesongx_mmc_softc *sc)
433 {
434 bus_dma_segment_t ds[1];
435 int error, rseg;
436
437 sc->sc_dmabounce_buflen = MAXPHYS;
438 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0,
439 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK);
440 if (error)
441 return error;
442 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen,
443 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK);
444 if (error)
445 goto free;
446 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1,
447 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map);
448 if (error)
449 goto unmap;
450 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map,
451 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL,
452 BUS_DMA_WAITOK);
453 if (error)
454 goto destroy;
455 return 0;
456
457 destroy:
458 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map);
459 unmap:
460 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf,
461 sc->sc_dmabounce_buflen);
462 free:
463 bus_dmamem_free(sc->sc_dmat, ds, rseg);
464 return error;
465 }
466
467 static int
mesongx_mmc_set_clock(struct mesongx_mmc_softc * sc,u_int freq,bool ddr)468 mesongx_mmc_set_clock(struct mesongx_mmc_softc *sc, u_int freq, bool ddr)
469 {
470 int best_diff, best_sel, best_div, sel, div;
471 uint32_t val;
472
473 if (freq == 0)
474 freq = SDMMC_SDCLK_400K;
475
476 best_diff = INT_MAX;
477 best_sel = 0;
478 best_div = 0;
479
480 const u_int target_rate = (freq * 1000) << ddr;
481 for (sel = 0; sel <= 1; sel++) {
482 const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]);
483 for (div = 1; div <= 63; div++) {
484 const u_int rate = parent_rate / div;
485 if (rate > target_rate)
486 continue;
487 const int diff = target_rate - rate;
488 if (diff < best_diff) {
489 best_diff = diff;
490 best_sel = sel;
491 best_div = div;
492 }
493 }
494 }
495
496 if (best_diff == INT_MAX)
497 return ERANGE;
498
499 val = MMC_READ(sc, SD_EMMC_CFG);
500 val |= CFG_STOP_CLK;
501 MMC_WRITE(sc, SD_EMMC_CFG, val);
502
503 val = MMC_READ(sc, SD_EMMC_CFG);
504 if (ddr)
505 val |= CFG_DDR;
506 else
507 val &= ~CFG_DDR;
508 MMC_WRITE(sc, SD_EMMC_CFG, val);
509
510 val = MMC_READ(sc, SD_EMMC_CLOCK);
511 if (sc->sc_hwtype == MESONGX_MMC_V3)
512 val |= CLOCK_CFG_V3_ALWAYS_ON;
513 else
514 val |= CLOCK_CFG_V2_ALWAYS_ON;
515 val &= ~CLOCK_CFG_RX_PHASE;
516 val |= __SHIFTIN(0, CLOCK_CFG_RX_PHASE);
517 val &= ~CLOCK_CFG_TX_PHASE;
518 val |= __SHIFTIN(0, CLOCK_CFG_TX_PHASE);
519 val &= ~CLOCK_CFG_CO_PHASE;
520 val |= __SHIFTIN(2, CLOCK_CFG_CO_PHASE);
521 val &= ~CLOCK_CFG_SRC;
522 val |= __SHIFTIN(best_sel, CLOCK_CFG_SRC);
523 val &= ~CLOCK_CFG_DIV;
524 val |= __SHIFTIN(best_div, CLOCK_CFG_DIV);
525 MMC_WRITE(sc, SD_EMMC_CLOCK, val);
526
527 val = MMC_READ(sc, SD_EMMC_CFG);
528 val &= ~CFG_STOP_CLK;
529 MMC_WRITE(sc, SD_EMMC_CFG, val);
530
531 return 0;
532 }
533
534 static void
mesongx_mmc_attach_i(device_t self)535 mesongx_mmc_attach_i(device_t self)
536 {
537 struct mesongx_mmc_softc * const sc = device_private(self);
538 struct sdmmcbus_attach_args saa;
539 uint32_t width;
540
541 if (sc->sc_pwrseq)
542 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq);
543
544 mesongx_mmc_bus_clock(sc, SDMMC_SDCLK_400K, false);
545 mesongx_mmc_host_reset(sc);
546 mesongx_mmc_bus_width(sc, 1);
547
548 if (sc->sc_pwrseq)
549 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq);
550
551 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0)
552 width = 4;
553
554 memset(&saa, 0, sizeof(saa));
555 saa.saa_busname = "sdmmc";
556 saa.saa_sct = &mesongx_mmc_chip_functions;
557 saa.saa_sch = sc;
558 saa.saa_dmat = sc->sc_dmat;
559 saa.saa_clkmin = SDMMC_SDCLK_400K;
560 saa.saa_clkmax = sc->sc_max_frequency / 1000;
561 saa.saa_caps = SMC_CAPS_DMA;
562 #if notyet
563 /* XXX causes init to die when using root on eMMC with ODROID-C2 */
564 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA;
565 #endif
566
567 sc->sc_host_ocr = MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
568
569 if (of_getprop_bool(sc->sc_phandle, "cap-sd-highspeed")) {
570 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED;
571 sc->sc_host_ocr |= MMC_OCR_HCS;
572 }
573 if (of_getprop_bool(sc->sc_phandle, "cap-mmc-highspeed"))
574 saa.saa_caps |= SMC_CAPS_MMC_HIGHSPEED;
575
576 if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-3_3v")) {
577 saa.saa_caps |= SMC_CAPS_MMC_DDR52;
578 }
579
580 if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-1_8v")) {
581 saa.saa_caps |= SMC_CAPS_MMC_DDR52;
582 sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V;
583 }
584 if (of_getprop_bool(sc->sc_phandle, "mmc-hs200-1_8v")) {
585 saa.saa_caps |= SMC_CAPS_MMC_HS200;
586 sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V;
587 }
588
589 if (width == 4)
590 saa.saa_caps |= SMC_CAPS_4BIT_MODE;
591 if (width == 8)
592 saa.saa_caps |= SMC_CAPS_8BIT_MODE;
593
594 if (sc->sc_gpio_cd)
595 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET;
596
597 sc->sc_sdmmc_dev = config_found(self, &saa, NULL, CFARGS_NONE);
598 }
599
600 static int
mesongx_mmc_intr(void * priv)601 mesongx_mmc_intr(void *priv)
602 {
603 struct mesongx_mmc_softc * const sc = priv;
604 struct sdmmc_command *cmd;
605 int rv = 0;
606
607 mutex_enter(&sc->sc_intr_lock);
608
609 const uint32_t irq_en = MMC_READ(sc, SD_EMMC_IRQ_EN);
610 const uint32_t status = MMC_READ(sc, SD_EMMC_STATUS) & irq_en;
611
612 if ((status & STATUS_IRQ_SDIO) != 0) {
613 rv = 1;
614 sdmmc_card_intr(sc->sc_sdmmc_dev);
615 }
616
617 cmd = sc->sc_cmd;
618 if (cmd == NULL) {
619 device_printf(sc->sc_dev, "WARNING: IRQ with no active command, status %#x\n", status);
620 goto done;
621 }
622
623 if ((status & STATUS_TIMEOUT) != 0) {
624 rv = 1;
625 cmd->c_error = ETIMEDOUT;
626 goto done;
627 }
628
629 if ((status & STATUS_ERROR) != 0) {
630 rv = 1;
631 cmd->c_error = EIO;
632 goto done;
633 }
634
635 if ((status & STATUS_END_OF_CHAIN) != 0 && (cmd->c_flags & SCF_ITSDONE) == 0) {
636 rv = 1;
637 if ((cmd->c_flags & SCF_RSP_PRESENT) != 0) {
638 if (cmd->c_flags & SCF_RSP_136) {
639 cmd->c_resp[0] = MMC_READ(sc, SD_EMMC_CMD_RSP);
640 cmd->c_resp[1] = MMC_READ(sc, SD_EMMC_CMD_RSP1);
641 cmd->c_resp[2] = MMC_READ(sc, SD_EMMC_CMD_RSP2);
642 cmd->c_resp[3] = MMC_READ(sc, SD_EMMC_CMD_RSP3);
643 if (cmd->c_flags & SCF_RSP_CRC) {
644 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
645 (cmd->c_resp[1] << 24);
646 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
647 (cmd->c_resp[2] << 24);
648 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
649 (cmd->c_resp[3] << 24);
650 cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
651 }
652 } else {
653 cmd->c_resp[0] = MMC_READ(sc, SD_EMMC_CMD_RSP);
654 }
655 }
656 cmd->c_flags |= SCF_ITSDONE;
657 cmd->c_error = 0;
658 goto done;
659 }
660
661 done:
662 if (rv) {
663 cv_broadcast(&sc->sc_intr_cv);
664 MMC_WRITE(sc, SD_EMMC_STATUS, irq_en);
665 }
666
667 mutex_exit(&sc->sc_intr_lock);
668
669 return rv;
670 }
671
672 static int
mesongx_mmc_host_reset(sdmmc_chipset_handle_t sch)673 mesongx_mmc_host_reset(sdmmc_chipset_handle_t sch)
674 {
675 struct mesongx_mmc_softc * const sc = sch;
676 uint32_t val;
677
678 MMC_WRITE(sc, SD_EMMC_START, 0);
679
680 val = MMC_READ(sc, SD_EMMC_CFG);
681 val &= ~CFG_RC_CC;
682 val |= __SHIFTIN(ilog2(16), CFG_RC_CC);
683 val |= CFG_SDCLK_ALWAYS_ON;
684 MMC_WRITE(sc, SD_EMMC_CFG, val);
685
686 return 0;
687 }
688
689 static uint32_t
mesongx_mmc_host_ocr(sdmmc_chipset_handle_t sch)690 mesongx_mmc_host_ocr(sdmmc_chipset_handle_t sch)
691 {
692 struct mesongx_mmc_softc * const sc = sch;
693
694 return sc->sc_host_ocr;
695 }
696
697 static int
mesongx_mmc_host_maxblklen(sdmmc_chipset_handle_t sch)698 mesongx_mmc_host_maxblklen(sdmmc_chipset_handle_t sch)
699 {
700 return 512;
701 }
702
703 static int
mesongx_mmc_card_detect(sdmmc_chipset_handle_t sch)704 mesongx_mmc_card_detect(sdmmc_chipset_handle_t sch)
705 {
706 struct mesongx_mmc_softc * const sc = sch;
707 int val;
708
709 if (sc->sc_non_removable || sc->sc_broken_cd) {
710 /*
711 * Non-removable or broken card detect flag set in
712 * DT, assume always present
713 */
714 return 1;
715 } else if (sc->sc_gpio_cd != NULL) {
716 val = fdtbus_gpio_read(sc->sc_gpio_cd);
717 if (sc->sc_gpio_cd_inverted)
718 val = !val;
719 return val;
720 } else {
721 return 1;
722 }
723 }
724
725 static int
mesongx_mmc_write_protect(sdmmc_chipset_handle_t sch)726 mesongx_mmc_write_protect(sdmmc_chipset_handle_t sch)
727 {
728 struct mesongx_mmc_softc * const sc = sch;
729 int val;
730
731 if (sc->sc_gpio_wp != NULL) {
732 val = fdtbus_gpio_read(sc->sc_gpio_wp);
733 if (sc->sc_gpio_wp_inverted)
734 val = !val;
735 return val;
736 }
737
738 return 0;
739 }
740
741 static int
mesongx_mmc_bus_power(sdmmc_chipset_handle_t sch,uint32_t ocr)742 mesongx_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
743 {
744 return 0;
745 }
746
747 static int
mesongx_mmc_bus_clock(sdmmc_chipset_handle_t sch,int freq,bool ddr)748 mesongx_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr)
749 {
750 struct mesongx_mmc_softc * const sc = sch;
751
752 return mesongx_mmc_set_clock(sc, freq, ddr);
753 }
754
755 static int
mesongx_mmc_bus_width(sdmmc_chipset_handle_t sch,int width)756 mesongx_mmc_bus_width(sdmmc_chipset_handle_t sch, int width)
757 {
758 struct mesongx_mmc_softc *sc = sch;
759 uint32_t val;
760
761 val = MMC_READ(sc, SD_EMMC_CFG);
762 val &= ~CFG_BUS_WIDTH;
763
764 switch (width) {
765 case 1:
766 val |= __SHIFTIN(CFG_BUS_WIDTH_1, CFG_BUS_WIDTH);
767 break;
768 case 4:
769 val |= __SHIFTIN(CFG_BUS_WIDTH_4, CFG_BUS_WIDTH);
770 break;
771 case 8:
772 val |= __SHIFTIN(CFG_BUS_WIDTH_8, CFG_BUS_WIDTH);
773 break;
774 default:
775 return EINVAL;
776 }
777
778 MMC_WRITE(sc, SD_EMMC_CFG, val);
779
780 return 0;
781 }
782
783 static int
mesongx_mmc_bus_rod(sdmmc_chipset_handle_t sch,int on)784 mesongx_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
785 {
786 return -1;
787 }
788
789 static int
mesongx_mmc_signal_voltage(sdmmc_chipset_handle_t sch,int signal_voltage)790 mesongx_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage)
791 {
792 struct mesongx_mmc_softc *sc = sch;
793 u_int uvol;
794 int error;
795
796 if (sc->sc_reg_vqmmc == NULL)
797 return 0;
798
799 switch (signal_voltage) {
800 case SDMMC_SIGNAL_VOLTAGE_330:
801 uvol = 3300000;
802 break;
803 case SDMMC_SIGNAL_VOLTAGE_180:
804 uvol = 1800000;
805 break;
806 default:
807 return EINVAL;
808 }
809
810 error = fdtbus_regulator_supports_voltage(sc->sc_reg_vqmmc, uvol, uvol);
811 if (error != 0)
812 return 0;
813
814 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol);
815 if (error != 0)
816 return error;
817
818 return fdtbus_regulator_enable(sc->sc_reg_vqmmc);
819 }
820
821 static int
mesongx_mmc_execute_tuning(sdmmc_chipset_handle_t sch,int timing)822 mesongx_mmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing)
823 {
824 switch (timing) {
825 case SDMMC_TIMING_MMC_HS200:
826 break;
827 default:
828 return EINVAL;
829 }
830
831 return 0;
832 }
833
834 static int
mesongx_mmc_dma_prepare(struct mesongx_mmc_softc * sc,struct sdmmc_command * cmd,uint32_t cmdflags)835 mesongx_mmc_dma_prepare(struct mesongx_mmc_softc *sc, struct sdmmc_command *cmd, uint32_t cmdflags)
836 {
837 struct mesongx_mmc_desc *dma = sc->sc_desc_desc;
838 bus_dmamap_t map = cmd->c_dmamap;
839 u_int xferlen, blen, resid;
840 bus_size_t off;
841 uint32_t flags;
842 int desc, seg;
843
844 if (cmd->c_blklen > 512) {
845 device_printf(sc->sc_dev, "block length %d not supported\n", cmd->c_blklen);
846 return EINVAL;
847 }
848
849 for (seg = 0; seg < map->dm_nsegs; seg++) {
850 if (map->dm_segs[seg].ds_len % cmd->c_blklen != 0) {
851 /* Force DMA bounce for unaligned transfers */
852 map = NULL;
853 break;
854 }
855 }
856
857 if (map == NULL) {
858 map = sc->sc_dmabounce_map;
859 cmd->c_flags |= SCF_NEED_BOUNCE;
860
861 if ((cmd->c_flags & SCF_CMD_READ) != 0) {
862 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen);
863 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
864 0, cmd->c_datalen, BUS_DMASYNC_PREREAD);
865 } else {
866 memcpy(sc->sc_dmabounce_buf, cmd->c_data, cmd->c_datalen);
867 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
868 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE);
869 }
870 }
871
872 desc = 0;
873 for (seg = 0; seg < map->dm_nsegs; seg++) {
874 bus_addr_t paddr = map->dm_segs[seg].ds_addr;
875 bus_size_t len = map->dm_segs[seg].ds_len;
876 resid = uimin(len, cmd->c_resid);
877 off = 0;
878 while (resid > 0) {
879 if (desc == sc->sc_desc_ndesc)
880 break;
881
882 flags = cmdflags;
883
884 if (resid >= cmd->c_blklen) {
885 xferlen = (resid / cmd->c_blklen) * cmd->c_blklen;
886 blen = xferlen / cmd->c_blklen;
887 flags |= MESONGX_MMC_FLAGS_BLOCK_MODE;
888 } else {
889 blen = xferlen = resid;
890 }
891 KASSERT(xferlen > 0);
892 KASSERT(blen <= 512);
893
894 flags |= __SHIFTIN(blen % 512, MESONGX_MMC_FLAGS_LENGTH);
895 if (desc > 0)
896 flags |= MESONGX_MMC_FLAGS_NO_CMD;
897 if (cmd->c_resid == xferlen)
898 flags |= MESONGX_MMC_FLAGS_END_OF_CHAIN;
899
900 dma[desc].flags = htole32(flags);
901 dma[desc].arg = htole32(cmd->c_arg);
902 dma[desc].data = htole32(paddr + off);
903 dma[desc].resp = 0;
904
905 cmd->c_resid -= xferlen;
906 resid -= xferlen;
907 off += xferlen;
908
909 if (cmd->c_resid == 0)
910 break;
911
912 ++desc;
913 }
914 }
915 if (desc == sc->sc_desc_ndesc) {
916 device_printf(sc->sc_dev,
917 "not enough descriptors for %d byte transfer (%d segs)!\n",
918 cmd->c_datalen, map->dm_nsegs);
919 return EIO;
920 }
921
922 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
923 sc->sc_desc_size, BUS_DMASYNC_PREWRITE);
924
925 return 0;
926 }
927
928 static void
mesongx_mmc_dma_complete(struct mesongx_mmc_softc * sc,struct sdmmc_command * cmd)929 mesongx_mmc_dma_complete(struct mesongx_mmc_softc *sc, struct sdmmc_command *cmd)
930 {
931 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0,
932 sc->sc_desc_size, BUS_DMASYNC_POSTWRITE);
933
934 if ((cmd->c_flags & SCF_NEED_BOUNCE) != 0) {
935 if ((cmd->c_flags & SCF_CMD_READ) != 0) {
936 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
937 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD);
938 memcpy(cmd->c_data, sc->sc_dmabounce_buf, cmd->c_datalen);
939 } else {
940 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
941 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE);
942 }
943 }
944 }
945
946 static void
mesongx_mmc_exec_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)947 mesongx_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
948 {
949 struct mesongx_mmc_softc *sc = sch;
950 uint32_t cmdflags, val;
951 int error;
952
953 const uint32_t irq_mask = IRQ_EN_RESP_STATUS |
954 IRQ_EN_END_OF_CHAIN |
955 IRQ_EN_DESC_TIMEOUT |
956 IRQ_EN_RESP_TIMEOUT |
957 IRQ_EN_RESP_ERR |
958 IRQ_EN_DESC_ERR |
959 IRQ_EN_TXD_ERR |
960 IRQ_EN_RXD_ERR;
961
962 mutex_enter(&sc->sc_intr_lock);
963
964 while (sc->sc_cmd != NULL)
965 cv_wait(&sc->sc_intr_cv, &sc->sc_intr_lock);
966 sc->sc_cmd = cmd;
967
968 MMC_WRITE(sc, SD_EMMC_START, 0);
969 MMC_WRITE(sc, SD_EMMC_STATUS, MMC_READ(sc, SD_EMMC_STATUS));
970
971 val = MMC_READ(sc, SD_EMMC_IRQ_EN);
972 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val | irq_mask);
973
974 cmdflags = MESONGX_MMC_FLAGS_OWNER;
975 cmdflags |= __SHIFTIN(12, MESONGX_MMC_FLAGS_TIMEOUT); /* 2^12 = 4096 ms timeout */
976 cmdflags |= __SHIFTIN(cmd->c_opcode, MESONGX_MMC_FLAGS_CMD_INDEX);
977
978 if ((cmd->c_flags & SCF_RSP_PRESENT) == 0) {
979 cmdflags |= MESONGX_MMC_FLAGS_NO_RESP;
980 } else {
981 cmdflags |= MESONGX_MMC_FLAGS_RESP_NUM;
982 if ((cmd->c_flags & SCF_RSP_136) != 0)
983 cmdflags |= MESONGX_MMC_FLAGS_RESP_128;
984 if ((cmd->c_flags & SCF_RSP_CRC) == 0)
985 cmdflags |= MESONGX_MMC_FLAGS_RESP_NOCRC;
986 if ((cmd->c_flags & SCF_RSP_MASK) == SCF_RSP_R1B)
987 cmdflags |= MESONGX_MMC_FLAGS_R1B;
988 }
989
990 if (cmd->c_datalen > 0) {
991 cmdflags |= MESONGX_MMC_FLAGS_DATA_IO;
992 if ((cmd->c_flags & SCF_CMD_READ) == 0)
993 cmdflags |= MESONGX_MMC_FLAGS_DATA_WR;
994
995 val = MMC_READ(sc, SD_EMMC_CFG);
996 val &= ~CFG_BL_LEN;
997 val |= __SHIFTIN(ilog2(cmd->c_blklen), CFG_BL_LEN);
998 MMC_WRITE(sc, SD_EMMC_CFG, val);
999
1000 cmd->c_resid = cmd->c_datalen;
1001 cmd->c_error = mesongx_mmc_dma_prepare(sc, cmd, cmdflags);
1002 if (cmd->c_error != 0)
1003 goto done;
1004
1005 const bus_addr_t desc_paddr = sc->sc_desc_map->dm_segs[0].ds_addr;
1006 MMC_WRITE(sc, SD_EMMC_START, desc_paddr | START_DESC_BUSY); /* starts transfer */
1007 } else {
1008 MMC_WRITE(sc, SD_EMMC_CMD_CFG, cmdflags | MESONGX_MMC_FLAGS_END_OF_CHAIN);
1009 MMC_WRITE(sc, SD_EMMC_CMD_DAT, 0);
1010 MMC_WRITE(sc, SD_EMMC_CMD_ARG, cmd->c_arg); /* starts transfer */
1011 }
1012
1013 struct bintime timeout = { .sec = 5, .frac = 0 };
1014 const struct bintime epsilon = { .sec = 1, .frac = 0 };
1015
1016 while ((cmd->c_flags & SCF_ITSDONE) == 0 && cmd->c_error == 0) {
1017 error = cv_timedwaitbt(&sc->sc_intr_cv, &sc->sc_intr_lock, &timeout, &epsilon);
1018 if (error != 0) {
1019 cmd->c_error = error;
1020 goto done;
1021 }
1022 }
1023
1024 if (cmd->c_error == 0 && cmd->c_datalen > 0)
1025 mesongx_mmc_dma_complete(sc, cmd);
1026
1027 done:
1028 MMC_WRITE(sc, SD_EMMC_START, 0);
1029
1030 val = MMC_READ(sc, SD_EMMC_IRQ_EN);
1031 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val & ~irq_mask);
1032
1033 sc->sc_cmd = NULL;
1034 cv_broadcast(&sc->sc_intr_cv);
1035
1036 #ifdef MESONGX_MMC_DEBUG
1037 if (cmd->c_error != 0) {
1038 for (u_int reg = 0x00; reg < 0x100; reg += 0x10) {
1039 device_printf(sc->sc_dev, " %02x: %08x %08x %08x %08x\n", reg,
1040 MMC_READ(sc, reg + 0),
1041 MMC_READ(sc, reg + 4),
1042 MMC_READ(sc, reg + 8),
1043 MMC_READ(sc, reg + 12));
1044 }
1045 }
1046 #endif
1047
1048 mutex_exit(&sc->sc_intr_lock);
1049 }
1050
1051 static void
mesongx_mmc_card_enable_intr(sdmmc_chipset_handle_t sch,int enable)1052 mesongx_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
1053 {
1054 struct mesongx_mmc_softc * const sc = sch;
1055 uint32_t val;
1056
1057 mutex_enter(&sc->sc_intr_lock);
1058
1059 val = MMC_READ(sc, SD_EMMC_IRQ_EN);
1060 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val | IRQ_EN_IRQ_SDIO);
1061
1062 mutex_exit(&sc->sc_intr_lock);
1063 }
1064
1065 static void
mesongx_mmc_card_intr_ack(sdmmc_chipset_handle_t sch)1066 mesongx_mmc_card_intr_ack(sdmmc_chipset_handle_t sch)
1067 {
1068 struct mesongx_mmc_softc *sc = sch;
1069
1070 MMC_WRITE(sc, SD_EMMC_STATUS, STATUS_IRQ_SDIO);
1071 }
1072