xref: /netbsd-src/sys/arch/sparc/sparc/memecc.c (revision 5eadbc3ac174cf47c88f8d339df4a13c7a9c5e96)
1 /*	$NetBSD: memecc.c,v 1.18 2021/01/24 07:36:54 mrg Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Paul Kranenburg.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * ECC memory control.
34  */
35 
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: memecc.c,v 1.18 2021/01/24 07:36:54 mrg Exp $");
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 
43 #include <sys/bus.h>
44 #include <machine/autoconf.h>
45 #include <sparc/sparc/memeccreg.h>
46 
47 struct memecc_softc {
48 	bus_space_tag_t		sc_bt;
49 	bus_space_handle_t	sc_bh;
50 };
51 
52 struct memecc_softc *memecc_sc;
53 
54 /* autoconfiguration driver */
55 static void	memecc_attach(device_t, device_t, void *);
56 static int	memecc_match(device_t, cfdata_t, void *);
57 static int	memecc_error(void);
58 
59 CFATTACH_DECL_NEW(eccmemctl, sizeof(struct memecc_softc),
60     memecc_match, memecc_attach, NULL, NULL);
61 
62 int
memecc_match(device_t parent,cfdata_t cf,void * aux)63 memecc_match(device_t parent, cfdata_t cf, void *aux)
64 {
65 	struct mainbus_attach_args *ma = aux;
66 
67 	return (strcmp("eccmemctl", ma->ma_name) == 0);
68 }
69 
70 /*
71  * Attach the device.
72  */
73 void
memecc_attach(device_t parent,device_t self,void * aux)74 memecc_attach(device_t parent, device_t self, void *aux)
75 {
76 	struct memecc_softc *sc = device_private(self);
77 	struct mainbus_attach_args *ma = aux;
78 	uint32_t reg;
79 
80 	if (memerr_handler) {
81 		printf("%s: already attached\n", __func__);
82 		return;
83 	}
84 
85 	sc->sc_bt = ma->ma_bustag;
86 
87 	/*
88 	 * Map registers
89 	 */
90 	if (bus_space_map(
91 			ma->ma_bustag,
92 			ma->ma_paddr,
93 			ma->ma_size,
94 			0,
95 			&sc->sc_bh) != 0) {
96 		printf("memecc_attach: cannot map registers\n");
97 		return;
98 	}
99 
100 	reg = bus_space_read_4(sc->sc_bt, sc->sc_bh, ECC_EN_REG);
101 
102 	printf(": version 0x%x/0x%x\n",
103 		(reg & ECC_EN_VER) >> 24,
104 		(reg & ECC_EN_IMPL) >> 28);
105 
106 	/* Enable checking & interrupts */
107 	reg |= ECC_EN_EE | ECC_EN_EI;
108 	bus_space_write_4(sc->sc_bt, sc->sc_bh, ECC_EN_REG, reg);
109 	memecc_sc = sc;
110 
111 	memerr_handler = memecc_error;
112 }
113 
114 /*
115  * Called if the MEMORY ERROR bit is set after a level 15 interrupt.
116  */
117 int
memecc_error(void)118 memecc_error(void)
119 {
120 	bus_space_handle_t bh = memecc_sc->sc_bh;
121 	uint32_t efsr, efar0, efar1;
122 	char bits[64];
123 
124 	efsr = bus_space_read_4(memecc_sc->sc_bt, bh, ECC_FSR_REG);
125 	efar0 = bus_space_read_4(memecc_sc->sc_bt, bh, ECC_AFR0_REG);
126 	efar1 = bus_space_read_4(memecc_sc->sc_bt, bh, ECC_AFR1_REG);
127 	snprintb(bits, sizeof(bits), ECC_FSR_BITS, efsr);
128 	printf("memory error:\n\tEFSR: %s\n", bits);
129 	snprintb(bits, sizeof(bits), ECC_AFR_BITS, efar0);
130 	printf("\tMBus transaction: %s\n", bits);
131 	printf("\taddress: 0x%x%x\n", efar0 & ECC_AFR_PAH, efar1);
132 	printf("\tmodule location: %s\n",
133 		prom_pa_location(efar1, efar0 & ECC_AFR_PAH));
134 
135 	/* Unlock registers and clear interrupt */
136 	bus_space_write_4(memecc_sc->sc_bt, bh, ECC_FSR_REG, efsr);
137 
138 	/* Return 0 if this was a correctable error */
139 	return ((efsr & ECC_FSR_CE) == 0);
140 }
141