1; Copyright (C) 2021-2022 Free Software Foundation, Inc. 2; 3; This file is part of GCC. 4; 5; GCC is free software; you can redistribute it and/or modify it under 6; the terms of the GNU General Public License as published by the Free 7; Software Foundation; either version 3, or (at your option) any later 8; version. 9; 10; GCC is distributed in the hope that it will be useful, but WITHOUT 11; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 13; License for more details. 14; 15; You should have received a copy of the GNU General Public License 16; along with GCC; see the file COPYING3. If not see 17; <http://www.gnu.org/licenses/>. 18; 19 20; Variables (macros) that should be exported by loongarch.opt: 21; la_opt_switches, 22; la_opt_abi_base, la_opt_abi_ext, 23; la_opt_cpu_arch, la_opt_cpu_tune, 24; la_opt_fpu, 25; la_cmodel. 26 27HeaderInclude 28config/loongarch/loongarch-opts.h 29 30HeaderInclude 31config/loongarch/loongarch-str.h 32 33Variable 34HOST_WIDE_INT la_opt_switches = 0 35 36; ISA related options 37;; Base ISA 38Enum 39Name(isa_base) Type(int) 40Basic ISAs of LoongArch: 41 42EnumValue 43Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100) 44 45 46;; ISA extensions / adjustments 47Enum 48Name(isa_ext_fpu) Type(int) 49FPU types of LoongArch: 50 51EnumValue 52Enum(isa_ext_fpu) String(@@STR_ISA_EXT_NOFPU@@) Value(ISA_EXT_NOFPU) 53 54EnumValue 55Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU32@@) Value(ISA_EXT_FPU32) 56 57EnumValue 58Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64) 59 60m@@OPTSTR_ISA_EXT_FPU@@= 61Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) Init(M_OPTION_NOT_SEEN) Save 62-m@@OPTSTR_ISA_EXT_FPU@@=FPU Generate code for the given FPU. 63 64m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@ 65Target RejectNegative Alias(m@@OPTSTR_ISA_EXT_FPU@@=,@@STR_ISA_EXT_NOFPU@@) 66 67m@@OPTSTR_SOFT_FLOAT@@ 68Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_SOFTF) Negative(m@@OPTSTR_SINGLE_FLOAT@@) 69Prevent the use of all hardware floating-point instructions. 70 71m@@OPTSTR_SINGLE_FLOAT@@ 72Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F32) Negative(m@@OPTSTR_DOUBLE_FLOAT@@) 73Restrict the use of hardware floating-point instructions to 32-bit operations. 74 75m@@OPTSTR_DOUBLE_FLOAT@@ 76Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(m@@OPTSTR_SOFT_FLOAT@@) 77Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. 78 79 80;; Base target models (implies ISA & tune parameters) 81Enum 82Name(cpu_type) Type(int) 83LoongArch CPU types: 84 85EnumValue 86Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE) 87 88EnumValue 89Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64) 90 91EnumValue 92Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464) 93 94m@@OPTSTR_ARCH@@= 95Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPTION_NOT_SEEN) Save 96-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA. 97 98m@@OPTSTR_TUNE@@= 99Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) Init(M_OPTION_NOT_SEEN) Save 100-m@@OPTSTR_TUNE@@=PROCESSOR Generate optimized code for PROCESSOR. 101 102 103; ABI related options 104; (ISA constraints on ABI are handled dynamically) 105 106;; Base ABI 107Enum 108Name(abi_base) Type(int) 109Base ABI types for LoongArch: 110 111EnumValue 112Enum(abi_base) String(@@STR_ABI_BASE_LP64D@@) Value(ABI_BASE_LP64D) 113 114EnumValue 115Enum(abi_base) String(@@STR_ABI_BASE_LP64F@@) Value(ABI_BASE_LP64F) 116 117EnumValue 118Enum(abi_base) String(@@STR_ABI_BASE_LP64S@@) Value(ABI_BASE_LP64S) 119 120m@@OPTSTR_ABI_BASE@@= 121Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_OPTION_NOT_SEEN) 122-m@@OPTSTR_ABI_BASE@@=BASEABI Generate code that conforms to the given BASEABI. 123 124;; ABI Extension 125Variable 126int la_opt_abi_ext = M_OPTION_NOT_SEEN 127 128 129mbranch-cost= 130Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save 131-mbranch-cost=COST Set the cost of branches to roughly COST instructions. 132 133mcheck-zero-division 134Target Mask(CHECK_ZERO_DIV) Save 135Trap on integer divide by zero. 136 137mcond-move-int 138Target Var(TARGET_COND_MOVE_INT) Init(1) Save 139Conditional moves for integral are enabled. 140 141mcond-move-float 142Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save 143Conditional moves for float are enabled. 144 145mmemcpy 146Target Mask(MEMCPY) Save 147Prevent optimizing block moves, which is also the default behavior of -Os. 148 149mstrict-align 150Target Var(TARGET_STRICT_ALIGN) Init(0) Save 151Do not generate unaligned memory accesses. 152 153mmax-inline-memcpy-size= 154Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024) Save 155-mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. 156 157; The code model option names for -mcmodel. 158Enum 159Name(cmodel) Type(int) 160The code model option names for -mcmodel: 161 162EnumValue 163Enum(cmodel) String(@@STR_CMODEL_NORMAL@@) Value(CMODEL_NORMAL) 164 165EnumValue 166Enum(cmodel) String(@@STR_CMODEL_TINY@@) Value(CMODEL_TINY) 167 168EnumValue 169Enum(cmodel) String(@@STR_CMODEL_TS@@) Value(CMODEL_TINY_STATIC) 170 171EnumValue 172Enum(cmodel) String(@@STR_CMODEL_LARGE@@) Value(CMODEL_LARGE) 173 174EnumValue 175Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME) 176 177mcmodel= 178Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) Save 179Specify the code model. 180 181mrelax 182Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION) 183Take advantage of linker relaxations to reduce the number of instructions 184required to materialize symbol addresses. 185 186mpass-mrelax-to-as 187Target Var(loongarch_pass_mrelax_to_as) Init(HAVE_AS_MRELAX_OPTION) 188Pass -mrelax or -mno-relax option to the assembler. 189